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Dica Lab Manual
Dica Lab Manual
LAB MANUAL
(R16 BATCH: 2018-19)
PREPARED BY
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DICA LAB MANUAL
INDEX
EXPERIMENT -1
CIRCUIT DIAGRAM:
TRUTH TABLE:
INPUTS OUTPUTS
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Y0 Y1 Y2 Y3
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 X 0 0 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 0 X X 0 0 1 0
1 1 1 1 1 1 1 1 1 1 1 1 0 X X X 0 0 1 1
1 1 1 1 1 1 1 1 1 1 1 0 X X X X 0 1 0 0
1 1 1 1 1 1 1 1 1 1 0 X X X X X 0 1 0 1
1 1 1 1 1 1 1 1 1 0 X X X X X X 0 1 1 0
1 1 1 1 1 1 1 1 0 X X X X X X X 0 1 1 1
1 1 1 1 1 1 1 0 X X X X X X X X 1 0 0 0
1 1 1 1 1 1 0 X X X X X X X X X 1 0 0 1
1 1 1 1 1 0 X X X X X X X X X X 1 0 1 0
1 1 1 1 0 X X X X X X X X X X X 1 0 1 1
1 1 1 0 X X X X X X X X X X X X 1 1 0 0
1 1 0 X X X X X X X X X X X X X 1 1 0 1
1 0 X X X X X X X X X X X X X X 1 1 1 0
0 X X X X X X X X X X X X X X X 1 1 1 1
PROCEDURE:
1. Assemble the circuit as per the fig: 1.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs as per the truth table
4. Check the logical outputs when LEDs are ON/OFF
PRECAUTIONS:
RESULT:
The 16 x 4 priority encoder using two 8 x 3 priority encoders is designed and its operation is
studied and verified.
INFERENCES:
VIVA QUESTIONS:
1. Explain the purpose of the priority feature in encoders.
2. Give the applications of encoders.
3. Describe the 74LS148 octal to binary priority encoder.
4. Describe the 74HC147 decimal to BCD priority encoder.
EXPERIMENT -2
CIRCUIT DIAGRAM:
TRUTH TABLE:
PROCEDURE:
1. Assemble the circuit as per the fig: 2.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs as per the truth table
4. Check the logical outputs when LEDs are ON/OFF
PRECAUTIONS:
RESULT:
16 bit comparator using 4-bit comparator is designed and its operation is studied and verified.
INFERENCES:
By designing and verifying a 16 bit comparator, it can be understood how large data
comparisons can be accomplished in complicated digital systems.
VIVA QUESTIONS:
EXPERIMENT -3
MODULO 53 COUNTERS USING 2 DECADE COUNTERS
AIM:
Design and verify the function of modulo 53 counter using 2 decade counters
CIRCUIT DIAGRAM:
TRUTH TABLE:
SW CLOCK D7 D6 D5 D4 D3 D2 D1 D0 O/P
Pressed X 0 0 0 0 0 0 0 0 (00)
Released ↓ 0 0 0 0 0 0 0 1 (01)
” ↓ . . . . . . . . .
” ↓ . . . . . . . . .
” ↓ . . . . . . . . .
” ↓ . . . . . . . . .
” ↓ 0 1 0 1 0 0 1 1 (53)
” ↓ 0 0 0 0 0 0 0 0 (00)
PROCEDURE:
1. Assemble the circuit as per the fig: 3.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs as per the truth table
4. Check the logical outputs when LEDs are ON/OFF
PRECAUTIONS:
RESULT:
Modulo 53 counter using 2 decade counters is designed and its operation is studied and
verified.
INFERENCES:
By designing and executing this experiment, one can learn using decade counter (74LS90)
how to design any no. of digits counters which count any events etc
VIVA QUESTIONS:
EXPERIMENT -4
CIRCUIT DIAGRAM:
Fig 4.1: CIRCUIT DAIGRAM OF 450 KHz CLOCK USING NAND GATES
Fig 4.2: CIRCUIT DAIGRAM OF 450 KHz CLOCK USING NOR GATES
DESIGN:
NAND GATE:
RC = 1µsec
Let R=100Ω
C=1/100 µF =0.01µF
R=1K pot
NOR GATE:
Let SW be pressed and capacitor be initially discharged. Let A=0V
RC = 1µsec
Let R=100Ω
C=1/100 µF =0.01µF
R=1K pot
PROCEDURE:
NAND GATES:
1. Assemble the circuit as per the fig: 4.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Observe the output on CRO by adjusting the potentiometer.
4. Check the output clock. It should be 450KHz
NOR GATES:
1. Assemble the circuit as per the fig: 4.2 on the digital IC trainer kit.
2. Switch ON the power supply
PRECAUTIONS:
RESULT:
450 KHz clock using NAND/ NOR gates is designed and its operation is studied and verified.
INFERENCES:
By executing this experiment, one can design low cost clock generator, without using custom
built clock generators which are not economical
VIVA QUESTIONS:
1. What is the principle involved in the design of a clock generator using NAND gate
2. Design a clock generator of frequency 300KHz using NOR gates
3. Give various applications of NAND & NOR gates
EXPERIMENT -5
To design and verify a 4-bit pseudo random sequence generator using 4-bit ring counter
CIRCUIT DIAGRAM:
TRUTH TABLE:
PROCEDURE:
1. Assemble the circuit as per the fig: 5.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs as per the truth table
4. Check the logical outputs when LEDs are ON/OFF
PRECAUTIONS:
RESULT:
4-bit pseudo random sequence generator using 4-bit ring counter is designed and its operation
is studied and verified.
INFERENCES:
VIVA QUESTIONS:
EXPERIMENT -6
CIRCUIT DIAGRAM:
TRUTH TABLE:
S3 S2 S1 S0 O/P
Y
0 0 0 0 I0
0 0 0 1 I1
0 0 1 0 I2
0 0 1 1 I3
0 1 0 0 I4
0 1 0 1 I5
0 1 1 0 I6
0 1 1 1 I7
1 0 0 0 I8
1 0 0 1 I9
1 0 1 0 I10
1 0 1 1 I11
1 1 0 0 I12
1 1 0 1 I13
1 1 1 0 I14
1 1 1 1 I15
PROCEDURE:
1. Assemble the circuit as per the fig: 6.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs as per the truth table
4. Check the logical outputs when LEDs are ON/OFF
PRECAUTIONS:
RESULT:
INFERENCES:
One can use these devices in various electronic communication systems (digital), real time
embedded system where multiple data processing is needed.
VIVA QUESTIONS:
EXPERIMENT -7
To design and verify a 16 bit adder/ subtractor using 4-bit adder/ subtractor ICs
CIRCUIT DIAGRAM:
TRUTH TABLE
FUNCTION:
Mode: 0 Addition
Mode: 1 Subtraction
Theory:-
IC 7483 is a 4 bit parallel adder which consists of four interconnected full adders along with
the look ahead carry circuit. Here we are constructing the 16 bit adder/subtractor by
cascading the four 7483 ICs.
16 BIT ADDER :
A15A2A1A0 is a 4 bit input word 'A' and B15B2B1B0 is the second 4 bit input word 'B'. Cin0
is the input carry. The IC adds the 4 four bit words along with input carry to produce a 4 bit
sum and a one bit carry-out. Cout3 represents the output carry. S3,S2,S1,S0 represents sum
output with S3 as the MSB.In odrder to design an 8 bit adder, we require two IC 7483s
cascaded as shown in the figure above.
As with the binary adder, we can also have n number of 1-bit full binary subtractor connected
or “cascaded” together to subtract two parallel n-bit numbers from each other. For
exampletwo 4-bit binary numbers. We said beforethat the only difference between a full
adder and a full subtractor was theinversion of one of the inputs.So by using an n-bit adder
and n number of inverters (NOT Gates), the process ofsubtraction becomes an addition as we
can use two’s complement notation on allthe bits in the subtrahend and setting the carry input
of the least significant bit to alogic “1” (HIGH).Then we can use a 4-bit full-adder ICs such
as the 74LS283 and CD4008 toperform subtraction simply by using two’s complement on the
subtrahend, Binputs as X – Y is the same as saying, X + (-Y) which equals X plus the
two’scomplement of Y.
PROCEDURE:
Procedure:-
Adder:
1. Apply the inputs A0-A15 and B0-B15 along with carry.
2. And observe S0-S15 and Cout.
Subtractor:
1. Apply the inputs A0-A15 and B0-B15 through not gates
PRECAUTIONS:
RESULT:
A 16 bit adder/ subtractor using 4-bit adder/ subtractor ICs is designed and its operation
is studied and verified.
INFERENCES:
It is understood that the dual function of both addition and subtraction can be implemented
with a simple addition of exclusive OR gates.
VIVA QUESTIONS:
1. How do you expand the 4-Bit adder to accomplish 8-Bit and 16-Bit addition
2. Explain method used for fast addition
3. Describe 74LS182 look ahead carry
4. Explain the working of N-Bit subtractor with the help of neat block diagram
EXPERIMENT -8
THEORY:
Inputs 'float' high to logic 1 if unconnected, but do not rely on this in a permanent
(soldered) circuit because the inputs may pick up electrical noise. 1mA must be
drawn out to hold inputs at logic 0. In a permanent circuit it is wise to connect any
unused inputs to +Vs to ensure good immunity to noise.
Outputs can sink up to 16mA (enough to light an LED), but they can source only
about 2mA. To switch larger currents you can connect a transistor.
Fan-out: one output can drive up to 10 74LS inputs, but many more 74HCT inputs.
Gate propagation time: about 10ns for a signal to travel through a gate.
Frequency: up to about 35MHz (under the right conditions).
Power consumption (of the IC itself) is a few mW.
FIG 8.1: CIRCUIT DIAGRAM OF 74LS04: FIG 8.2: TRANSFER CHARACTERSISTICS OF 74LS04:
FIG 8.3: CIRCUIT DIAGRAM OF 74H04: FIG 8.4: TRANSFER CHARACTERSISTICS OF 74H04:
FIG 8.5: CIRCUIT DIAGRAM OF 74HS04: FIG 8.6: TRANSFER CHARACTERSISTICS OF 74HS04:
PROCEDURE:
74LS04:
1. Assemble the circuit as per the fig: 8.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the input voltage = 0 and note down the output.
4. Repeat step 3 for input voltages = 1V,2V,3V,4V,5V and note down the corresponding
outputs
74H04:
1. Assemble the circuit as per the fig: 8.3 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the input voltage = 0 and note down the output.
4. Repeat step 3 for input voltages = 1V,2V,3V,4V,5V and note down the corresponding
outputs
74HS04:
1. Assemble the circuit as per the fig: 8.5 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the input voltage = 0 and note down the output.
4. Repeat step 3 for input voltages = 1V,2V,3V,4V,5V and note down the corresponding
outputs
OBSERVATIONS:
74LS04:
74HC04:
74HS04:
PRECAUTIONS:
RESULT:
The transfer characteristics of 74H, LS, HS series ICs are studied, observed, and verified.
INFERENCES:
The difference among 74H, LS, & HS series ICs is understood and also the applications of
HCT series is understood which is popularly used nowadays.
VIVA QUESTIONS:
EXPERIMENT -9
CIRCUIT DIAGRAM:
Fig 9.1: CIRCUIT DAIGRAM OF 4-BIT BINARY AND BINARY TO GRAY CONVERTER
TRUTH TABLE:
PROCEDURE:
1. Assemble the circuit as per the fig: 9.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs as per the truth table
4. Check the logical outputs when LEDs are ON/OFF
PRECAUTIONS:
RESULT:
A 4-bit gray to binary and binary to gray converter is designed and its operation is studied
and verified.
INFERENCES:
The applications of code converters, especially binary to gray conversion are understood. The
use of binary to BCD code converter is also understood.
VIVA QUESTIONS:
EXPERIMENT -10
CIRCUIT DIAGRAM:
Fig 10.1: CIRCUIT DIAGRAM OF 2 DIGIT SEVEN SEGMENT DISPLAY USING THE
DISPLAY MODE COUNTER
TRUTH TABLE:
PROCEDURE:
1. Assemble the circuit as per the fig: 10.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs from the modulo 53 counter as shown in the truth table
4. Check the output on 7-segment display.
PRECAUTIONS:
RESULT:
A 2 digit seven segment display using the display mode counter of experiment 3 is designed
and its operation is studied
INFERENCES:
The decimal counter outputs can be well visualized with the help of 7-segment modules.
VIVA QUESTIONS:
EXPERIMENT -11
To design an 8-bit parallel load and serial out shift register using two 4-bit shift registers
CIRCUIT DIAGRAM:
Fig 11.1: CIRCUIT DAIGRAM OF 8-BIT PARALLEL LOAD AND SERIAL OUT
SHIFT REGISTER
FUNCTION TABLE:
PROCEDURE:
1. Assemble the circuit as per the fig: 11.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs as per the function table.
4. Check the logical outputs when LEDs are ON/OFF
PRECAUTIONS:
RESULT:
An 8-bit parallel load and serial out shift register using two 4-bit shift registers is designed
and its operation is studied
INFERENCES:
The parallel load and serial out shift register can be used in interfacing BCD switch which
has 4 bit data. This 4-bit data can be read serially using only three signals which save the
input output ports when interfacing with microcontrollers.
VIVA QUESTIONS:
EXPERIMENT -12
To design an 8-bit serial in and serial out shift register using two 4-bit shift registers
CIRCUIT DIAGRAM:
Fig 12.1: CIRCUIT DAIGRAM OF 8-BIT SERIAL IN AND SERIAL OUT SHIFT
REGISTER
FUNCTION TABLE:
PROCEDURE:
1. Assemble the circuit as per the fig: 12.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs as per the function table
4. Check the logical outputs when LEDs are ON/OFF
PRECAUTIONS:
RESULT:
An 8 -bit serial in and serial out shift register is designed using two 4-bit shift registers and its
operation is studied
INFERENCES:
To interface multiple BCD switches, cascading of shift register, the data can be read with the
help of serial in and serial out option in the shift register.
VIVA QUESTIONS:
EXPERIMENT -13
AIM:
To design a ring counter and twisted ring counter using a 4-bit shift register
A. RING COUNTER
CIRCUIT DIAGRAM:
TRUTH TABLE:
PROCEDURE:
1. Assemble the circuit as per the fig: 13.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs as per the truth table
4. Check the logical outputs when LEDs are ON/OFF
CIRCUIT DIAGRAM:
TRUTH TABLE:
PROCEDURE:
1. Assemble the circuit as per the fig: 13.2 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs as per the truth table
4. Check the logical outputs when LEDs are ON/OFF
PRECAUTIONS:
RESULT:
A ring counter and twisted ring counter is designed using a 4-bit shift register and its
operation is studied
INFERENCES:
One can use ring counters in hardware logic design (e.g. ASIC and FPGAdesign) to
create complicated finite state machines.
One can use Johnson or Twisted Ring Counters as:
1) Divider of clock inputs by varying their feedback loops.
2) A 3-stage Johnson Ring Counter could be used as a 3-phase, 120 degree phase shift
square wave generator.
3) A stepper motor controller.
VIVA QUESTIONS:
EXPERIMENT -14
AIM:
To design a 4 digit hex counter using synchronous one digit hex counter
CIRCUIT DIAGRAM:
TRUTH TABLE:
PROCEDURE:
1. Assemble the circuit as per the fig: 14.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs as per the truth table
4. Check the logical outputs when LEDs are ON/OFF
PRECAUTIONS:
RESULT:
A 4 digital hex counter is designed using synchronous one digital hex counter and its
operation is studied
INFERENCES:
We can use synchronous hex counters in fast counting applications but the clock signal may
be loaded.
VIVA QUESTIONS:
EXPERIMENT -15
AIM:
To design a 4 digital hex counter using asynchronous one digit hex counter
CIRCUIT DIAGRAM:\
FUNCTION TABLE:
PROCEDURE:
1. Assemble the circuit as per the fig: 15.1 on the digital IC trainer kit.
2. Switch ON the power supply
3. Apply the logic inputs as per the truth table
4. Check the logical outputs when LEDs are ON/OFF
PRECAUTIONS:
RESULT:
A 4 digital hex counter is designed and using asynchronous one digit hex counter and its
operation is studied
INFERENCES:
The asynchronous hex counters can be used in applications where loading of clock signals
should be avoided. But these are used in low speed applications.
VIVA QUESTIONS:
APPENDIX
I. DATASHEET OF 74LS148
V. DATASHEET OF 74LS02
X. DATASHEET OF 74LS47
REFERENCES