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    Pasupuleti Venkata Ramana
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    6 views2 pages

    3 RD Unit 2 Mrks

    Uploaded by

    Pasupuleti Venkata Ramana

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
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    of 2
    c Np Los! piorraL suectROMCe= OLUTIONS | = ons with 5! 7 svdel of ASM DAH i Sen ~ART-A SHORT ques’ QI. Define state diagram. Ans: mode! Papers. aH sxpresentation of the performance of shown in figure below Figure Define state reduction. a2, Ans: The process of eliminating the redundant number of states from the state diagram by keeping external input-output requirements unmodified is called as state reduction. Q3. Define finite state machine. Ans: Finite state machine is a model which is used to describe the synchronous sequential machine, It isa machine with a fixed mumber of siates Q4. Define Mealy and Moore machine. Ans: Mealy Machine ‘A sequential circuit whose output depends on both present state and present input is termed as Mealy machine or Mealy circuit, Moore Machine A sequential circuit whose output depends only on Present state of the flip-flop is termed as Moore machine, Q5. Define ASM chart, List its three basic elements. Model Paper-2, 1() DESION [JNTU-ANAy, SP eweral ay, | Thee te, A jay pn Figure: Goveral Model of RSM Chant Ge. Differentiate between 8” ASM char, i A conventional flow chart. ans: Conventional flow shart provides 1 descrip timing relationship between procession of procedyn and the decision paths. Whereas ASM charts provi, ¢ along with the timing relationship of sega. sequen : controller state and the events oceurred on traveling fog, state to another state. 7. How are the Mealy type outputs ang oF ype outputs indicated in an ASM chart The Mealy type outputs in an ASM chart are india inthe conditional output boxes whereas the Moot type tap, jin_the state box of the ASM chart An: An Algorithmic State Machine (ASM) chart is a special type of flow chart which provides the design and realization of digital hardware systems, are indicated Whatis shift register? Give the classificatiqn them. Mosel Paper’, (on) Define a shift register. ‘May! June-48, (Ri2\ reason) Ans: Shift Register = A register capable of shifting its binary information! ‘one or both directions is called a shift register. Shift gst The components of ASM chart are, 1, State box ‘consists of a chain of flip-flops which is caseaded with ow) ee peciacn tax ‘of one fli flop connected to the input of the next bee 3. Conditional output box. apes ee ets PF warnne: xecuPhoiocopyig this ook it inna 2 Aayne ood pts BLE t 6 LEGAL proces. | Fila Serial -O shi rep or They ae, #e° [SIS0) ‘i jn Parallel - Out 94 a das ser! MM register) Ana: Aon, Yo) peal “18 PAH -Owshinegee eel Wl id in eSedalsOuain get PPO acl ill restr Wer PIs 9) pone COUNEETS. ANA Give tg <2) ications, a f sequential CCU Which suns «inown 25 “counter gion of Counter’ the numberof clog feat ie ces 0 for fons in cate oF AECUSGF And ace empeay n oe : "vent ‘A counter is a register used for counting the number of nial spk pulses atits clock input in a specific sequence. It can be ‘one (fed stored or incremented and can actas a program counter, — | Gif what arethe drawbacks of ripple counters? ore (Model Paper-2, Q1(0) | Now/Dec-18, (R15), a(n) “The main drawbacks of ripple counters are, ‘As the number of bits increase, the number of flip flops jnereases. This makes the counting function to be too Ans: slow. i ‘ ; ‘The propagation delay ‘time increases due to transition i an ‘at the output of previous flip flop. 12. Define modulus of a counter. | ‘Ans: ost. gubogen ir | : f st unter is referred a5, ‘The number of states in the counter is referred ‘modulus eeepc The! ‘ofan-bit counteris given % Pim e : eit Binary Counter hs nary seca ecucncs tes of Tos orninary Core 2, a SyHchronous binary up-down counter. & Define ring counter. si Ans: counter are pascal’! fositied ino ino een vera. ‘9p. They | igs ECM ao known as cea si eit counter Syne soul the quence of operation of Sigal ys synchronous 3 Wing timing signals tn he counter out ofeach abe nected to the‘inpu of the successive stage. The output OF een en Sy oe ca ear ee | ee ee c aren yess cute awn Wises bina

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