Conditional-store instruetions

Software-programmable wait-state generator

Programmable bank switching

Power consumption control ructions 1or power.

with IDLEI, IDLE 2, and IDILE 3 instructions for ne

down modes

5.8.2 Architecture of TM5320C54X

Program Address Data Address

System Control Generation Generation
interface Logic (PAGEN) Logic (DAGEN)
ARAUO, ARAU1
PC, IPTR,RC ARO AR7
BRC, RSA, REA LARP BK DE.^P

PAB
PB Memory
and
CAB External
Interface
CB

DAB
DB Peripheral
Interface
EAB
EB
EXP
Ençoder

MUX
T registe

D
Sign ct Sign cy A40) B40 Signc t Sign ctr/ Sign ct7
Multiplier (17x 17) MUX Barrel
ALU (40) Shifter
B
Fractional MUX7 Legend
AAccumulator A
BAccumulator B
MLUX
C CB Data Bus
Adder(40) D DB Data Bus MSWLSW
E EB Data Bus COMP Select
M MAC Unit
L ZERO SAT ROUND P PB Program Bus LTRN
S Barrel Shifter
TTRegister
LTC
UALU

Fig. 5.8
Digitai D g u

The architecture is built around 25

The program bus (PB) carries
eight major 16-bit buses
the
Three cdata buses (CB, DB, instruction code and immediate
memory. Three
and EB) operands from program
address generation logie. program
data a interconnect to various
address
various elements, such as the
CPU,
w. The
memory. CB and DB
carry the generation logic, on-chip peripherals, and data
ta be written to memory. operands that are read from data
Four address buses (PAB, memory. The EB carries the
needed for instruction execution. CAB, DAB, and EAB) carry the
addresses
The '54x can
generate up to two
register arithmetic units (ARAU0 and
data-memory addresses per cycle using the two
ARAUI). auxiliary
Internal Memory Organization
The 54x memory is
organized into three individually selectable spaces: program, data, and
snace. All "54x devices contain both
random-access memory (RAM) and
ROM). Among the devices, two
types of RAM read-only memory
and single-access RAM
are
represented: dual-access RAM (DARAM)
(SARAM).
On-Chip ROM

The on-chip ROM is part of the program memory space and,

in some cases,
memory space. On devices with a small amount part of the data
of ROM (2K words), the ROM contains a bootloader
that is useful for booting to faster
on-chip or external RAM. On devices with larger amounts of
ROM, portion of the ROM may be mapped into both data and
a
program space.
On-Chip Dual-Access RAM (DARAM)
The DARAM iscomposed of several blocks. Because each DARAM block can be accessed
twice per machine cycle, the central processing unit
(CPU) and peripherals such as the buffered
serial port (BSP) and host port interface (HPI) can read from and write to a DARAM memory
address in the same cycle.
On-Chip Single-Access RAM (SARAM)
The SARAM is composed of several blocks. Each block is accessible once per machine
cycle for either a read or a write. The SARAM is always mapped in data space and is primarily
intended to store data values.

On-Chip Memory Security

he '54x maskable memory security option protects the contents
of on-chup memories

Memory-Mapped Registers
tor the CPU and the on-chip
ne data memory space contains memory-mapped registers
access to them. The memory-
pherals. These repgisters are located on data page 0, simplitying
and restore the regsters for context switches
Pped access provides a convenicnt way to save
and the other registers.
dtO transfer information between the accumulators
 gnal Processors
Select, and Store Unit 5.27
(CSSU)
Compare,

The compare, select, and store unit

(CSSU)
nnlator's high and loW Word, allows both the performs maximum comparisons between the
ccumula
test/control flag bit (TC) in status register STO
he
and transition register (TRN) to keep their transition
the transit

umulator to store into data memory. histories, and selects the larger word in the

Dota Addressing

The "54x offers seven basic data

addressing modes:
Immediate addressing uses the instruction to encode a fixed value. Absolute addressing
uses the instruction to encode a fixed address.
Accumulator addressing uses accumulator Ato access a location in program memory
as data.

Direct address'ng uses seven bits of the instruction to encode the lower seven bits of an
address. The seven bits are used with the data page pointer (DP) or the stack pointer
(SP) to determine the actual memory address.
Indirect addressing uses the auxiliary registers to access memory.
Memory-mapped register addressing uses the memory-mapped registers
modifying either the current DP value or the current SP value.
stack.
Stack addressing manages adding and removing items from the system
Program Memory Addressing
With
addressed on a '54x device with the program counter (PC).
Program Memory is usually access data items that have been
Some instructions, however,
absolute addressing may be used to

stored in program memory.

Pipeline Operation that occur during the

execution of
consists ofa sequence of operations
An instruction pipeline read, and execute.

six levels: prefetch,

fetch, decode, access,
has
instruction. The '54x pipeline
independent.
an are
occurs. Because these operations
operation different stage of
Al each ofthe levels, an independent
be active in any given cycle, each
instruction at a

of the six
instructions, each at
one
One to six instructions can set of
is full with a sequential
npletion. Typically, the pipeline
stages.
connected to
On-Chip Peripherals diflerent on-chip
peripherals are

CPU, but
the '54x devices
have the same

A peripheral options
'54x devices have these on-chip
Ir
CPUs The
Software-programmable wait-state generator

Programmable bank-switchin8
 5.28 Digital Signal Processin
Parallel /0 ports
DMA controller
Host-port interface (standard 8-bit, enhanced 8-bit, and 16-bit)
Serial ports (standard, TIDM. BSP, and McBSP)
General-purpose I/O pins
16-bit timer with 4-bit prescaler
Phase-lockcd loop (PLL) clock generator
General-Purpose 1/O Pins
Each 54x device has two
be used to
general-purpose 1/O pins: BIO and XE. BIO 1s an input pin that can
monitor the status of
you to signal external devices.
external devices. XF is a software-controlled output pin that allowcan

Software-Programmable Wait-State Generators

The
to
software-programmable wait-state
interface with slower generator can be used to
extend external bus
off-chip memory and 1/0 devices. The software wait-state cycles
incorporated without any external hardware. For generator is
can be off-chip memory access, a number
of wait states
specified for every 32K-word block of program and data
word block of 1/O memory space, and for one 64K
space within the software wait-state
register
Programmable Bank-Switchingg
Programmable bank-switching can be used to insert one
memory-bank boundaries inside program memory or data cycle automatically when erossing
memory space.
Parallel 1/O Ports
Each '54x device has a total of
64K I/0 ports. These
instruction or the PORTW instruction. ports can be addressed by the PORTK
Direct Memory Access (DMA) Controller
The 54x direct
memory access (DMA) controller
map without intervention by the transters data between points in the memory
CPU. The DMA allows movements of data
program/data memory, internal peripherals (such as the to and from interna
occur in the
background of CPU operation. McBSPs), or external memory devices t
The DMA has the
following features:
The DMA
operates independently of the CPU
The DMA has six
channels. The DMA can
block transfers. keep track ofthe contexts of six
indepenaedent
The DMA has
higher priority than the CPU for both
internal and external accesse
 Digtal ignal Proc8sing
Centrel Processing Unlt (CPU)

he $4N CPL iscomnmm to all the 'S4x devioes.

The '54x CPU contains: 40-bitsrithmetic legie
40-bit adder Compnre,
mt (ALU) wo 40-bit aveumulators
Harel shifter 17 17-bit multiplier
x

unit
unit Program address generation
welevt, and storv unit ((CSSU) Data addrens generation
Arithmetle Logle Unt (ALU)
nrithmetie with a 40-bit arithmetic logic
unit (ALU) and
The S4x performs 2s-complement
Hoolean operations
wo 40-bit accumulators
(aceumulators A and B). TheALU Can also performn
wordfrom data memory 16-bit value
inputs: 16-bit immediate value 16-bit
ThçALU usesthese 32-bit word from data memory
the register, T Two 16-bit words from data memory
in temporary
40-bit word from cither accumulator

Accumulators
ALU the multiplier/adder block. They can
A and B store the output from the
or
Accumuiators

to the ALU; accunulator Acan be an input to the multiplier/adder. Each

also prvide a second input
aocumulator is divided intothree parts:
Guard bits (bits 39 32)

High-order word (bits 31-16)

Low-orderword (bits 15-0)
bits, for storing the high- and the low-order
Instructions are provided for storing the guard
transferring 32-bit accumulator
words in or out of data
accumulator words in data memory, and for

emory

Borrel Shifter
connected to the accumulators or to data memory
The "54x barrel shifter has a 40-bit input
memory (using EB).
The
(using CB or DB), and a 40-bit output connected to the ALU or todata
to 31 bits and a right shift to 16 bits on the input data.
of O
barrel shifter can produce a left shift of 0
normalize the values in an accumulator in a single
The barrel shifter and the exponent encoder
MSBs can be either zero filled or sign
cycie.The LSBs of the output are filled with Os, and the
mode bit (SXM) in STL.
extended, depending on the state of the sign-extension

Multiplier/Adder Unit
with a 40-bit addition
The multiplier/adder unit perfoms 17X17-bit 2s-complement multiplication
instruction cycle. The multiplier/adder block consists ofseveral
elements: a multiplier, an
in a
single
adder, signed/unsigned input control logie, fractional control logic, a detector, a rounder (s
zero

complement), overflow/saturation logic,and a l6-bit temporary storage register (T). The multiplier
has two inputs: one input is selccted from T, a data-memory operand, or aecumulator A; the other

is selected from program menmory, data memory, accumulator A, or an immmediate value.

 Rach ohannel has
independently programnable priorities
ach channel's source and
through menmory on each renddestination address registers can have
and write configurable inddexes
eonstant. postinerement, transfer, respectively. address may remain
The
postdecrement, or be
adjusted by a progranmable value,
Each read or write transfer
may be initialized by selected
events.
On completion
of a half-block or full-block
interrupt to the CPU. transfer, ench DMA channel may send an

On-chip-RAM-to-off-chip-memory
memory-to-on-chip-RAM DMA
DMA transfer
requires 5
cycles while off-chip
transfer requires 5 cycles.
The DMA can perform
double-word transfers (a 32-bit transfer of two 16-bit
Host-Port Interface (HP) words)
The host port interface (HPI) is a parallel port that
Infomation is exchanged between the '54x and the host provides an interface to a host processor.
that is accessible to both the processor through "54x on-chip memory
host processor and the '54x.
Program Control

Program control is provided by several hardware and software mechanisms:

The program controller decodes
instructions, manages the pipeline, stores the status of
operations, and decodes conditional operations. Some of the hardware elements included
in the program controller are the
program counter, the status and control register, the
stack, and the address-generation logic.
Some of the software mechanisms used for
program control include branches, calls.
conditional instructions, a repeat instruction, reset, and
interrupts.
The S4x supports both the use of hardware and software interrupts for
program control.
Stotus Registers (STO, ST1)
the status registers, STO and STI, contain the statusofthe various conditions and modes for
Ue
54xdevices. STO contains the flags (Ov,C, and TC) produced by arithmetic operations and bit
pulations in addition to the data page pointer (DP) and the auxiliary register pointer (ARP)
fields
Auxdiliary Registers (ARO-AR7)
Theeight 16-bit auxiliary registers (ARO-AR7) can be accessed by the central airthmetie
gCunit(CALU)and modified by the auxiliary register arithmetie units(ARAUS).
Temporary Register (TREG)
and multiply/accumulate
The TREG is used to hold one of the multiplicands for multiply
shift count for instructions with
(execution-time programmable)
instructions. It can hold a dynamic
a shift operation such as ADD,
LD, and SUB.

Transition Register (TRN)

decision for the path to new
that is used to hold the transition
The TRN is 16-bit
a register and store) instruction
The CMPS (compare, select, max,
metrics to perfom the Viterbi algorithm.
updates the contents of the TRN

Stack-Pointer Register (SP)

address at the top of the system stack. The SP
The SP is a 16-bit register that contains the
onto the stack. The stack is manipulated by interrupts,
always points to the last element pushed
and POPM instructions.
returns, and the PUSHD, PSHM, POPD,
traps, calls,
Circular-Buffer-Size Register (BK)
the data block size.
The 16-bit BK is used by the ARAUs in circular addressing to specify
Block-Repeat Registers (BRC, RSA, REA)
specify the number of times
The block-repeat counter (BRC) is a 16-bit register used to
a

block of code is to be repeated when performing a block repeat.

Interrupt Registers (IMR, IFR)

The interrupt-mask register (IMR) is used to mask off specific interrupts individually at required
times. The interrupt-flag register (IFR) indicates the current status ofthe interrupts

Processor-Mode Status Register (PMST)

The processor-mode status register (PMST) controls memory configurations of the "54x
devices.
Power-Down Modes
Thereare three power-down modes, activated by the IlDLEI, IDLE2, and IDLE3 instructions.
In these modes, the "54x devices enter a dormant state and dissipate considerably less power than
in normal operation. The IDILEI instruction is used to shut down the CPU. The IDLE2 instruction
is used to shut down the CPU and on-chip peripherals.

Bus Structure
The '54x device architecture is built around eight major 16-bit buses:

One program-read bus (PB) which carries the instruction code and immediate
operands
from program memory

Two data-read buses (CB, DB) and one data-write bus (EB), which interconnect to