Barisal Information Technology College (BITC) Assignment Title: Computer Architecture & Computer System Course Name: Computer Organization and Architecture Course Code: 520205 Submitted To Md. Nazmul Hasan Lecturer, Department of Computer Science & Engineering (CSE). Submitted By No. Name Registration No. Signature 1. Kazi Tamanna Alam 19502003465 2. Khadija Tul Kobra 19502003458 3. Methila Sarker 19502003442 4. Anik Samaddar 19502003450 E. MD Nidul Sarder 19502003449 6. Debobrata Das 195020034331. What is system bus? Describe different types of system bus. Ans: System bus: A system bus is a single computer that connects the major components of a computer system, combining the functions of a data bus to carry information, an address bus to determine where it should be sent, and a control bus to determine its operation. Types of system bus: i & There are three types of system bus- 1. Control bus 2. Address bus 3. Data bus. 1. Control bus A control bus is a computer bus that is used by the CPU to communicate with devices that are contained within the computer. This occurs through physical connections such as cables or printed circuits. 2. Address busAn address bus is a computer bus architecture used to transfer data between devices that are identified by the hardware address of the physical memory (the physical address), which is stored in the form of binary numbers to enable the data bus to access memory storage. 3. Data bus A data bus is a system within a computer or device, consisting of a connector or set of wires, that provides transportation for data. 2. Architecture of Local, PCI and Service bus. Ans: Architecture of local bus:Architecture of PCI bus: Sos] (ess 3. What is interrupt? Describe types of interrupt. Ans: Interrupt: The interrupt is a signal emitted by hardware or software when a process or an event needs immediate attention. It alerts the processor to a high-priority process requiring interruption of the current working process. In I/O devices one of the bus control lines is dedicated for this purpose and is called the Interrupt Service Routine (ISR).Types of Interrupts: Generally, there are three types of Interrupts those are occurred for example 1. Internal Interrupt. 2. Software Interrupt. 3. External Interrupt. Internal Interrupts The Internal Interrupts are those which are occurred due to Some Problem in the Execution for Example When a user performing any Operation which contains any Error and which contains any type of Error. So that Internal Interrupts are those which are occurred by the Some Operations or by Some Instructions and the Operations those are not Possible but a user is trying for that Operation. Software Interrupts Software Interrupts are those which are made some call to the System for Example while we are Processing Some Instructions and when we want to Execute one more Application Programs. External Interrupt The External Interrupt occurs when any Input and Output Device request for any Operation and the CPU will Execute those instructions first For Example When a Program is executed and when we move the Mouse on the Screen then the CPU will handle this External interrupt first and after that he will resume with his operation. 4. Briefly discuss about addressing mode. Ans: Addressing Mode The addressing mode is the method to specify the operand of an instruction. The job of a microprocessor is to execute a set of instructions stored in memory to perform a specific task. Operations require the following:1. The operator or opcode which determines what will be done 2. The operands which define the data to be used in the operation Types of Addressing Modes: 1. Immediate With immediate addressing mode, the actual data to be used as the operand is included in the instruction itself. Let's say we want to store operand 1 into a register and then add operand 2. With immediate addressing mode, the data values 1 and 2 would be part of the instruction itself as shown below. add $10,$8,2 This would be a relatively fast option since there is no memory access required to get the operand. The operand, however, is limited to the size of one word 2. Direct Addressing When using direct addressing mode, the address of the operand is specified in the instruction. The processor will retrieve the data directly from the address specified in the instruction. In this figure, the example shows how the instruction tells the processor where to get the data from in memory. The variable addr_of_2is a pointer to the effective address of the operand. lw $11, addr_of_2 There are no calculations required to retrieve the operand since the effective address (the address of the operand) is addressed directly. Like immediate addressing mode, the operand is limited to the size of 1 word (8 or 16 bits). 3, Register AddressingRegister addressing mode indicates the operand data is stored in the register itself, so the instruction contains the address of the register. The data would be retrieved from the register. Here's how this would work: add $12, $11, $10 Retrieving data from the register is fast and the instructions are shorter because no memory is involved. 5. Discuss about register addressing mode. Ans: Register addressing mode: The instruction is said to be have an addressing mode that specify two registers that exist one op-code another is operand. Example: ADD A, RS (The instruction will do the addition of data in Accumulator with data in register R5) 6. Discuss about relative addressing mode. Ans: Relative addressing mode: Relative addressing is the technique of addressing instructions and data areas by designating their location in relation to the location counter or to some symbolic location. We can classify the Relative Addressing Mode into three of the following types: Program Counter or PC Relative Addressing Mode. Base Register Addressing Mode. Indexed Addressing Mode or Index Register Relative Addressing Mode.Set-1 1. Define computer architecture. Explain Von Neumann architecture with diagram. Or, Explain the functional view of a computer. (2019) Ans: Computer architecture Computer architecture can be defined as a set of rules and methods that describe the functionality, management and implementation of computers. Von Neumann architecture Von Neumann architecture was first published by John von Neumann in 1945. His computer architecture design consists of a Control Unit, Arithmetic and Logic Unit (ALU), Memory Unit, Registers and Inputs/Outputs. Von Neumann architecture is based on the stored-program computer concept, where instruction data and program data are stored in the same memory. This design is still used in most computers produced today. Yon Neumann Memory ate Stuctre ‘arithmetic = control F-——=>| gic Unit a PO Processor AccumulatorFunctional view of a computer: In general terms, there are four main functions of a computer- * Data processing © Data storage © Data movement © Control Functional view of a computer- Prev Processing Facility3. Distinguish between computer architecture and computer organization. (2018 Ans: called Instruction Set Architecture (ISA). S!_|Computer architecture | computer organization No. L Computer Architecture deals ‘Computer Organization deals with a with the functional behavior of _| structural relationship. computer systems. a Architecture indicates its Where Organization indicates its hardware. performance. 3. For designing a computer, its For designing a computer, an architecture is fixed first. organization is decided after its architecture. 4. Computer Architecture is also Computer Organization is frequently called microarchitecture. 5. _ | It makes the computer's hardware visible. It offers details on how well the computer performs. The different architectural categories found in our computer systems are as follows: 1. Von-Neumann Architecture 2. Harvard Architecture 3. Instruction Set Architecture Micro-architecture 5. System Design CPU organization is classified into three categories based on the number of address fields: 1. Organization of a single Accumulator. 2. Organization of general registers 3. Stack organization4. Draw the block diagram of IAS computer and mention the function of resister. Ans: Function of the registers as follows: Memory Buffer Register (MBR): MBR is a two-way register that holds the data fetched from memory and ready for the CPU to process or the data waiting to be stored in memory. Memory Address Register (MAR): MAR specifies the address in memory of the word to be written from or read into the MBR. Instruction Register (IR): IR contains the 8-bit op-code instruction being executed. Instruction Buffer Register (IBR): IBR is employed to hold temporarily the right- hand instructions from a word in memory. Program Counter (PC): PC is an counter that contains the address of the next instruction-pair to be fetched from memory to be executed.Accumulator (AC) and Multiplier Quotient (MQ): AC and MQ are employed to hold temporarily operands and results of ALU operations. 5. What are the characteristic of a good instruction format? (2018,2020) Ans: An instruction formats defines the logout of the bits of an instruction in terms of it constituent parts. As instruction format- © Must explicit operand is referenced using one of the addressing modes. ‘© Must implicitly or explicitly, indicate the addressing mode for each operand. The most basic design issue to be faced is the instruction format length. This decision effects and is affected by memory size, memory organization, bus instruction, CPU complexity and CPU speed. The other issue is allocating the bits in that format. The tread of here is complex. Given instruction length, there is clearly a tread-off between the number of op-codes and the power of the addressing capability. The following interrelate factors go into determining the use of the address bits. © Number of operands. ‘© Register versus memory. * Number of register sets. * Address range. © Address granularity, 6. Define Addressing Mode. Discuss about direct, relative, register addressing mode? Ans:Addressing Modes The term addressing modes refers to the way in which the operand of an instruction is specified. The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually executed. Types of Addressing Modes 1. Direct Addressinj (ercoad tress A (i) Address field contains address of operand. (ii) Effective address (EA) = address field (A) (iii) e.g ADDA -Add contents of cell A to accumulator -Look in memory at address A for operand. (iv) Single memory reference to access data. {v)_No additional calculations to work out effective address. (vi) Limited address space. 2.Relative addressing mode:fopcodeRegiterR] Address A Memory Regions | pointer to Opernd| {| operand Fe Relate adding de A= contents of an address field in the instruction R = contents of an address field in the instruction that refers to a register Relative addressing, also called pc- relative addressing, the implicitly referenced register is the program counter pc. That is, the next instruction address is added to the address field to produce the EA. typically, the address field is treated as a two's complement number this operation. Thus, the effective address is a displacement relative the address of the instruction. 3.Register addressing mode: Prod Rogier Addon] Registers Operand Figure: Reiser advesing modeRegister Addressing is similar to direct addressing. The only difference is that the address field refers to a register rather than a main memory address: EA=R 7. Discuss the characteristic of RISK and CISC processors. (2019) Ans Reduced Instruction Set Architecture (RISC) — The main idea behind this is to make hardware simpler by using an instruction set composed of a few basic steps for loading, evaluating, and storing operations just like a load command will load data, a store command will store the data. Complex Instruction Set Architecture (CISC) - The main idea is that a single instruction will do all loading, evaluating, and storing operations just like a multiplication command will do stuff like loading data, evaluating, and storing it, hence it’s complex. Characteristic of RISC — Simpler instruction, hence simple instruction decoding. Instruction comes undersize of one word. Instruction takes a single clock cycle to get executed. More general-purpose registers. Simple Addressing Modes. Fewer Data types. Apipeline can be achieved. NAWEYNE Characteristic of CISC - 1, Complex instruction, hence complex instruction decoding. Instructions are larger than one-word size. . Instruction may take more than a single clock cycle to get executed. . Less number of general-purpose registers as operations get performed in memory itself.5. Complex Addressing Modes. 6. More Data types. Example - Suppose we have to add two 8-bit numbers: CISC approach: There will be a single command or instruction for this like ADD which will perform the task. RISC approach: Here programmer will write the first load command to load data in registers then it will use a suitable operator and then it will store the result in the desired location. So, add operation is divided into parts i.e., load, operate, store due to which RISC programs are longer and require more memory to get stored but require fewer transistors due to less complex command. 8. What is interrupt? Describe about different types of interrupts. (2019) Ans: Interrupt: The interrupt is a signal emitted by hardware or software when a process or an event needs immediate attention. It alerts the processor to a high-priority process requiring interruption of the current working process. In I/O devices one of the bus control lines is dedicated for this purpose and is called the Interrupt Service Routine (ISR). Types of Interrupts: Generally, there are three types of Interrupts those are occurred for example 1. Internal Interrupt. 2. Software Interrupt. 3. External Interrupt.Internal Interrupts The Internal Interrupts are those which are occurred due to Some Problem in the Execution for Example When a user performing any Operation which contains any Error and which contains any type of Error. So that Internal Interrupts are those which are occurred by the Some Operations or by Some Instructions and the Operations those are not Possible but a user is trying for that Operation. Software Interrupts Software Interrupts are those which are made some call to the System for Example while we are Processing Some Instructions and when we want to Execute one more Application Programs. External Interrupt The External Interrupt occurs when any Input and Output Device request for any Operation and the CPU will Execute those instructions first For Example When a Program is executed and when we move the Mouse on the Screen then the CPU will handle this External interrupt first and after that he will resume with his operation. 9. What is instruction? How many instructions are there? Discuss briefly. (2019.2020) Ans: Instruction: The instruction set, also called ISA (instruction set architecture), is part of a computer that pertains to programming, which is more or less machine language. The instruction set provides commands to the processor, to tell it what it needs to do. The instruction set consists of addressing modes, instructions, native data types, registers, memory architecture, interrupt, and exception handling, and external I/O. The instruction can be classified as three, two, and one address instruction or zero address instruction, depending on the number of address fields.Three Address Instructions A three-address instruction has the following general format: source 1 operation, source 2 operation, source 3 operation, destination ADD X, Y,Z Here, X, Y, and Z seem to be the three variables that are each assigned to a distinct memory location. The operation implemented on operands is ‘ADD.’ The source operands are ‘x’ and ‘Y,’ while the destination operand is ‘Z’ In order to determine the three operands, bits are required. To determine one operand, n bits are required (one memory address). In the same way, 3n bits are required to define three operands (or three memory addresses). To identify the ADD operation, bits are also required. Two Address Instructions A two-address instruction has the following general format: source and destination of the operation ADDX,Y Here X and Y are the two variables that have been assigned to a specific memory address. The operation performed on the operands is ‘ADD.’ This command combines the contents of variables X and Y and stores the result in variable Y. The source operand is ‘A,’ while ‘B’ is used as both a source and a destination operand. The two operands must be determined using bits. To define one operand, n bits are required (one memory address). To determine two operands, 2n bits are required (two memory addresses). The ADD operation also necessitates the use of bits. One Address Instructions One address instruction has the following general format: operation source INCLUDE XHere X refers to the variable that has access to a specific memory region. The operation performed on operand A is ‘ADD.’ This instruction adds the value of variable A to the accumulator and then saves the result inside the accumulator by restoring the accumulator’s contents. Zero Address Instructions In zero address instructions, the positions of the operands are implicitly represented. These instructions use a structure called a pushdown stack to hold operands. 10. What is instruction cycle? Discuss the instruction cycle state diagram. (2019,2020) Ans: Instruction cycle: An instruction cycle is the basic operation of a computer. Each instruction cycle contains of two sub-cycles. During the fetch cycle the op-code of the next instruction is loaded into the IR and the address portion is loaded into the MAR. m ‘Operand fetch eas Instruction complete Jeloh next insrvcion | [x ees Retr fr sing or vecior data Fig: Instruction Cycle state diagram© Instruction address calculation: Determine the address of the next instruction to be executed usually this involves adding a fixed number to the address of the previous instruction. * Instruction fetch: Read instruction from its memory location in to the processor. © Instruction operation decode: Analyze instruction to determine type of operation to be performed and operands(s) to be used. © Operand address calculation: It the operations involves reference to an operand in memory or a viable via I/O. © Operand fetch: Fetch the operand form memory or read from 1/0. © Data operation: Perform the operation indicated in the instruction. © Operand store: Write the result into memory or out to 1/0. 11. Diagrammatically show the instruction cycle with interrupt. (2018) Ans: Instruction cycle with interrupt: Figure: Instruction cycle state diagram with interrupsSet-2 1. What is computer bus? Discuss in briefly the elements to design of computer bus. (2019) Ans: Computer bus A computer bus is a communication path way that connecting two or more device. In Computer architecture, a bus is a communication system that transfer data between components inside a computer, or between computers. Elements of bus design: Type: 1. Dedicated 2. Multiplexed Method of arbitration: 1. Centralized 2. Distributed Timing: 1. Synchronous 2. Asynchronous Bus width: 1. Address 2. Data Data transfer type: Read Write Read-modify-write Read-after-write BYwNE5. Block 2. With diagram describe different types of bus architecture and mention their advantages and disadvantages. (2018) Ans: There are 2 types of bus architecture: 1. Traditional 2. High speed Traditional bus architecture: Maden C=] Advantage of Traditional Bus Architecture: A separate cache structure insulates the processor from the requirement to access the main memory frequently. This arrangement allows the system to support a wide variety of I/O devices and, at the same time, insulate memory to processor traffic from I/O traffic. Disadvantages of Traditional Bus Architecture: The traditional bus architecture is reasonably efficient but begins to break down as higher, and higher performance is seen in the I/O devices.High speed bus architecture: = ee Advantage of High-speed bus architecture: The advantage of this arrangement is that the high-speed bus brings high-demand devices into closer integration with the processor and, at the same time, is independent of the processor. So changes in processor architecture also do not affect the high-speed bus Disadvantage of High-speed bus architecture: A large amount of energy is required to transmit data over a wide bus, exacerbating ground bounce and noise problems. Path length and impedance are difficult to control, and a large amount of circuit board real estate is required to situate wide parallel buses. 4. What is system bus? Describe with configuration the high-performance bus system. (2020) Ans: System bus: Asystem bus is a single computer bus that connects the major components of a computer system, combining the functions of a data bus to carry information, anaddress bus to determine where it should be sent, and a control bus to determine its operation. High-performance bus system: =] Pe]| Ge] Ge] Ge ieee This bus supports connections to high-speed LANs, such as fast ethernet at 100 Mbps, video and graphics workstation controllers, as well as interface controllers to local peripheral buses, including SCSI and FireWire. The latter is high-speed bus arrangement specifically designed to support high- capacity I/O devices. Lower-speed devices are still supported off an expansion bus, with an interface buffering traffic between the expansion bus and high-speed bus.