Digital Electronics.

CHAPTER TWENTY FOUR

CMOS Combinational Logic Circuits

1
 Introduction
© Dr. Anas

This chapter presents the structure of multi-input CMOS gates

Ch. 24 such as NANDs, NORs, AND-OR-Inverts (AOIs)

2
 CMOS Inverter
© Dr. Anas

 
D, S D, S
VIN VDS VIN N-MOS with body
VDS implied at ground
Ch. 24
S, D 
S, D 

 
D, S D, S
VDS VIN P-MOS with body
VIN VDS implied at VDD
VDD
S, D 
S, D 

3
 CMOS Inverter
© Dr. Anas

VDD

When VIN is low, i.e. VIN=VGS<VTN: Source at higher voltage

S
Ch. 24  N is “off”, P is active “on”
P Drain at lower voltage

VIN D VOUT
G
Drain at higher voltage
D
When VIN is high, i.e. VIN=VDD-VSG>VTP:
N
 P is “off”, N is active “on” Source at lower voltage
S

Thus, for input high and low states, both

devices never conduct simultaneously

4
 CMOS NAND Gate
© Dr. Anas

VDD
VA VB NA NB PA PB VOUT S
S
low low off off on on high
low high off on on off high PA PB
high low on off off on high
Ch. 24
high high on on off off low D D V
OUT

VB D
VB NB
VOUT
NAND VA S
D
VA
NA
S

5
 CMOS NOR Gate
© Dr. Anas

VDD
VA VB NA NB PA PB VOUT S
low low off off on on high
low high off on on off low PA
high low on off off on low
Ch. 24 high high on on off off low D
VB S
PB
D VOUT
VB VOUT D D
NOR VA VA
NA NB
S
S

6
 CMOS AND Gate
© Dr. Anas

VDD VDD
S S
S
PA PB
P
Ch. 24
D D
D VOUT
VB D
NB D
S
D N
VA
NA
S
S

VB VOUT
AND VA
7
 CMOS OR Gate
© Dr. Anas

VDD
S
VDD
PA
S
Ch. 24
D S
VB P
PB
D D VOUT
D D
VA
NA NB D
S
S N

VB S
VOUT
OR VA

8
 CMOS AND-OR-Inverter Gate
© Dr. Anas

A
Ch. 24
B
F  A B  C  D
C
D

9
 CMOS XOR Gate
© Dr. Anas

Ch. 24
A F  A B
B
 
F  A  B  A  B  A  B   A  B

F  A A  A B  B  A  B  B  A B  B  A

10
© Dr. Anas

 HW #13:Solve Problems: 24.1-6, 24.25

Ch. 24

11