Muhammad Usman CA Lab 12-ENC-17

Lab Assignment 09
ALU
module usman(S, A, M, N, U);

input [3:0] M, N; input U;

output [3:0] S; output A; wire [3:1] Wire;

full_adder FA1 (S[0], Wire[1], N[0], I[0], U); full_adder FA2 (S[1], Wire[2], M[1], N[1], Wire[1]);

full_adder FA3 (S[2], Wire[3], M[2], R[2], Wire[2]); full_adder FA4 (S[3], A, M[3], I[3], Wire[3]);

endmodule

module half_adder (Sum, Carry, input1, input2);

input Input1, input2;

output Sum, Carry;

xor (Sum, input1, input2); and (Carry, input1, input2);

endmodule

module full_adder (sum, carry_out, in1, in2, carry_in);

input in1, in2, carry_in; output sum, carry_out; wire wire1, wire2, wire3;

half_adder HA1 (wire1, wire2, in1, in2); half_adder HA2 (sum, wire3, wire1, carry_in);

or (carry_out, wire2, wire3);

endmodule

module ALU(sel, x, y, G, CO);

input [2:0]sel; input [3:0] x, y;

output CO; output [3:0] G; wire [3:0] w;

wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16;

not (w1, y[0]); not (w2, y[1]);

not (w3, y[2]); not (w4, y[3]);

and (w5, y[3], sel[1]); and (w6, w4, sel[2]);

and (w7, y[2], sel[1]); and (w8, w3, sel[2]);

and (w9, y[1], sel[1]); and (w10, w2, sel[2]);

and (w11, y[0], sel[1]); and (w12, w1, sel[2]);

or (w[3], w5, w6); or (w[2], w7, w8);

or (w[1], w9, w10); or (w[0], w11, w12);

MUHAMMAD_USMAN tewq(G[3:0], CO,w[3:0] ,x[3:0], sel[0]);

Muhammad Usman CA Lab 12-ENC-17

endmodule

module test_ALU;

reg [2:0]sel; reg [3:0] x, y;

wire CO; wire [3:0] G;

ALU ARR1(sel, x, y, G, CO);

Initial

begin

x=4'b0011 ; y=4'b1101;

sel=3'b000;

#10 sel=3'b001;

#10 sel=3'b010;

#10 sel=3'b011;

#10 sel=3'b100;

#10 sel=3'b101;

#10 sel=3'b110;

#10 sel=3'b111;

end

endmodule Wave Form