Muhamamd Usman CA-lab 12-ENC-17

Universal Shift Register

module usman_usr (q,d,s,lsi,rsi,clk);

input [3:0]d; input clk,lsi,rsi; input [1:0]s;

output [3:0]q; reg [3:0]q;

always @(posedge clk)

begin

case(s)

2'b00:q <= 4'b1010;

2'b01:q <= {lsi,q[3:1]};

2'b10:q <= {q[2:0],rsi};

2'b11:q <= d;

endcase

end

endmodule

module usman_usr_test;

reg [3:0]d; reg clk,lsi,rsi; reg [1:0]s; wire [3:0]q;

anees_usr USR1(q,d,s,lsi,rsi,clk);

always #5 clk=~clk;

initial

begin

clk=1;

d=4'b1100; lsi=1; rsi=1;

s= 2'b00;

#10 s=2'b01;

#10 s=2'b10;

#10 s=2'b11;

end

endmodule
Muhamamd Usman CA-lab 12-ENC-17

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