Muhammad Usman CA Lab 12-ENC-17

8-Bit Ring Counter

module ring_count (Resetn, Clock, Q);

parameter n = 8; input Resetn, Clock;

output [n-1:0] Q; reg [n-1:0] Q;

always @(posedge Clock)

if (!Resetn)

begin

Q[7:1] <= 0; Q[0] <= 1; end

else

Q <= {{Q[6:0]}, {Q[7]}};

endmodule

module test_ring_counter; reg Resetn, Clock; wire [7:0] Q; ring_count asdxxc(Resetn, Clock, Q);

always #2 Clock=~Clock;

initial

begin

Resetn=0; Clock=1;

#10 Resetn=1;

end

endmodule

module Test; reg Resetn, Clock; wire [n-1:0] Q;

ring_count mateb(Resetn, Clock, Q);

always #5 Clock=~Clock;

initial begin

Clock=1;Resetn=1;

#10 Resetn=0;

end

endmodule Wave Diagram