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CS 223 - SystemVerilog Codes -

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a) Multiplexer 2-1

module multiplexer(
input x[0:1],
input s,
output y
);

assign y = (x[0] & ~s) | (x[1] & s);

endmodule

b) Multiplexer 4-1

module multiplexer4_1(
input x[0:3],
input s[0:1],
output y
);

logic carry[0:1];

multiplexer m1(x[0:1], s[0], carry[0]);

multiplexer m2(x[2:3], s[0], carry[1]);
multiplexer m3(carry[0:1], s[1], y);

endmodule

c) Multiplexer 8-1

module multiplexer8_1(
input x[0:7],
input s[0:2],
output y
);

logic carry[0:3];
logic nots2;

multiplexer4_1 m1(x[0:3],s[0:1],carry[0]);
multiplexer4_1 m2(x[4:7],s[0:1],carry[1]);

and a1(carry[3], carry[1], s[2]);

not n1(nots2,s[2]);
and a2(carry[2], carry[0], nots2);

or o1(y, carry[2], carry[3]);

endmodule

d) Equalizer
 module equalizer(
input a,
output b
);

assign b = a;
endmodule

e) Main Function (Function F)

module mainFunc(
input a,
input b,
input c,
input d,
output y
);

logic notC, in[0:7], s[0:2];

not n1(notC, c);

equalizer e1(c,in[0]);
equalizer e2(c,in[1]);
equalizer e3(c,in[2]);
equalizer e4(c,in[3]);

equalizer e5(notC,in[4]);
equalizer e6(notC,in[5]);
equalizer e7(notC,in[6]);
equalizer e8(notC,in[7]);

equalizer e9(d,s[0]);
equalizer e10(b,s[1]);
equalizer e11(a,s[2]);

multiplexer8_1 mux1(in[0:7] , s[0:2] , y);

endmodule

f) Decoder 1-2

module decoder(
input x,
input en,
output y[0:1]
);

assign y[0] = x & en;

assign y[1] = ~x & en;

endmodule

g) Decoder 2-4

module decoder2_4(
 input x[0:1],
input en,
output y[3:0]
);

logic carry[0:1];

decoder d1(x[1],en,carry[0:1]);
decoder d2(x[0], carry[0], y[3:2]);
decoder d3(x[0], carry[1], y[1:0]);

endmodule

h) All Testbenches

module testbench_MUX8_1();

logic x[0:7], s[0:2];

logic y;

multiplexer8_1 mux(x[0:7], s[0:2], y);

initial begin
for (int i = 0; i<2048; i++)
begin
{x[0],x[1],x[2],x[3],x[4],x[5],x[6],x[7],s[0],s[1],s[2]} = i;
#5;
end
end
endmodule

module testbench_decoder1_2();

logic x, en;
logic y[0:1];

decoder func(x, en, y[0:1]);

initial begin
x=0; en=0; #10;
x=1; #10;
x=0; en=1; #10;
x=1;
end

endmodule

module testbench_decoder2_4();

logic x[0:1], en;

logic y[3:0];

decoder2_4 func(x[0:1], en, y[3:0]);

initial begin
en=0; x[0]=0; x[1]=0; #10;
x[0]=1; #10;
x[0]=0; x[1]=1; #10;
 x[0]=1; #10;
en=1; x[0]=0; x[1]=0; #10;
x[0]=1; #10;
x[0]=0; x[1]=1; #10;
x[0]=1; #10;
end
endmodule

module testbench_multiplexer2_1();

logic x[0:1], s;
logic y;

multiplexer func(x[0:1], s, y);

initial begin
s=0; x[0]=0; x[1]=0; #10;
x[0]=1; #10;
x[0]=0; x[1]=1; #10;
x[0]=1; #10;
s=1; x[0]=0; x[1]=0; #10;
x[0]=1; #10;
x[0]=0; x[1]=1; #10;
x[0]=1; #10;
end
endmodule

module testbench_multiplexer4_2();

logic x[0:3], s[0:1];

logic y;

multiplexer4_1 func(x[0:3], s[0:1], y);

initial begin
s[1]=0; s[0]=0; x[3]=0; x[2]=0; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
x[2]=1; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
x[3]=1; x[2]=0; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
x[2]=1; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
s[0]=1; x[3]=0; x[2]=0; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
x[2]=1; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
 x[3]=1; x[2]=0; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
x[2]=1; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
s[1]=1; s[0]=0; x[3]=0; x[2]=0; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
x[2]=1; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
x[3]=1; x[2]=0; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
x[2]=1; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
s[0]=1; x[3]=0; x[2]=0; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
x[2]=1; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
x[3]=1; x[2]=0; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
x[2]=1; x[1]=0; x[0]=0; #10;
x[0]=1; #10;
x[1]=1; x[0]=0; #10;
x[0]=1; #10;
end

endmodule