Introduction to FPGA programming

Using Xilinx® Vivado® and VHDL

Dott. Luca Pacher

luca.pacher@cern.ch

University of Torino
Ph.D. in Physics
Fall 2020
Introduction to FPGAs
and Xilinx devices
 From CPLDs to FPGAs

”Programmable” logic devices (PLDs):

one-time programmable (OTP) :
− Fuses (destroy internal links with current)
− Anti-fuses (grow internal links)
− PROM
reprogrammable :
− EPROM
− EEPROM
− Flash
− RAM (volatile)
 CPLDs

CPLD = Complex Programmable Logic Device

a combination of a fully programmable AND/OR array and a bank of
macrocells
the AND/OR array is reprogrammable and can perform a multitude of logic
functions
macrocells are functional blocks that perform combinatorial or sequential
logic, along with varied feedback paths
 FPGA devices

FPGA = Field Programmable Gate Array

− gate array : array of ”logic cells” (more later) that can be programmed
to implement any desired logic functionality
− field programmable : device not committed to do something until
effectively programmed according to the field of application

born in 80s as evolution of CPLD

conceptually same as Programmable Logic Devices (PLDs)

in practice, vastly more complex functions can be implemented

due to size and extra features

in principle, reprogrammable infinite times with no limitations

 Advantages of FPGAs

flexible
− you can implement any digital function !
− reprogrammable
fast CAD-to-silicon prototyping cycle
− no need for mask-based production
− that is... no need to wait for years before looking at some nice waveforms
at the oscilloscope and making measurements in the lab !
de facto cheaper, safer and more relaxed business than making ASICs
− affordable per-unit costs (from ≈ 100 e for an ”entry level” evaluation
board to ≈ 1,500 e for a ”professional” evaluation board)
− cheaper (with free versions) and much simpler EDA softwares !
− no neurotic and mental exhaustion ”GDS submissions” to foundries
fast Engineering Change Orders (ECOs) if required
− ”respin” of a mapped RTL project in a few hours
 Disadvantages of FPGAs

slower than equivalent ASICs

− you can map a whole CPU into your FPGA but...
− ... it will never perform as a 2.5 GHz Intel Core i7 (not the best one!)

higher power consumption compared to ASICs

high costs to instrument large experimental equipments
(e.g. LHC counting rooms) compared to ASICs
not as simple to use as a microcontroller (e.g. Arduino) or a CPUs
− FPGA design is NOT software programming !
− in depth knowledge of modern digital design techniques, Verilog or VHDL
and modern electronics engineering mandatory

configurability requires more infrastructure

radiation tolerance can be an issue

Application-Specific Integrated
Circuits (ASICs) :
− full-custom
− high performance
− low-power consumption
− expensive development tools
− long and time-consuming
CAD-to-silicon prototyping
cycle
− high development cost, but
cheaper on high volume
production
− highly bugs-prone (outside
industry)
− highest performance !
Recap: ASICs vs. FPGAs
Field Programmable Gate Arrays
(FPGAs) :
− reconfigurable
− ”out of the box” solution
(no layout, masks or other
manufacturing steps needed)
− slow compared to ASICs
− power hungry
− fast CAD-to-silicon prototyping
and quick time-to-market
− small development overhead,
low-cost development tools
− per-unit cost low compared to
ASICs, expensive on large-scales
− no minimum quantity order
 FPGA vendors

”Big” FPGA manufactures :

− Xilinx (acquired by AMD in 2020)
− Altera (acquired by Intel in 2019)

Other vendors :
− Actel (acquired by Microsemi Corporation in 2010)
− Lattice Semiconductor
− less known: QuickLogic, Achronix
 Xilinx vs. (Intel) Altera
Xilinx and Intel Altera are de facto the two biggest FPGA manufacturers and vendors
available on the market :
− each vendor provides both ”the silicon” and ”the software” to program it
− once you choose a vendor you are tied up to use its own software†
(at least for the actual physical implementation)
− Xilinx software: Vivado (legacy ISE)
− Altera software: Quartus
− Quartus is much simpler and easier to use compared to Vivado
− when you move to High-Level Synthesis (HLS), Altera is far away with respect to Xilinx
− both companies offer free software versions including free IP cores for most of their devices
− OPEN DOCUMENTATION !
− both widely used in the Nuclear and High-Energy Physics (HEP) research communities
− the actual choice mainly due to each project history
− example: Xilinx extensively used in Torino INFN labs, while Altera in Pisa INFN labs
From now on we will focus only to Xilinx FPGA devices.
† HDL simulations can be performed with any digital simulator, including gate-level simulations with SDF.
In principle also synthesis can be performed using third-party tools, but place-and-route necessarily requires
to use the vendor software.
 The (modern) Xilinx ”zoo”

7-series family
− 28 nm high-K metal gate CMOS technology
− Spartan-7 ⇒ Artix-7 ⇒ Kintex-7 ⇒ Virtex-7
− devices containing ”only” programmable logic

System on Chip (SoC) devices

− 28 nm high-K metal gate CMOS technology
− Zynq-7000 / Zynq UltraScale+
− FPGA (aka ”programmable logic, PL”) + single/dual core ARM CPU
(aka ”processor, PS”) embedded on the same silicon die
− PL programmed in HDL/HLS, PS running C/C++ programs ... wonderful !

Virtex/Kintex UltraScale and Virtex/Kintex UltraScale+

− 20 nm and 16 nm FinFET technologies
− highest performance and integration densities
− hic sunt leones ...
 Xilinx 7-series family comparison

Different size, number of programmable logic cells, I/O capabilities, performance and cost
depending on the chosen device family :

− Spartan 7 : lowest-cost, lowest-power, good I/O performance, lowest number of resources

− Artix 7 : low-power, medium number of resources and I/O, good choice for DSP
− Kintex 7 : best compromise between number of resources, I/O, speed, power and cost
− Virtex 7 : highest system performance (resources, speed, I/O) but also largest power
consumption and highest cost
Reference documentation :
− Xilinx 7 Series FPGAs Data Sheet: Overview (DS180)
− Xilinx 7 Series Product Selection Guide
 Example: Xilinx Kintex-7 KC705 evaluation board

A very popular choice for many ongoing projects here in Torino !

(price: approx. 1,700 USD)

https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html
 Example: Digilent Arty-A7 evaluation board

Device: Xilinx Artix-7

https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists
 Example: Digilent Zybo-Z7 evaluation board

Device: Xilinx Zynq-7000 ARM/FPGA SoC

https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board
Xilinx FPGAs architecture overview

Reference documentation :

− Xilinx 7 Series FPGAs Data Sheet: Overview (DS180)

− 7 Series FPGAs Configurable Logic Block User Guide (UG474)
 Fundamental FPGA components

Programmable Switch Matrix (PSM) I/O Block (IOB)

Configurable Logic Block (CLB)

 Programmable interconnections /1

A
0 1 2 3 4 5

D B D B

C C
Programmable interconnections /2
 Look-up tables (LUT) /1

How to implement a 2-bit truth table (boolean logic) ?

x1 x2 F
x1
0 0 1
F (x1, x2)
0 1 0
x2
1 0 0
1 1 1
 Look-up tables (LUT) /2

FPGA solution: write the truth table into a RAM !

x1

0/1
0

1
0/1 0
F (x1, x2)
1
0/1
0

1
0/1

x2
 Look-up tables (LUT) /3

x1

1
0

1
0
0
F (x1, x2)
1
0
0

1
1
x1 x2 F

x2 0 0 1

0 1 0

1 0 0

1 1 1
 Logic Cell (LC)

Xilinx terminology :
− Logic Cell (LC) = 1x LUT + 1 register (FF) + programmable MUX
− LUT implemented as 6-inputs, 64-bit RAM
− slice = 4x LUTs + 8 registers (FFs) + MUXs + fast-carry chain (CLA)
− Configurable Logic Block (CLB) = 2x slices
− Basic Element (BEL) = any device primitive
 Programmable I/O pads

I/O BLOCK

programmable pad
 Design flow

Design Verification

Behavioral
Design entry (HDL)
Simulation

Synthesis

Gate-level
Implementation Simulation
(place-and-route)

Timing Analysis

Device programming
 Gate-level (GL) simulations

In order to simulate FPGA primitives in VHDL :

library UNISIM ;
use UNISIM . VComponents . all ;