a Precision, Low Cost,

High Speed, BiFET Op Amp

AD711
FEATURES CONNECTION DIAGRAMS
Enhanced Replacements for LF411 and TL081
AC PERFORMANCE TO-99 Plastic Mini-DIP (N) Package
Settles to 60.01% in 1.0 ms (H) Package Plastic Small Outline (R)
16 V/ms min Slew Rate (AD711J) and
3 MHz min Unity Gain Bandwidth (AD711J) Cerdip (Q) Package

DC PERFORMANCE
0.25 mV max Offset Voltage: (AD711C)
3 mV/8C max Drift: (AD711C)
200 V/mV min Open-Loop Gain (AD711K)
4 mV p-p max Noise, 0.1 Hz to 10 Hz (AD711C)
Available in Plastic Mini-DIP, Plastic SO, Hermetic
Cerdip, and Hermetic Metal Can Packages
MIL-STD-883B Parts Available
Available in Tape and Reel in Accordance with
EIA-481A Standard
Surface Mount (SOIC)
Dual Version: AD712
Extended reliability PLUS screening is available, specified over
Quad Version: AD713
the commercial and industrial temperature ranges. PLUS
screening includes 168-hour burn-in, as well as other environ-
PRODUCT DESCRIPTION
mental and physical tests.
The AD711 is a high speed, precision monolithic operational
amplifier offering high performance at very modest prices. Its The AD711 is available in an 8-pin plastic mini-DIP, small out-
very low offset voltage and offset voltage drift are the results of line, cerdip, TO-99 metal can, or in chip form.
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that use PRODUCT HIGHLIGHTS
older precision BiFETs and, in many cases, bipolar op amps. 1. The AD711 offers excellent overall performance at very
competitive prices.
The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16 V/µs 2. Analog Devices’ advanced processing technology and with
and a settling time of 1 µs to ± 0.01%, the AD711 is ideal as a 100% testing guarantees a low input offset voltage (0.25 mV
buffer for 12-bit D/A and A/D Converters and as a high-speed max, C grade, 2 mV max, J grade). Input offset voltage is
integrator. The settling time is unmatched by any similar IC specified in the warmed-up condition. Analog Devices’ laser
amplifier. wafer drift trimming process reduces input offset voltage
drifts to 3 µV/°C max on the AD711C.
The combination of excellent noise performance and low input
current also make the AD711 useful for photo diode preamps. 3. Along with precision dc performance, the AD711 offers
Common-mode rejection of 88 dB and open loop gain of excellent dynamic response. It settles to ± 0.01% in 1 µs and
400 V/mV ensure 12-bit performance even in high-speed unity has a 100% tested minimum slew rate of 16 V/µs. Thus this
gain buffer circuits. device is ideal for applications such as DAC and ADC
buffers which require a combination of superior ac and dc
The AD711 is pinned out in a standard op amp configuration
performance.
and is available in seven performance grades. The AD711J and
AD711K are rated over the commercial temperature range of 4. The AD711 has a guaranteed and tested maximum voltage
0°C to +70°C. The AD711A, AD711B and AD711C are rated noise of 4 µV p-p, 0.1 to 10 Hz (AD711C).
over the industrial temperature range of –40°C to +85°C. The 5. Analog Devices’ well-matched, ion-implanted JFETs ensure
AD711S and AD711T are rated over the military temperature a guaranteed input bias current (at either input) of 25 pA
range of –40°C to +125°C and are available processed to MIL- max (AD711C) and an input offset current of 10 pA max
STD-883B, Rev. C. (AD711C). Both input bias current and input offset current
are guaranteed in the warmed-up condition.

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
AD711–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V = 615 V @ T = +258C unless otherwise noted)
S A

J/A/S K/B/T C
Parameter Min Typ Max Min Typ Max Min Typ Max Units
INPUT OFFSET VOLTAGE1
Initial Offset 0.3 2/1/1 0.2 0.5 0.10 0.25 mV
TMIN to TMAX 3/2/2 1.0 0.45 mV
vs. Temp 7 20/20/20 5 10 2 5 µV/°C
vs. Supply 76 95 80 100 86 110 dB
TMIN to TMAX 76/76/76 80 86 dB
Long-Term Stability 15 15 15 µV/Month
INPUT BIAS CURRENT2
VCM = 0 V 15 50 15 50 15 25 pA
VCM = 0 V @ TMAX 1.1/3.2/51 1.1/3.2/51 1.6 nA
VCM = ± 10 V 20 100 20 100 20 50 pA
INPUT OFFSET CURRENT
VCM = 0 V 10 25 5 25 5 10 pA
VCM = 0 V @ TMAX 0.6/1.6/26 0.6/1.6/26 0.65 nA
FREQUENCY RESPONSE
Small Signal Bandwidth 3.0 4.0 3.4 4.0 3.4 4.0 MHz
Full Power Response 200 200 200 kHz
Slew Rate 16 20 18 20 18 20 V/µs
Settling Time to 0.01% 1.0 1.2 1.0 1.2 1.0 1.2 µs
Total Harmonic Distortion 0.0003 0.0003 0.0003 %
INPUT IMPEDANCE
Differential 3 × 1012i5.5 3 × 1012i5.5 3 × 1012i5.5 ΩipF
Common Mode 3 × 1012i5.5 3 × 1012i5.5 3 × 1012i5.5 ΩipF
INPUT VOLTAGE RANGE
Differential3 ± 20 ± 20 ± 20 V
Common-Mode Voltage4 +14.5, –11.5 +14.5, –11.5 +14.5, –11.5
TMIN to TMAX –VS + 4 +VS – 2 –VS + 4 +VS – 2 –VS + 4 +VS – 2 V
Common-Mode
Rejection Ratio
VCM = ± 10 V 76 88 80 88 86 94 dB
TMIN to TMAX 76/76/76 84 80 84 86 90 dB
VCM = ± 11 V 70 84 76 84 76 90 dB
TMIN to TMAX 70/70/70 80 74 80 74 84 dB
INPUT VOLTAGE NOISE 2 2 2 4 µV p-p
45 45 45 nV/√Hz
22 22 22 nV/√Hz
18 18 18 nV/√Hz
16 16 16 nV/√Hz
INPUT CURRENT NOISE 0.01 0.01 0.01 pA/√Hz
OPEN-LOOP GAIN 150 400 200 400 200 400 V/mV
100/100/100 100 100 V/mV
OUTPUT CHARACTERISTICS
Voltage +13, –12.5 +13.9, –13.3 +13, –12.5 +13.9, –13.3 +13, –12.5 +13.9, –13.3 V
± 12/± 12/612 +13.8, –13.1 612 +13.8, –13.1 612 +13.8, –13.1 V
Current 25 25 25 mA
POWER SUPPLY
Rated Performance ± 15 ± 15 ± 15 V
Operating Range 64.5 618 64.5 618 64.5 618 V
Quiescent Current 2.5 3.4 2.5 3.0 2.5 2.8 mA
NOTES
1
Input Offset Voltage specifications are guaranteed after 5 minutes of operation at T A = +25°C.
2
Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25°C. For higher temperatures, the current doubles every 10°C.
3
Defined as voltage between inputs, such that neither exceeds ± 10 V from ground.
4
Typically exceeding –14.1 V negative common-mode voltage on either input results in an output phase reversal.
Specifications subject to change without notice.

–2– REV. A
 AD711
ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . 500 mW Temperature Package Package
Model Range Description Option*
Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite AD711AH –40°C to +85°C 8-Pin Metal Can H-08A
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS AD711AQ –40°C to +85°C 8-Pin Ceramic DIP Q-8
AD711BH –40°C to +85°C 8-Pin Metal Can H-08A
Storage Temperature Range (Q, H) . . . . . . . . –65°C to +150°C
AD711BQ –40°C to +85°C 8-Pin Ceramic DIP Q-8
Storage Temperature Range (N) . . . . . . . . . . –65°C to +125°C
AD711CH –40°C to +85°C 8-Pin Metal Can H-08A
Operating Temperature Range AD711CQ –40°C to +85°C 8-Pin Ceramic DIP Q-8
AD711J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C AD711JN 0°C to +70°C 8-Pin Plastic DIP N-8
AD711A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C AD711JR 0°C to +70°C 8-Pin Plastic SOIC R-8
AD711S/T . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C AD711JR-REEL 0°C to +70°C 8-Pin Plastic SOIC R-8
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C AD711JR-REEL7 0°C to +70°C 8-Pin Plastic SOIC R-8
NOTES AD711KN 0°C to +70°C 8-Pin Plastic DIP N-8
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
AD711KR 0°C to +70°C 8-Pin Plastic SOIC R-8
permanent damage to the device. This is a stress rating only and functional AD711KR-REEL 0°C to +70°C 8-Pin Plastic SOIC R-8
operation of the device at these or any other conditions above those indicated in the AD711KR-REEL7 0°C to +70°C 8-Pin Plastic SOIC R-8
operational section of this specification is not implied. Exposure to absolute AD711SCHIPS –55°C to +125°C Bare Die
maximum rating conditions for extended periods may affect device reliability. AD711SQ/883B –55°C to +125°C 8-Pin Ceramic DIP Q-8
2
Thermal Characteristics: AD711TQ/883B –55°C to +125°C 8-Pin Ceramic DIP Q-8
8-Pin Plastic Package: θJC = 33°C/Watt; θJA = 100°C/Watt
8-Pin Cerdip Package: θJC = 22°C/Watt; θJA = 110°C/Watt
8-Pin Metal Can Package: θJC = 65°C/Watt; θJA = 150°C/Watt
3
For supply voltages less than ± 18 V, the absolute maximum input voltage is equal
to the supply voltage.

METALLIZATION PHOTOGRAPH
Dimensions shown in inches and (mm)
Contact factory for latest dimensions.

REV. A –3–
AD711–Typical Characteristics

Figure 1. Input Voltage Swing vs. Figure 2. Output Voltage Swing vs. Figure 3. Output Voltage Swing
Supply Voltage Supply Voltage vs. Load Resistance

Figure 4. Quiescent Current vs. Figure 5. Input Bias Current vs. Figure 6. Output Impedance vs.
Supply Voltage Temperature Frequency

Figure 7. Input Bias Current vs. Figure 8. Short Circuit Current Figure 9. Unity Gain Bandwidth vs.
Common Mode Voltage Limit vs. Temperature Temperature

–4– REV. A
 AD711

Figure 10. Open-Loop Gain and Phase Figure 11. Open-Loop Gain vs. Figure 12. Power Supply Rejection
Margin vs. Frequency Supply Voltage vs. Frequency

Figure 13. Common Mode Rejection Figure 14. Large Signal Frequency Figure 15. Output Swing and Error
vs. Frequency Response vs. Settling Time

Figure 16. Total Harmonic Distortion Figure 17. Input Noise Voltage Figure 18. Slew Rate vs. Input
vs. Frequency Spectral Density Error Signal

REV. A –5–
AD711

Figure 20. T.H.D. Test Circuit

Figure 19. Slew Rate vs. Temperature

Figure 21. Offset Null Configurations

Figure 22a. Unity Gain Follower Figure 22b. Unity Gain Follower Figure 22c. Unity Gain Follower
Pulse Response (Large Signal) Pulse Response (Small Signal)

Figure 23a. Unity Gain Inverter Figure 23b. Unity Gain Inverter Figure 23c. Unity Gain Inverter
Pulse Response (Large Signal) Pulse Response (Small Signal)

–6– REV. A

OPTIMIZING SETTLING TIME
Most bipolar high-speed D/A converters have current outputs;
therefore, for most applications, an external op amp is required
for current-to-voltage conversion. The settling time of the con-
verter/op amp combination depends on the settling time of the
DAC and output amplifier. A good approximation is:
t S Total = (t S DAC )2 + (t S AMP )2
The settling time of an op amp DAC buffer will vary with the
noise gain of the circuit, the DAC output capacitance, and with
the amount of external compensation capacitance across the
DAC output scaling resistor.
Settling time for a bipolar DAC is typically 100 to 500 ns. Previ-
ously, conventional op amps have required much longer settling
times than have typical state-of-the-art DACs; therefore, the
amplifier settling time has been the major limitation to a
high-speed voltage-output D-to-A function. The introduction of
the AD711/712 family of op amps with their 1 µs (to ± 0.01% of
final value) settling time now permits the full high-speed capa-
bilities of most modern DACs to be realized.
Figure 24. ± 10 V Voltage Output Bipolar DAC
a. (Full-Scale Negative Transition)
Figure 25. Settling Characteristics for AD711 with AD565A
REV. A
AD711
In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD711 family assures 12-bit accuracy over the full
operating temperature range.
The excellent high-speed performance of the AD711 is shown in
the oscilloscope photos of Figure 25. Measurements were taken
using a low input capacitance amplifier connected directly to the
summing junction of the AD711 – both photos show the worst
case situation: a full-scale input transition. The DAC’s 4 kΩ
[10 kΩi8 kΩ = 4.4 kΩ] output impedance together with a 10 kΩ
feedback resistor produce an op amp noise gain of 3.25. The
current output from the DAC produces a 10 V step at the op
amp output (0 to –10 V Figure 25a, –10 V to 0 V Figure 25b.)
Therefore, with an ideal op amp, settling to ± 1/2 LSB (± 0.01%)
requires that 375 µV or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD711 summing junction) must be
less than 375 µV. As shown in Figure 25, the total settling time
for the AD711/AD565 combination is 1.2 microseconds.
b. (Full-Scale Positive Transition)
–7–
AD711
OP AMP SETTLING TIME— When RO and IO are replaced with their Thevenin VIN and RIN
A MATHEMATICAL MODEL equivalents, the general purpose inverting amplifier of Figure
The design of the AD711 gives careful attention to optimizing 26b is created. Note that when using this general model, capaci-
individual circuit components; in addition, a careful tradeoff was tance CX is EITHER the input capacitance of the op amp if a
made: the gain bandwidth product (4 MHz) and slew rate simple inverting op amp is being simulated OR it is the com-
(20 V/µs) were chosen to be high enough to provide very fast bined capacitance of the DAC output and the op amp input if
settling time but not too high to cause a significant reduction in the DAC buffer is being modeled.
phase margin (and therefore stability). Thus designed, the
AD711 settles to ± 0.01%, with a 10 V output step, in under
1 µs, while retaining the ability to drive a 100 pF load capaci-
tance when operating as a unity gain follower.
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency of ωο/2π, Equation 1 will accurately de-
scribe the small signal behavior of the circuit of Figure 26a, con-
sisting of an op amp connected as an I-to-V converter at the
output of a bipolar or CMOS DAC. This equation would com-
pletely describe the output of the system if not for the op amp’s
finite slew rate and other nonlinear effects.
Equation 1. Figure 26b. Simplified Model of the AD711
Used as an Inverter
VO –R
= In either case, the capacitance CX causes the system to go from
I IN R(C f = CX ) 2  GN 
s + + RC f  s + 1 a one-pole to a two-pole response; this additional pole increases
ωο  ωο  settling time by introducing peaking or ringing in the op amp
output. Since the value of CX can be estimated with reasonable
ωο accuracy, Equation 2 can be used to choose a small capacitor,
where 2 =op amp’s unity gain frequency
π CF, to cancel the input pole and optimize amplifier response.
 R 
Figure 27 is a graphical solution of Equation 2 for the AD711
GN = “noise” gain of circuit 1 + R  with R = 4 kΩ.
O

This equation may then be solved for Cf:

Equation 2.

2 − GN 2 RC X ω ο + (1 − GN )
Cf = +
Rω ο Rω ο

In these equations, capacitor CX is the total capacitor appearing

the inverting terminal of the op amp. When modeling a DAC
buffer application, the Norton equivalent circuit of Figure 26a
can be used directly; capacitance CX is the total capacitance of
the output of the DAC plus the input capacitance of the op amp
(since the two are in parallel).

Figure 27. Value of Capacitor CF vs. Value of CX

Figure 26a. Simplified Model of the AD711 Used as a
Current-Out DAC Buffer
The photos of Figures 28a and 28b show the dynamic response
of the AD711 in the settling test circuit of Figure 29.
The input of the settling time fixture is driven by a flat-top pulse
generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2 and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 10, amplifying the error
signal output of A1.

–8– REV. A

Figure 28a. Settling Characteristics 0 to +10 V Step
Upper Trace: Output of AD711 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
Figure 29. Settling Time Test Circuit
GUARDING
The low input bias current (15 pA) and low noise characteristics
of the AD711 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
current-to-voltage converters. The use of a guarding technique
such as that shown in Figure 30, in printed circuit board layout
and construction is critical to minimize leakage currents. The
guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should not
be extended for any unnecessary length on the printed circuit
board.
Figure 30. Board Layout for Guarding Inputs
REV. A
AD711
Figure 28b. Settling Characteristics 0 to –10 V Step
Upper Trace: Output of AD711 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
D/A CONVERTER APPLICATIONS
The AD711 is an excellent output amplifier for CMOS DACs.
It can be used to perform both 2 quadrant and 4 quadrant op-
eration. The output impedance of a DAC using an inverted
R-2R ladder approaches R for codes containing many 1s, 3R for
codes containing a single 1, and for codes containing all zero,
the output impedance is infinite.
For example, the output resistance of the AD7545 will modu-
late between 11 kΩ and 33 kΩ. Therefore, with the DAC’s in-
ternal feedback resistance of 11 kΩ, the noise gain will vary from
2 to 4/3. This changing noise gain modulates the effect of the
input offset voltage of the amplifier, resulting in nonlinear DAC
amplifier performance.
The AD711K with guaranteed 500 µV offset voltage minimizes
this effect to achieve 12-bit performance.
Figures 31 and 32 show the AD711 and AD7545 (12-bit
CMOS DAC) configured for unipolar binary (2-quadrant multi-
plication) or bipolar (4-quadrant multiplication) operation. Ca-
pacitor C1 provides phase compensation to reduce overshoot
and ringing.
–9–
AD711
NOISE CHARACTERISTICS
The random nature of noise, particularly in the 1/f region, makes
it difficult to specify in practical terms. At the same time, design-
ers of precision instrumentation require certain guaranteed maxi-
mum noise levels to realize the full accuracy of their equipment.
The AD711C grade is specified at a maximum level of 4.0 µV
p-p, in a 0.1 to 10 Hz bandwidth. Each AD711C receives a
100% noise test for two 10-second intervals; devices with any ex-
cursion in excess of 4.0 µV are rejected. The screened lot is then
submitted to Quality Control for verification on an AQL basis.
All other grades of the AD711 are sample-tested on an AQL
basis to a limit of 6 µV p-p, 0.1 to 10 Hz.

DRIVING THE ANALOG INPUT OF AN A/D CONVERTER

Figure 31. Unipolar Binary Operation
Figure 32. Bipolar Operation
An op amp driving the analog input of an A/D converter, such as
that shown in Figure 34, must be capable of maintaining a con-
stant output voltage under dynamically changing load condi-
tions. In successive-approximation converters, the input current
is compared to a series of switched trial currents. The compari-
son point is diode clamped but may deviate several hundred mil-
livolts resulting in high frequency modulation of A/D input
current. The output impedance of a feedback amplifier is made
artificially low by the loop gain. At high frequencies, where the
loop gain is low, the amplifier output impedance can approach
its open loop value. Most IC amplifiers exhibit a minimum open
loop output impedance of 25 Ω due to current limiting resistors.
A few hundred microamps reflected from the change in converter

R1 and R2 calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are shown below.

Table I. Recommended Trim Resistor Values vs. Grades

of the AD7545 for VDD = +5 V

TRIM
RESISTOR JN/AQ/SD KN/BQ/TD LN/CQ/UD GLN/GCQ/GUD

R1 500 Ω 200 Ω 100 Ω 20 Ω

R2 150 Ω 68 Ω 33 Ω 6.8 Ω

Figures 33a and 33b show the settling time characteristics of the
Figure 34. AD711 as ADC Unity Gain Buffer
AD711 when used as a DAC output buffer for the AD7545.

a. Full-Scale Positive b. Full-Scale Negative

Transition Transition
a. Full-Scale Positive b. Full-Scale Negative a. Source Current = 2 mA b. Sink Current = 1 mA
Transition Transition
Figure 35. ADC Input Unity Gain Buffer Recovery Times
Figure 33. Settling Characteristics for AD711 with AD7545

–10– REV. A

loading can introduce errors in instantaneous input voltage. If
the A/D conversion speed is not excessive and the bandwidth of
the amplifier is sufficient, the amplifier’s output will return to
the nominal value before the converter makes its comparison.
However, many amplifiers have relatively narrow bandwidth
yielding slow recovery from output transients. The AD711 is
ideally suited to drive high speed A/D converters since it offers
both wide bandwidth and high open-loop gain.
DRIVING A LARGE CAPACITIVE LOAD
The circuit in Figure 36 employs a 100 Ω isolation resistor
which enables the amplifier to drive capacitive loads exceeding
1500 pF; the resistor effectively isolates the high frequency feed-
back from the load and stabilizes the circuit. Low frequency
feedback is returned to the amplifier summing junction via the
low pass filter formed by the 100 Ω series resistor and the load
capacitance, CL. Figure 37 shows a typical transient response
for this connection.
Figure 36. Circuit for Driving a Large Capacitive Load
Figure 37. Transient Response RL = 2 kΩ, CL = 500 pF
ACTIVE FILTER APPLICATIONS
In active filter applications using op amps, the dc accuracy of
the amplifier is critical to optimal filter performance. The
amplifier’s offset voltage and bias current contribute to output
error. Offset voltage will be passed by the filter and may be am-
plified to produce excessive output offset. For low frequency
applications requiring large value input resistors, bias currents
flowing through these resistors will also generate an offset
voltage.
In addition, at higher frequencies, an op amp’s dynamics must
be carefully considered. Here, slew rate, bandwidth, and
open-loop gain play a major role in op amp selection. The slew
rate must be fast as well as symmetrical to minimize distortion.
The amplifier’s bandwidth in conjunction with the filter’s gain
will dictate the frequency response of the filter.
The use of a high performance amplifier such as the AD711 will
minimize both dc and ac errors in all active filter applications.
REV. A
AD711
SECOND ORDER LOW PASS FILTER
Figure 38 depicts the AD711 configured as a second order
Butterworth low pass filter. With the values as shown, the cor-
ner frequency will be 20 kHz; however, the wide bandwidth of
the AD711 permits a corner frequency as high as several hun-
dred kilohertz. Equations for component selection are shown
below.
R1 = R2 = user selected (typical values: 10 kΩ – 100 kΩ)
1.414 0.707
C1= , C2 =
(2 π)( f cutoff )(R1) (2 π)( f cutoff )(R1)
Where C1 and C2 are in farads.
Figure 38. Second Order Low Pass Filter
An important property of filters is their out-of-band rejection.
The simple 20 kHz low pass filter shown in Figure 38, might be
used to condition a signal contaminated with clock pulses or
sampling glitches which have considerable energy content at
high frequencies.
The low output impedance and high bandwidth of the AD711
minimize high frequency feedthrough as shown in Figure 39.
The upper trace is that of another low-cost BiFET op amp
showing 17 dB more feedthrough at 5 MHz.
Figure 39.
9-POLE CHEBYCHEV FILTER
Figure 40 shows the AD711 and its dual counterpart, the
AD712, as a 9-pole Chebychev filter using active frequency de-
pendent negative resistors (FDNR). With a cutoff frequency of
50 kHz and better than 90 dB rejection, it may be used as an
anti-aliasing filter for a 12-bit Data Acquisition System with
100 kHz throughput.
As shown in Figure 40, the filter is comprised of four FDNRs
(A, B, C, D) having values of 4.9395 3 10–15 and 5.9276 3
10–15 farad-seconds. Each FDNR active network provides a
two-pole response; for a total of 8 poles. The 9th pole consists
of a 0.001 µF capacitor and a 124 kΩ resistor at Pin 3 of ampli-
fier A2. Figure 41 depicts the circuits for each FDNR with the
–11–
AD711
proper selection of R. To achieve optimal performance, the
0.001 µF capacitors must be selected for 1% or better matching
and all resistors should have 1% or better tolerance.

C1018b-20-3/88
Figure 40. 9-Pole Chebychev Filter

Figure 41. FDNR for 9-Pole Chebychev Filter Figure 42. High Frequency Response for 9-Pole
Chebychev Filter

OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Mini-DIP (N) Package Cerdip (Q) Package

PRINTED IN U.S.A.

TO-99 (H) Package Small Outline (R) Package

–12– REV. A