Name: NEELAKANDAN V

Student ID: 2021HT01042

Assignment2 (Embedded System Design)

1. It is proposed to use a microcontroller to design an ATM/CDM controller system

which is required to be modelled using UML before implementation. The function of
the system includes safe transactions, either withdrawal or deposit by the customer
through current account or savings account. The customer can also view the account
summary after a successful transaction by verifying the pin. The controller system is
linked to the respective bank to authenticate the transaction. Based on the above
description identify the classes and attributes required. Draw a UML class diagram
representation to model the behaviour of the system.
Answer:

The UML Class diagram is a graphical notation used to construct and visualize object

oriented systems. A class diagram in the Unified Modeling Language (UML) is a type of
static structure diagram that describes the structure of a system by showing the system's:
 classes,
 their attributes,
 operations (or methods),
 and the relationships among objects.
Class Name:
 The name of the class appears in the first partition.
Class Attributes:
 Attributes are shown in the second partition.
 The attribute type is shown after the colon.
 Attributes map onto member variables (data members) in code.
Class Operations (Methods):
 Operations are shown in the third partition. They are services the class provides.
 The return type of a method is shown after the colon at the end of the method
signature.
 The return type of method parameters are shown after the colon following the
parameter name. Operations map onto class methods in code
Classes and Attributes for ATM system are mentioned in first and second part of the
Class diagram respectively
 2. How is a DSP different from a microprocessor? What are the fixed point and floating-
point representations of a number and how are they handled by a DSP and a
microprocessor? Provide a description of the IEEE 754 and IEEE 754r formats of
representing a number.
Answer
Main difference between general purpose microprocessor and DSP is that, DSP has
Multiply and Accumulate Unit along with ALU, whereas GPP only has ALU
Other differences are given below
DSP GPP
Instructions are executed in single cycle of Multiple clocks cycles are required for
the clock. execution of one instruction.
Parallel execution is possible. Execution of instruction is always
sequential.
Program and Data memories are present on Normally on chip cache memory present,
chip extendable off chip. main memory is off chip.
Program sequencer and instruction register Program counter take care of flow of
take care of program flow. execution.
Pipelining is implicated through instruction Queuing is performed explicate by one
register and instruction cache. queue register to support pipelining.
Multiple operands can be fetched Operands are fetched sequentially.
simultaneously.
Address and data buses are not multiplexed. Address and data buses are multiplexed.
They are separate on chip as well as off
chip.
Three separate computational units: ALU, Only one main unit ALU.
MAC and shifter.
Direct and indirect addressing modes. Direct, Indirect, Register, Register indirect,
Immediate addressing mode etc.
Application: Signal processing, audio General Purpose applications.
processing, speech processing and array
processing etc

Fixed-Point Representation -

This representation has fixed number of bits for integer part and for fractional part. For
example, if given fixed-point representation is IIII.FFFF, then you can store minimum value
is 0000.0001 and maximum value is 9999.9999. There are three parts of a fixed-point number
representation: the sign field, integer field, and fractional field
Fixed-Point DSP
Fixed point DSP do vital arithmetic operation of type S xi * yi. It will have either multiplier
and ALU integrated or separate followed by operand registers, accumulators to store the
operands and results respectively. One or more shifter to handle result having size greater
than the basic size of DSP to shift the data before passing to ALU. Multiplier will support 2n
bits when n*n bits data as input. Accumulator will have guard bits to prevent overflow during
accumulation operations. When the result overflows, fixed point DSP handles using
saturation, truncation and convergent rounding.
1. Fixed point DSP hardware performs strictly integer arithmetic.
2. Fixed point DSPs usually represent each number with a minimum of 16 bits, although
a different length can be used.
3. Have single or multiple data paths, e.g. TI’s TMS320C62x™ have two data paths
operating in parallel,each with a 16-bit word width that provides signed integer values
within a range from –2^15 to 2^15.
4. In a fixed-point DSP, the programmer is responsible for performing the normalization
and scaling operation.

Floating-Point Representation -

This representation does not reserve a specific number of bits for the integer part or the
fractional part. Instead it reserves a certain number of bits for the number (called the mantissa
or significand) and a certain number of bits to say where within that number the decimal
place sits (called the exponent).

The floating number representation of a number has two part: the first part represents a
signed fixed point number called mantissa. The second part of designates the position of the
decimal (or binary) point and is called the exponent

Floating-Point DSP –
1. Floating-point DSPs support either integer or real arithmetic, the latter normalized in
the form of scientific notation.
2. Floating point DSPs typically use a minimum of 32 bits to store each value. They
divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either
for integer values or as the base of a real number, and an 8-bit exponent. The 16M
 range of precision offered by 24 bits with the addition of an 8-bit exponent, thus
supporting a vastly greater dynamic range than is available with the fixed-point
format.
3. Most floating point data paths can also do fixed pt. functions but only one of them can
be carried out per inst cycle.
4. Some floating point processors provide two data paths ->one for fixed pt. and the
other for floating point numbers. In such processors the fixed point data path usually
does not include a multiplier.
5. Floating point DSPs do not usually follow law of conservation of bits. In case of 32-
bit nos. By law of conservation of bits resultant mantissa must be 48 but in floating pt
DSP product is larger only by few bits (8/12).
6. In Floating point DSPs normalization and scaling operation happens automatically
offering greater dynamic range and precision.

IEEE 754 –

The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for
floating-point computation which was established in 1985 by IEEE.

IEEE 754 has 3 basic components:

1. The Sign of Mantissa –

This is as simple as the name. 0 represents a positive number while 1 represents a
negative number.
2. The Biased exponent –
The exponent field needs to represent both positive and negative exponents. A bias is
added to the actual exponent in order to get the stored exponent.
3. The Normalised Mantissa –
The mantissa is part of a number in scientific notation or a floating-point number,
consisting of its significant digits. Here we have only 2 digits, i.e. O and 1. So a
normalised mantissa is one with only one 1 to the left of the decimal.

IEEE 754 numbers are divided into two based on the above three components: single
precision and double precision.

According to IEEE 754 standard, the floating-point number is represented in following ways:

 Single Precision (32 bit): 1 sign bit, 8 bit exponent, and 23 bit mantissa.
 Double Precision (64 bit): 1 sign bit, 11 bit exponent, and 52 bit mantissa.

BIASED NORMALISED
TYPES SIGN BIAS
EXPONENT MANTISA
Single precision 1(31st bit) 8(30-23) 23(22-0) 127
Double
1(63rd bit) 11(62-52) 52(51-0) 1023
precision
IEEE 754r –

IEEE 754-2008 (previously known as IEEE 754r) was published in August 2008 and is a
significant revision to, and replaces, the IEEE 754-1985 floating-point standard, while in
2019 it was updated with a minor revision IEEE 754-2019. The 2008 revision extended the
previous standard where it was necessary, added decimal arithmetic and formats, tightened up
certain areas of the original standard which were left undefined, and merged in IEEE 854 (the
radix-independent floating-point standard).

Added enhancement to the original standard -

 Addition of a 16-bit and a 128-bit binary type.

o Half Precision (16 bit): 1 sign bit, 5 bit exponent, and 10 bit mantissa.
o Quadruple Precision (128 bit): 1 sign bit, 15 bit exponent, and 112 bit
mantissa.

BIASED NORMALISED
TYPES SIGN BIAS
EXPONENT MANTISA
Half precision 1(15th bit) 5(14-10) 10(9-0) 15
Double
1(127th bit) 14(126-113) 113(112-0) 8191
precision

 Introduced standards for representing decimal floating point numbers.

 Many of the definitions have been rewritten for clarification and consistency. A few
terms have been renamed for clarity (for example, denormalized has been renamed to
subnormal).
 The basic formats have 32-bit, 64-bit, and 128-bit encodings. Three new decimal
formats are described, matching the lengths of the 32–128-bit binary formats. These
give decimal interchange formats with 7, 16, and 34-digit significands, which may be
normalized or unnormalized. For maximum range and precision, the formats merge
part of the exponent and significand into a combination field, and compress the
remainder of the significand using either a decimal integer encoding (which uses
Densely Packed Decimal, or DPD, a compressed form of BCD) encoding or
conventional binary integer encoding. The basic formats are the two larger sizes,
which have 64-bit and 128-bit encodings. Generalized formulae for some other
interchange formats are also specified.Extended and extendable formats allow for
arithmetic at other precisions and ranges.
 New operations include fused multiply–add (FMA), explicit conversions,
classification predicates (isNan(x), etc.), various min and max functions, a total
ordering predicate, and two decimal-specific operations (samequantum and quantize).

IEEE 754-2008 decimal floating-point formats

decimal32 decimal64 decimal128 decimal(32k) Format

 1 1 1 1 Sign field (bits)
Combination
5 5 5 5
field (bits)
Exponent
6 8 12 w = 2×k + 4 continuation
field (bits)
Coefficient
20 50 110 t = 30×k−10 continuation
field (bits)
32 64 128 32×k Total size (bits)
p = 3×t/10+1 = Coefficient size
7 16 34
9×k−2 (decimal digits)
192 768 12288 3×2w = 48×4k Exponent range
Largest value is
96 384 6144 Emax = 3×2w−1
9.99...×10Emax
Smallest
normalized
−95 −383 −6143 Emin = 1−Emax
value is
1.00...×10Emin
Smallest non-
Etiny =
−101 −398 −6176 zero value is
2−p−Emax
1×10Etiny

Two different representations are defined:

 One with a binary integer significand field encodes the significand as a large binary
integer between 0 and 10p−1. This is expected to be more convenient for software
implementations using a binary ALU.
 Another with a densely packed decimal significand field encodes decimal digits more
directly. This makes conversion to and from binary floating-point form faster, but
requires specialized hardware to manipulate efficiently. This is expected to be more
convenient for hardware implementations.