LA-H811P Seite 5

A B C D E
MODEL NAME : Modena

PCB NO : LA-H811P
BOM P/N : 451AHT31L01 ~ L08
1 1
ZZZ LA-H811P
Dell/Compal Confidential
2 2
Schematic Document
(MODENA ICE Lake U)
CPU Option
UC1 QRGN@ UC1 QRVM@ UC1 QRGK@ UC1 QRJG@
SA0000CJ90L SA0000CJD1L SA0000CJ50L SA0000CJW0L

ICE LAKE QRGN ICE LAKE QRVM ICE LAKE QRGK ICE LAKE QRJG
3 3
TBT Option
URT1 BB@ URT2 BB@
2019-01-29
SA0000CAH1L SA0000CAH1L
Rev: 0.1 (X00)
JHL8040R QURW JHL8040R QURW
PD Option
UPD1 MP@ UPD2 MP@
SA0000C3N00 SA0000C3N00
TPS65987DDHRSHR TPS65987DDHRSHR
WLAN Option TPM Option

UWL1 KILLER@ U712 ST@
4 4
PK29S009L0L SA0000C5G10
KILLER1650S.01 ST33HTPH2032AHC1_VQFN32_5X5
EC Option
UE1 5105@ UE1 5106@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2020/10/01 Deciphered Date 2018/10/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P001 - Cover
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
SA00009GL30 SA0000C5D00 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1 (X00)
MEC5105_WFBGA169_11X11 MEC5106_WFBGA169_11X11 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H811P
Date: Tuesday, January 29, 2019 Sheet 1 of 100
A B C D E
A B C D E
PCH SPI
Flash ROM
32M
p.9
SPI
SPI#0 Hinge up
TPM2.0 eDP x4 lanes 13.3"FHD+/UHD+ Panel
DDI#A eDP v1.4b
ST/Nuvoton TPM chip p.66
p.38
M.2 SSD-Key M PCIe Gen3 x 4lanes PCIe#9,10,11,12

p.67 I2C Touch Screen Controller
I2C#0
p.38
1 LPDDR4 4GB X32x4 Memory Down 1
LPDDR4x 8/16/32 GB X32x4 Memory Down

Memory Bus
PCIe Gen2 x 1lane (LPDDR4/x)
WLAN/BT 5.1 Solder down 6 USB2.0
PCIe#3
Dual Channel
3733MHz
LPDDR4/x - ChA
Harrison Peak AX 22560 1 USB2#3 p.23,24
2
1
&Killer 1650-S 1216 SIP CNVi Gen2 Memory Bus
CNVi Gen2
(LPDDR4/x)
p.52
Dual Channel LPDDR4/x - ChB
SD4.0/SDXC Card Reader 4.0
3733MHz p.23,24 Middle Board CAM module
uSD Connector RealTek PCIe Gen2 x 1lane
SD_WP PCIe#16
p.70 RTS5242 PCIe to SD p.70 USB2.0 CSI
USB2#9 RGBIR Camera RGBIR Camera
GPIO (BIOS Controlled) Contrlller
SMBUS ISH_I2C
SML#0 ALS
ISH_I2C#1
TBT TBT
TBT#0
SBU 2 Burnside Bridge LSx / AUX
LSx / AUX
TBT Re-Timer I2C
SML#1
TPS65987-DH p.46,47 RT SPI USB2#8 DMIC FPC

Flash ROM
VBUS VBUS PP_HV1 8M
CHRG_IN p.46
USB Type-C DMIC DMIC 2xDMIC
PP_HV2 DMIC
TBT with PD 5VALW
(Left) CC 2 CC VCONN enable
2 2
I2C2
I2C1
I2C
PD SPI IceLake-U DMIC
IR SW IR LED
SPI Flash ROM
p.42
to EC
8M
p.42
4+2 P-sensor
USB2/I2C MUXES_L Audio Codec Universal
USB (Top) I2C HDA ALC3281-CG
HDA Headset Jack
USB (Bottom) USB p.57 p.39
p.43 p.56
p.50 SMBUS
I2C I2S
TBT ~4dB/2" TBT ~15dB / 7"
TBT#2
SBU 2 Burnside Bridge LSx / AUX
LSx / AUX
TBT Re-Timer I2C SPK Amp 2xSpeaker
TI TAS2770 p.57
RT SPI USB2#4 p.57
TPS65987-DH p.48,49
Flash ROM
VBUS VBUS PP_HV1 8M
CHRG_IN p.48
USB Type-C PP_HV2
5VALWB
TBT with PD CC 2 CC VCONN
(Right)
I2C2
I2C
I2C1 PD SPI USB2.0
p.44 SPI Flash ROM USB2#1
USB3.1 USB DCI Debug
8M USB3#2
to EC p.44 p.79
USB2/I2C MUXES_R
USB (Top) I2C
USB (Bottom) USB
3 3
p.45
p.50
Fingerprint module SMB
SMB MIPI60 Debug
p.79
Fingerprint Controller USB2.0

USB2#5
GOODIX GF5288+HT32
p.77
I2C
I2C#1
PWRBTN# GPP_D13
Power Button GPP_D14 eSPI
p.77
KB Transfer Board
SMBUS eSPI
+3V_NB_LID
SMB#03 eSPI
EC UART Debug/80 port MIPI60 Debug NB_LID#
GPIO Hall Sensor
YB8251
GPIO GPIO 161
SPI Programmer APS Debug (VCI_IN2#)
SMB#01
PD Programmer/I2C BIOS UART Debug BATBTN#
to Battery Gauge FPC GPIO
BC Bus KB Controller
EC BCM#1 ECE1117
Keyboard
DCI Debug JESPI Debug

MEC5106 PWM
SMBUS PWM#0 Fan 1
to PD & USB2/I2C MUXES SMB#04 p.77
Accelerometer
4
RT Programmer PWM LNG2DMTR 4
VCCIN Controller SMBUS PWM#1 Fan 2

SMB#05 p.77
MP2940AGRT p.91 +3V_NB_LID
Coin Cell PS/2
PS/2
Touchpad
Accelerometer
MCube MC3451
Battery Gauge
Charger SMBUS p.63
SMB#10
ISL9538B p.83 SMBUS Accelerometer
SMB#00 MCube MC3451
LEDs
Battery Connector p.33 p.63
p.82
A B
Hinge Down C D
Issued Date 2020/10/01 Deciphered Date 2018/10/01
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
Date:
E
P002 - Block Diagram
Document
LA-H811P
Number
Monday, January 28, 2019 Sheet 2 of 100

Rev
0.1 (X00)
A
Board ID Table PCIE/USB3.1

Vcc 3.3V +/- 5%
Board ID R C REV PCB Revision
0 240K +/- 1% 4700p X00 0.1 Flexible I/O Interface DESTINATION
1 130K +/- 5% 4700p X01 0.2
2 62K +/- 5% 4700p X02 0.3 0 PCI-E#1 / USB 3.1#1 None
3 33K +/- 5% 4700p
4 8.2K +/- 5% 4700p 1 PCI-E#2 / USB 3.1#2 USB DCI Debug
5 4.3K +/- 5% 4700p
6 2K +/- 5% 4700p 2 PCI-E#3 / USB 3.1#3 WLAN PCIe Gen2
7 1K +/- 5% 4700p N/A N/A
3 PCI-E#4 / USB 3.1#4 None
SMBUS Control Table Check

4
5
PCI-E#5 / USB 3.1#5
PCI-E#6 / USB 3.1#6

None
None
BATT VCCIN PD USB/I2C BurnSide
SOURCE PCH Connector Charger Controller Controller MIPI60 MUX Bridge Accel TI Amp.
6 PCI-E#7 None
PCH_SML0CLK PCH Reserve
PCH_SML0DATA 7 PCI-E#8 None
PCH_SML1CLK
PCH_SML1DATA
PCH
V V 8 PCI-E#9
SMBCLK
SMBDATA
PCH
V 9 PCI-E#10
M.2 SSD
EC_SMB03_CLK
EC_SMB03_DAT
MEC5106
V 10 PCI-E#11 / SATA#0
EC_SMB04_CLK
EC_SMB04_DAT
MEC5106
V V 11 PCI-E#12 / SATA#1a
EC_SMB05_CLK MEC5106 Reserve
EC_SMB05_DAT 12 PCI-E#13 None
EC_SMB10_CLK
EC_SMB10_DAT
MEC5106
V V 13 PCI-E#14 None
EC_SMB00_CLK
EC_SMB00_DAT
MEC5106
V 14 PCI-E#15 / SATA#1b None
EC_SMB01_CLK
EC_SMB01_DAT
MEC5106
V 15 PCI-E#16 / SATA#2 Card Reader PCIE GEN2
USB 2.0 CLK Thunderbolt 1
USB 2.0 PORT# DESTINATION DIFFERENTIAL DESTINATION TBT PORT# DESTINATION
1 USB DCI Debug CLKOUT_PCIE0 WLAN 0 USB Type-C_L
2 None CLKOUT_PCIE1 M.2 SSD TBT 1 None
3 None CLKOUT_PCIE2 None 2 USB Type-C_R
4 Type-C_R CLKOUT_PCIE3 None 3 None

CLK
5 FPR CLKOUT_PCIE4 Card Reader
6 None CLKOUT_PCIE5 None

Displayport
7 DDI PORT# DESTINATION
None
FLEX CLOCKS DESTINATION DDI A
8 4 Lane eDP
Type-C_L
ESPI_CLK EC eSPI B None
9 CAM
10 BT
Symbol Note :
@ : means de-pop
: means Digital Ground
: means Analog Ground

P003 - Notes List
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1 (X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H811P
Date: Monday, January 28, 2019 Sheet 3 of 100
A
5 4 3 2 1
Power Rail Modena POWER BLOCK DIAGRAM

Audio Power Rail UC22 CPU_C10_GATE#
2S2P Battery B+ +VCC1P8A
AOZ1334DI-01
51W
+1.8VPRIM UC25 AUD_PW R_EN
+1.8VS_AUDIO
TDC 1.9A AOZ1336DI
D PCH_PRIM_EN Peak Current 2.8A D
(NB691)
UC24 RUN_ON_P
Page:88 +1.8VS
PD1 AOZ1336DI
Type-C Port-L Controller
TPS65987DH
UC23 SUS_ON_P
+1.8V_MEM
EC_I2C AOZ1334DI-01
Buck-boost
Charger +3VALW
ISL9538B TDC 7.4A
(NVDC) ALWON_3VALW U7 ENVDD
Peak Current 10.5A +LCDVDD
Page:83 SY6288
B+ (NB502)
Page:84
EC_I2C VCCDSW_EN_GPIO
U31 +3V_PRIM
PD2 AOZ1331DI VCCDSW_EN_GPIO
Type-C Port-R +3VALW_DSW
Controller
TPS65987DH WLAN_PW R_EN
U34 +3VS_WLAN
AOZ1331DI TS_EN_R
B+ +3VS_TS
C B+ B+ B+ C
UC30 RUN_ON_P
+3VS
AOZ1336DI
VCCIN
IMVP_VR_ON_EN PL2 TDC 36A
Peak Current 62A
(MP2940A)
Page:91,92,93
US1 RUN_ON_P_R
+3VS_SSD
+VCC1.05_OUT_FET AOZ1336DI
UC13 VCCST_EN
+VCCST_CPU UC31 SD_PWR_EN
AOZ1334DI-01 +3VS_CR
SY6288
UC12 VCCSTG_EN
+VCCSTG_CPU UT1 3.3V_TBT_L_EN
AOZ1334DI-01 +3.3V_TBT_L
AOZ1336DI
VCCIN_AUX UT2 3.3V_TBT_R_EN

TDC 10A
+3.3V_TBT_R
1.8V_PRIM_PG AOZ1336DI
Peak Current 26A
(MP2941)
B Page:89,90 U713 TP_EN B
+3VS_TP
AOZ1336DI
+0.6V_VDDQ (LPDDR4X only)
0.6V_VDDQ_EN_P TDC 0.5A U55 3.3V_CAM_EN
Peak Current 0.72A +CAM_PWR
SY6288
(NB691)
Page:87
+1.1V_MEM UPD1
1.1V_MEM_EN TDC 4.2A +5VALW +5VALWB_L_TBT
TPS65987DH
Peak Current 6A ALWON_5VALW TDC 5.1A
(RT6243B) Peak Current 7.3A
Page:86 UC27 VCC_SFR_OC_EN (NB502) UC28 RUN_ON_P
+VCC_SFR_OC Page:85 +5VS
AOZ1334DI-01 AOZ1336DI
Q15 EN_INVPW R U60 RUN_ON_P

SI3457BDV +INV_PWR_SRC +5VALWB +5VBS
AOZ1336DI
ALWON_5VALWB TDC 3.5A
Peak Current 5A
(NB502) UPD2 +5VALWB_R_TBT
A
QZ10 IRCAM_EN Page:85 TPS65987DH A
SI3457BDV B+_CAM
U36 AUD_PW R_EN

AOZ1336DI +5VS_AUDIO

P004 - Power MAP
0.1 (X00)
Monday, January 28, 2019 4 100
Date: Sheet of
5 4 3 2 1
5 4 3 2 1
Power On Sequence Power Down Sequence

[AC in] [Battery only, AC absent] EC pay attention timing
[AC in] for VBU_L/VBU_R [Battery only, AC absent]

ITEM Measure Point Time ITEM Measure Point Time
TBT_VBUS Ta TBT_VBUS To +3V_LDO PCH_PLTRST#
Ta
PD Output CHR Output B+
Tb +3V_LDO To +CHG_VIN_20V
+3V_LDO
Tb Tc +CHG_VIN_20V To B+ Tc B+ To POWER_SW_IN# CPUPWRGD
PD Output +CHG_VIN_20V 200ms < Th Td B+ To ACAV_IN Th POWER_SW_IN# Low pluse width
Tc PWR_SW_IN#
Te ACAV_IN To ALWON Td POWER_SW_IN# To ALWON PCH_CLK_OUT PUT S
CHR Output B+
Td EC Output ALWON Td Tf ALWON To +3VALW Te ALWON To +3VALW
EC Input ACAV_IN Tg ALWON To +5VALW (+5VALWB) Tf ALWON To +5VALW (+5VALWB) SIO_SLP_S3#
Te VR Output +3VA LW Te
Th +3VALW To ALW_PWRGD_3V_5V Tg +3VALW To ALW_PWRGD_3V_5V
EC Output ALWON
Tf VR Output +5VALW (+5VALWB) Tf CPU_C10_GAT E#
D D
VR Output +3VA LW
Tg VR Output ALW_PWRGD_3V_5V Tg
SYS_PWROK
VR Output +5VALW (+5VALWB)
Th
VR Output ALW_PWRGD_3V_5V PCH_PWROK_P
IMVP_VR_ON_P(VCCST_PWRGD)
ITEM Measure Point Time

RUNPWROK(ALL_SYS_PWRGD)
T1 VCCDSW_EN_GPIO To +3VALW_DSW/+3V_PRIM
T2 +3VALW_DSW/+3V_PRIM To PCH_DPWROK +VCCIN
T3 PCH_DPWROK To SIO_SLP_SUS#
T4 SIO_SLP_SUS# To +1.8V_PRIM 3VS/+1.8VS/+5VS/+5VBS
T5 +1.8V_PRIM To +VCC1.05_OUT_PCH
200ms < Th
EC Input POWER_SW_IN# T6 +1.8V_PRIM To +VCC1.05_OUT_FET +VCCSTG_CPU
T7 +VCC1.05_OUT_FET To +VCCST_CPU
T8 +1.8V_PRIM To 1.8V_PRIM_PG
SIO_SLP_S4#
T9 1.8V_PRIM_PG To +VCCIN_AUX
T10 +VCCIN_AUX To VCCIN_AUX_VR_PG
EC pay attention timing +1.1V_MEM
T11 VCCIN_AUX_VR_PG To PCH_RSMRST#
T12 PCH_RSMRST# To ESPI_RESET# +0.6V_VDDQ
T13 ESPI_RESET# To AC_PRESENT
VCCDSW_EN_GPIO T14 SIO_SLP_S5# To SIO_SLP_S4#
T1 +1.8V_MEM
T15 SIO_SLP_S4# To SIO_SLP_S3#
+3VALW_DSW/+3V_PRIM(U31)
T2 T16 SIO_SLP_S4# To CPU_C10_GATE#
+VCC_SFR_OC
EC Output PCH_DPWROK T17 SIO_SLP_S4# To SIO_SLP_S0#
T3
PCH Output SIO_SLP_SUS#
T18 SIO_SLP_S4# To RUN_ON_EC
SIO_SLP_S5#
T4 T19 SIO_SLP_S4# To +1.1V_MEM
VR Output +1.8V_PRIM(PU500) T20 SIO_SLP_S4# To +0.6V_VDDQ
T5 +VCC1P05_OUTPUT_PLL
T21 SIO_SLP_S4# To +1.8V_MEM
PCH Output +VCC1.05_OUT _PCH
T6 T22 SIO_SLP_S4# To +1.8V_MEM PCH_RSMRST #
PCH Output +VCC1.05_OUT _FET T23 SIO_SLP_S4# To +VCC1P8A
T7
T24 SIO_SLP_S4# To +VCC_SFR_OC
+VCCST_CPU(UC13) PCH_DPWROK
T8 T25 RUN_ON_EC To +3VS
VR Output 1.8V_PRIM_PG T26 RUN_ON_EC To +1.8VS
T9 +3VALW_DSW/+3V_PRIM
T27 RUN_ON_EC To +5VS/+5VBS
C
PCH Output +VCCIN_AUX(PU900) C
T10 T28 RUN_ON_EC To +3.3VDX_SSD
SIO_SLP_SUS#
VR Output VCCIN_AUX_VR_PG T29 RUN_ON_EC To +SSD_PWR2
T11
T30 RUN_ON_EC To +SSD_PWR3
EC Output PCH_RSMRST # ESPI_RESET#
T12 T31 +3VS To RUNPWROK
PCH Output ESPI_RESET# T32 RUNPWROK To IMVP_VR_ON_P
T13 SIO_SLP_S0#
EC Output AC_PRESENT
T33 IMVP_VR_ON_P To +VCCIN
T34 +VCCIN To PCH_PWROK_P
+1.8V_PRIM
POWER_SW_IN# 16ms < T < 4s T35 PCH_PWROK_P To CPUPWRGD
T36 CPUPWRGD To SYS_PWROK +VCC1.05_OUT _PCH
PCH Output SIO_SLP_S5#
T37 SYS_PWROK To PCH_PLTRST#_EC
T14
+VCCIN_AUX
T15
PCH Output SIO_SLP_S3# +VCCST_CPU
T16
PCH Output CPU_C10_GAT E#
T17 SUSCLK
T18
EC Output RUN_ON_EC
T19
VR Output +1.1V_MEM(PU700)
T20
VR Output +0.6V_VDDQ(PU800)
T21
+1.8V_MEM(UC23)
T22
+VCCSTG_CPU(UC12)
T23
+VCC1P8A(UC22)
T24
+VCC_SFR_OC(UC27)
T25
+3VS(UC30)
T26
+1.8VS(UC24)
T27
+5VS(UC28)/+5VBS(U60)
T28
+3VS_SSD(US1)
B B
T29
EC Input RUNPWROK(ALL_SYS_PWRGD)
T30
EC Output IMVP_VR_ON_P(VCCST_PWRGD)
T31
VR Output +VCCIN(PU1100)
T32
VR Output PCH_PWROK_P
T33
CPUPWRGD
T34
EC Output SYS_PWROK
T35
PCH Output PCH_PLT RST #_EC
A A

P005 - Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Date: Sheet of
5 4 3 2 1
5 4 3 2 1
D D
UC1A
Y5 BB5
<38> EDP_TXN0 DDIA_TXN_0 TCP0_TX_N0 TBT_0_TTX_DRX_N0 <46>
Y3 BB6
<38> EDP_TXP0 DDIA_TXP_0 TCP0_TX_P0 TBT_0_TTX_DRX_P0 <46>
Y1 AV6
<38> EDP_TXN1 DDIA_TXN_1 TCP0_TX_N1 TBT_0_TTX_DRX_N1 <46>
Y2 AV5
<38> EDP_TXP1 DDIA_TXP_1 TCP0_TX_P1 TBT_0_TTX_DRX_P1 <46>
V2 BH2
<38> EDP_TXN2 DDIA_TXN_2 TCP0_TXRX_N0 TBT_0_TRX_DTX_N0 <46>
V1 BH1
eDP <38>
<38>
EDP_TXP2
EDP_TXN3
V3
V5
DDIA_TXP_2
DDIA_TXN_3
TCP0_TXRX_P0
TCP0_TXRX_N1
BF1
BF2
TBT_0_TRX_DTX_P0
TBT_0_TRX_DTX_N1
<46>
<46> TBT_L
<38> EDP_TXP3 DDIA_TXP_3 TCP0_TXRX_P1 TBT_0_TRX_DTX_P1 <46>
W4 AY5
<38> EDP_AUXN DDIA_AUX_N TCP0_AUX_N TBT_0_AUXN <46>
W3 AY6
<38> EDP_AUXP DDIA_AUX_P TCP0_AUX_P TBT_0_AUXP <46>
AE3 DDI
AE5 DDIB_TXN_0 AR5
AE2 DDIB_TXP_0 TCP1_TX_N0 AR6
AE1 DDIB_TXN_1 TCP1_TX_P0 AL5
AC5 DDIB_TXP_1 TCP1_TX_N1 AL3
AC3 DDIB_TXN_2 TCP1_TX_P1 BD2
AC1 DDIB_TXP_2 TCP1_TXRX_N0 BD1
AC2 DDIB_TXN_3 TCP1_TXRX_P0 BB1
DDIB_TXP_3 TCP1_TXRX_N1 BB2
AD3 TCP1_TXRX_P1
AD4 DDIB_AUX_N AN3
DDIB_AUX_P TCP1_AUX_N AN5
+3V_PRIM DP15 TCP1_AUX_P
DJ17 GPP_E22/DDPA_CTRLCLK/PCIE_LNK_DOWN TBT / USB / DP
GPP_E23/DDPA_CTRLDATA/BK4/SBK4 BF6
USB_OC1# TCP2_TX_N0 TBT_2_TTX_DRX_N0 <48>
10K_0201_5% 2 @ 1 RH742 DL40 BF5
GPP_H16/DDPB_CTRLCLK TCP2_TX_P0 TBT_2_TTX_DRX_P0 <48>
DP42 BJ5
GPP_H17/DDPB_CTRLDATA TCP2_TX_N1 TBT_2_TTX_DRX_N1 <48>
BJ6
C USB_OC2# TCP2_TX_P1 TBT_2_TTX_DRX_P1 <48> C
10K_0201_5% 2 @ 1 RH603 DL17 BL1
<46>
<46>
TBT_0_LSX_TX
TBT_0_LSX_RX
TBT_0_LSX_RX DK17 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD
TCP2_TXRX_N0
TCP2_TXRX_P0
BL2
BM2
TBT_2_TRX_DTX_N0
TBT_2_TRX_DTX_P0
<48>
<48> TBT_R
EDP_HPD TCP2_TXRX_N1 TBT_2_TRX_DTX_N1 <48>
100K_0201_5% 2 1 RH675 DN17 BM1
GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP2_TXRX_P1 TBT_2_TRX_DTX_P1 <48>
DP17
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD BG6
CPU_TCP0_HPD TCP2_AUX_N TBT_2_AUXN <48>
100K_0201_5% 2 @ 1 RH717 DK34 BG5
<48> TBT_2_LSX_TX TBT_2_LSX_RX GPP_D9/ISH_SPI_CS_N/DDP3_CTRLCLK/GSPI2_CS0_N/TBT_LSX2_TXD TCP2_AUX_P TBT_2_AUXP <48>
DL34
USB_OC1# <48> TBT_2_LSX_RX GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD
100K_0201_5% 2 @ 1 RH718
DN33 BP6
DL33 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD TCP3_TX_N0 BP5
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD TCP3_TX_P0 BV5
EDP_HPD DW11 TCP3_TX_N1 BV6
<38,58> EDP_HPD GPP_E14/DPPE_HPDA/DISP_MISCA TCP3_TX_P1
CV42 BR1
CPU_TCP0_HPD CV39 GPP_A18/DDSP_HPDB/DISP_MISCB TCP3_TXRX_N0 BR2
CY43 GPP_A19/DDSP_HPD1/DISP_MISC1 TCP3_TXRX_P0 BT2
<38> TS_DET USB_OC1# GPP_A20/DDSP_HPD2/DISP_MISC2 TCP3_TXRX_N1
CR41 BT1
USB_OC2# CT41 GPP_A14/USB_OC1_N/DDSP_HPD3/DISP_MISC3 TCP3_TXRX_P1
DV14 GPP_A15/USB_OC2_N/DDSP_HPD4/DISP_MISC4 BT6
<38> TS_INT# GPP_E17 TCP3_AUX_N BT5
DN21 TCP3_AUX_P
<38> ENVDD_PCH EDP_VDDEN TCRCOMP_DN RC1
DL19 AY1 1 2 150_0201_1%
<10,38> PANEL_BKLEN EDP_BKLTEN TC_RCOMP_N TCRCOMP_DP
DU19 AY2 +3V_PRIM
<38> EDP_BIA_PWM EDP_BKLTCTL TC_RCOMP_P
1 PAD~D TP@ RSVD_1 J3
TP99 RSVD_1 RTC_DET#
CT38 1 @ 2
GPP_A17/DISP_MISCC RTC_DET#_R <63>
1 PAD~D TP@ DISP_UTILS D2 CV43 RH734 0_0201_5% KB_DET# RH672 1 2 10K_0201_5%
150_0201_1% TP69 DP_RCOMP DISP_UTILS GPP_A21 3.3V_CAM_EN <71>
2 1 RC3 R2 CV41
DISP_RCOMP GPP_A22 KB_DET# <63>
1 0f 19
ICL-U_BGA1526
@
+3V_PRIM +3V_PRIM
B B
1
R6172 @ R6174 @
4.7K_0201_5% 4.7K_0201_5%
2
TBT_0_LSX_RX TBT_2_LSX_RX
2
RC691 RC693
20K_0201_5% 20K_0201_5%
1
TBT LSX #0 PINS VCCIO CONFIGURATION TBT LSX #2 PINS VCCIO CONFIGURATION
HIGH 3.3V HIGH 3.3V

LOW 1.8V LOW 1.8V
PLACE CLOSE TO THE SIGNAL TO AVOID STUB
A A

P006 - ICL-U(1/13)TCSS,EDP
5 4 3 2 1
5 4 3 2 1
Memory connection refer 573975 Rev1P1

D D
UC1B
CA48 LP4(NIL) / DDR4(NIL) LP4(NIL) / DDR4(NIL) BL48

<23> DDR_A_D0_0 DDRA_DQ0_0/DDR0_DQ0_0 DDRA_CLK_N/DDR0_CLK_N_0 DDR_A_CLK# <23>
CA47 BL47
<23> DDR_A_D0_1 DDRA_DQ0_1/DDR0_DQ0_1 DDRA_CLK_P/DDR0_CLK_P_0 DDR_A_CLK <23>
CA49 BF42
<23> DDR_A_D0_2 DDRA_DQ0_2/DDR0_DQ0_2 DDRB_CLK_N/DDR0_CLK_N_1 DDR_B_CLK# <23>
BV49 BF43
<23> DDR_A_D0_3 DDRA_DQ0_3/DDR0_DQ0_3 DDRB_CLK_P/DDR0_CLK_P_1 DDR_B_CLK <23>
CA45
<23> DDR_A_D0_4 DDRA_DQ0_4/DDR0_DQ0_4
BV47 BG49
<23> DDR_A_D0_5 DDRA_DQ0_5/DDR0_DQ0_5 DDRA_CKE0/DDR0_CKE0 DDR_A_CKE0 <23>
BV45 BJ47
<23> DDR_A_D0_6 DDRA_DQ0_6/DDR0_DQ0_6 DDRA_CKE1/NC DDR_A_CKE1 <23>
BV48 BF38
<23> DDR_A_D0_7 DDRA_DQ0_7/DDR0_DQ0_7 DDRB_CKE0/NC DDR_B_CKE0 <23>
CC42 BF41
<23> DDR_A_D1_0 DDRA_DQ1_0/DDR0_DQ1_0 DDRB_CKE1/DDR0_CKE1 DDR_B_CKE1 <23>
CC39
CC43 BM38
<23> DDR_A_D1_2 DDRA_DQ1_2/DDR0_DQ1_2 DDRA_CS_0/DDR0_CS#0 DDR_A_CS#0 <23>
CE38 BM42
<23> DDR_A_D1_3 DDRA_DQ1_3/DDR0_DQ1_3 DDRA_CS_1/NC DDR_A_CS#1 <23>
CC38 BP42
<23> DDR_A_D1_4 DDRA_DQ1_4/DDR0_DQ1_4 DDRB_CS_0/NC DDR_B_CS#0 <23>
CE39 BG42
<23> DDR_A_D1_5 DDRA_DQ1_5/DDR0_DQ1_5 DDRB_CS_1/DDR0_CS#1 DDR_B_CS#1 <23>
CE42
CE43 BM43
<23> DDR_A_D1_7 DDRA_DQ1_7/DDR0_DQ1_7 DDRB_CA4/DDR0_BA0 DDR_B_CA4 <23>
BT48 BG39
<23> DDR_A_D2_0 DDRA_DQ2_0/DDR0_DQ2_0 NC/DDR0_BA1
BT47
BT49 BB49
<23> DDR_A_D2_2 DDRA_DQ2_2/DDR0_DQ2_2 DDRA_CA5/DDR0_BG0 DDR_A_CA5 <23>
BN49 BD47
<23> DDR_A_D2_3 DDRA_DQ2_3/DDR0_DQ2_3 NC/DDR0_BG1
BT45
C BN47 BB48 C
<23> DDR_A_D2_5 DDRA_DQ2_5/DDR0_DQ2_5 NC/DDR0_MA0
BN45 BL49
BN48 BG38
<23> DDR_A_D2_7 DDRA_DQ2_7/DDR0_DQ2_7 DDRB_CA5/DDR0_MA2 DDR_B_CA5 <23>
BV42 BL45
BV39 BJ46
BV43 BG48
<23> DDR_A_D3_2 DDRA_DQ3_2/DDR0_DQ3_2 DDRA_CA0/DDR0_MA5 DDR_A_CA0 <23>
BW38 BE45
BV38 BG45
BW39 BG47
BW42 BE47
BW43 BJ38
AY48 BB47
<23> DDR_B_D0_0 DDRB_DQ0_0/DDR0_DQ4_0 NC/DDR0_MA11
AY47 BE48
<23> DDR_B_D0_1 DDRB_DQ0_1/DDR0_DQ4_1 NC/DDR0_MA12
AY49 BM39
<23> DDR_B_D0_2 DDRB_DQ0_2/DDR0_DQ4_2 DDRB_CA0/DDR0_MA13 DDR_B_CA0 <23>
AU45 BG43
<23> DDR_B_D0_3 DDRB_DQ0_3/DDR0_DQ4_3 DDRB_CA2/DDR0_MA14WE# DDR_B_CA2 <23>
AY45 BJ42
<23> DDR_B_D0_4 DDRB_DQ0_4/DDR0_DQ4_4 DDRB_CA1/DDR0_MA15CAS# DDR_B_CA1 <23>
AU47 BM41
<23> DDR_B_D0_5 DDRB_DQ0_5/DDR0_DQ4_5 DDRB_CA3/DDR0_MA16RAS# DDR_B_CA3 <23>
AU48
<23> DDR_B_D0_6 DDRB_DQ0_6/DDR0_DQ4_6
AU49 BJ39
<23> DDR_B_D0_7 DDRB_DQ0_7/DDR0_DQ4_7 NC/DDR0_ODT_0
AY42 BB45
<23> DDR_B_D1_0 DDRB_DQ1_0/DDR0_DQ5_0 NC/DDR0_ODT_1
AY38
AY43 BY47 DDR_A_DQS#0 <23>
<23> DDR_B_D1_2 DDRB_DQ1_2/DDR0_DQ5_2 DDRA_DQSN_0/DDR0_DQSN_0
BB39 BY46 DDR_A_DQS0 <23>
<23> DDR_B_D1_3 DDRB_DQ1_3/DDR0_DQ5_3 DDRA_DQSP_0/DDR0_DQSP_0
AY39 CC41 DDR_A_DQS#1 <23>
BB38 CE41 DDR_A_DQS1 <23>
BB42 BR47 DDR_A_DQS#2 <23>
BB43 BR46 DDR_A_DQS2 <23>
AR48 BV41 DDR_A_DQS#3 <23>
AR47 BW41 DDR_A_DQS3 <23>
B <23> DDR_B_D2_1 DDRB_DQ2_1/DDR0_DQ6_1 DDRA_DQSP_3/DDR0_DQSP_3 B
AR49 AV46 DDR_B_DQS#0 <23>
<23> DDR_B_D2_2 DDRB_DQ2_2/DDR0_DQ6_2 DDRB_DQSN_0/DDR0_DQSN_4
AM45 AV47 DDR_B_DQS0 <23>
<23> DDR_B_D2_3 DDRB_DQ2_3/DDR0_DQ6_3 DDRB_DQSP_0/DDR0_DQSP_4
AR45 AY41 DDR_B_DQS#1 <23>
AM47 BB41 DDR_B_DQS1 <23>
AM48 AN46 DDR_B_DQS#2 <23>
AM49 AN47 DDR_B_DQS2 <23>
<23> DDR_B_D3_0
AT42
DDRB_DQ3_0/DDR0_DQ7_0 DDRB_DQSN_3/DDR0_DQSN_7
AR41 DDR_B_DQS#3 <23> +1.1V_MEM
AT39 AT41 DDR_B_DQS3 <23>
AR43
AT38 BF39
<23> DDR_B_D3_3
AR38
DDRB_DQ3_3/DDR0_DQ7_3 NC/DDR0_PAR
BE49
BF39,BE49 SDS CRB P.8 NC
<23> DDR_B_D3_4 DDRB_DQ3_4/DDR0_DQ7_4 NC/DDR0_ACT#
2
AR39 BD46 M_0_ALERT_N RH11 1 2 0_0201_5%
<23> DDR_B_D3_5 DDRB_DQ3_5/DDR0_DQ7_5 NC/DDR0_ALERT#
AR42 RH12
AT43 M38 470_0201_1%
<23> DDR_B_D3_7 DDRB_DQ3_7/DDR0_DQ7_7 RSVD_73
C44
100_0201_1% 2 1 RC12 DDR_COMP_0 D47 DDR0_VREF_CA B45
M38,C44,B45 SDS CRB P.8 NC
1
100_0201_1% 2 DDR_COMP_1 DDR_RCOMP_0 DDR1_VREF_CA
1 RC13 E46 M39
100_0201_1% 2 DDR_COMP_2 DDR_RCOMP_1 DDR_VTT_CTL DDR_DRAMRST#
1 RC14 C47 DK47 RH42 1 2 0_0201_5%
DDR_RCOMP_2 2 of 19 DRAM_RESET# DDR_DRAMRST#_R <23,24>
ICL-U_BGA1526
M39 (DDR_VTT_CTL) is DDR4 System Memory Power Gate 1
@ Control Buf f er us e , L PDDR4/x don' t us e. CC740 @

Processor EDS Rev0p7 P.118,119 #572795 0.1U_0201_10V6K
2
SDS CRB NC
C44(DDR0_VREF_CA),B45(DDR1_VREF_CA) for DDR4 used only
LPDDR4/4x has all Vref Internal inside the DRAMS
Rev.0.91 PDG P.112 #572907
A A

P007 - ICL-U(2/13)LPDDR4/x
5 4 3 2 1
5 4 3 2 1
D D

UC1C
LP4(NIL) / DDR4(NIL) LP4(NIL) / DDR4(NIL)

AK48 Y48
<24> DDR_C_D0_0 DDRC_DQ0_0/DDR1_DQ0_0 DDRC_CLK_N/DDR1_CLK_N_0 DDR_C_CLK# <24>
AK45 Y47
<24> DDR_C_D0_1 DDRC_DQ0_1/DDR1_DQ0_1 DDRC_CLK_P/DDR1_CLK_P_0 DDR_C_CLK <24>
AK49 M43
<24> DDR_C_D0_2 DDRC_DQ0_2/DDR1_DQ0_2 DDRD_CLK_N/DDR1_CLK_N_1 DDR_D_CLK# <24>
AG47 M42
<24> DDR_C_D0_3 DDRC_DQ0_3/DDR1_DQ0_3 DDRD_CLK_P/DDR1_CLK_P_1 DDR_D_CLK <24>
AK47
<24> DDR_C_D0_4 DDRC_DQ0_4/DDR1_DQ0_4
AG45 U45
<24> DDR_C_D0_5 DDRC_DQ0_5/DDR1_DQ0_5 DDRC_CKE0/DDR1_CKE0 DDR_C_CKE0 <24>
AG48 V46
<24> DDR_C_D0_6 DDRC_DQ0_6/DDR1_DQ0_6 DDRC_CKE1/NC DDR_C_CKE1 <24>
AG49 M41
<24> DDR_C_D0_7 DDRC_DQ0_7/DDR1_DQ0_7 DDRD_CKE0/NC DDR_D_CKE0 <24>
AJ38 P43
<24> DDR_C_D1_0 DDRC_DQ1_0/DDR1_DQ1_0 DDRD_CKE1/DDR1_CKE1 DDR_D_CKE1 <24>
AL39
AJ39 V42
<24> DDR_C_D1_2 DDRC_DQ1_2/DDR1_DQ1_2 DDRC_CS_0/DDR1_CS#0 DDR_C_CS#0 <24>
AL43 V39
<24> DDR_C_D1_3 DDRC_DQ1_3/DDR1_DQ1_3 DDRC_CS_1/NC DDR_C_CS#1 <24>
AL38 Y39
<24> DDR_C_D1_4 DDRC_DQ1_4/DDR1_DQ1_4 DDRD_CS_0/NC DDR_D_CS#0 <24>
AJ42 T39
<24> DDR_C_D1_5 DDRC_DQ1_5/DDR1_DQ1_5 DDRD_CS_1/DDR1_CS#1 DDR_D_CS#1 <24>
AL42
AJ43 T38
<24> DDR_C_D1_7 DDRC_DQ1_7/DDR1_DQ1_7 DDRD_CA4/DDR1_BA0 DDR_D_CA4 <24>
AB49 T42
<24> DDR_C_D2_0 DDRC_DQ2_0/DDR1_DQ2_0 NC/DDR1_BA1
C AB48 C
AE49 R45
<24> DDR_C_D2_2 DDRC_DQ2_2/DDR1_DQ2_2 DDRC_CA5/DDR1_BG0 DDR_C_CA5 <24>
AE47 N47
<24> DDR_C_D2_3 DDRC_DQ2_3/DDR1_DQ2_3 NC/DDR1_BG1
AE48
AB47 P42
<24> DDR_C_D2_5 DDRC_DQ2_5/DDR1_DQ2_5 NC/DDR1_MA0
AB45 Y49
AE45 U48
<24> DDR_C_D2_7 DDRC_DQ2_7/DDR1_DQ2_7 DDRD_CA5/DDR1_MA2 DDR_D_CA5 <24>
AD38 Y45
AD39 U47
AE39 R49
<24> DDR_C_D3_2 DDRC_DQ3_2/DDR1_DQ3_2 DDRC_CA0/DDR1_MA5 DDR_C_CA0 <24>
AE43 U49
AE38 M47
AD43 M45
AD42 R47
AE42 P39
J48 N46
<24> DDR_D_D0_0 DDRD_DQ0_0/DDR1_DQ4_0 NC/DDR1_MA11
J45 R48
<24> DDR_D_D0_1 DDRD_DQ0_1/DDR1_DQ4_1 NC/DDR1_MA12
J49 Y41
<24> DDR_D_D0_2 DDRD_DQ0_2/DDR1_DQ4_2 DDRD_CA0/DDR1_MA13 DDR_D_CA0 <24>
G47 V41
<24> DDR_D_D0_3 DDRD_DQ0_3/DDR1_DQ4_3 DDRD_CA2/DDR1_MA14WE# DDR_D_CA2 <24>
J47 Y42
<24> DDR_D_D0_4 DDRD_DQ0_4/DDR1_DQ4_4 DDRD_CA1/DDR1_MA15CAS# DDR_D_CA1 <24>
G45 V47
<24> DDR_D_D0_5 DDRD_DQ0_5/DDR1_DQ4_5 DDRD_CA3/DDR1_MA16RAS# DDR_D_CA3 <24>
G48
<24> DDR_D_D0_6 DDRD_DQ0_6/DDR1_DQ4_6
E48 V43
<24> DDR_D_D0_7 DDRD_DQ0_7/DDR1_DQ4_7 NC/DDR1_ODT_0
J38 V38
<24> DDR_D_D1_0 DDRD_DQ1_0/DDR1_DQ5_0 NC/DDR1_ODT_1
G39
G38 AH46 DDR_C_DQS#0 <24>
<24> DDR_D_D1_2 DDRD_DQ1_2/DDR1_DQ5_2 DDRC_DQSN_0/DDR1_DQSN_0
G42 AH47 DDR_C_DQS0 <24>
<24> DDR_D_D1_3 DDRD_DQ1_3/DDR1_DQ5_3 DDRC_DQSP_0/DDR1_DQSP_0
J39 AJ41 DDR_C_DQS#1 <24>
J42 AL41 DDR_C_DQS1 <24>
B <24> DDR_D_D1_5 DDRD_DQ1_5/DDR1_DQ5_5 DDRC_DQSP_1/DDR1_DQSP_1 B
G43 AC47 DDR_C_DQS#2 <24>
J43 AC46 DDR_C_DQS2 <24>
B43 AE41 DDR_C_DQS#3 <24>
D43 AD41 DDR_C_DQS3 <24>
A43 H47 DDR_D_DQS#0 <24>
<24> DDR_D_D2_2 DDRD_DQ2_2/DDR1_DQ6_2 DDRD_DQSN_0/DDR1_DQSN_4
C40 H46 DDR_D_DQS0 <24>
<24> DDR_D_D2_3 DDRD_DQ2_3/DDR1_DQ6_3 DDRD_DQSP_0/DDR1_DQSP_4
C43 G41 DDR_D_DQS#1 <24>
D40 J41 DDR_D_DQS1 <24>
B40 C42 DDR_D_DQS#2 <24>
A40 D42 DDR_D_DQS2 <24>
B35 D36 DDR_D_DQS#3 <24>
D35 C36 DDR_D_DQS3 <24>
A35
D38 P38
<24> DDR_D_D3_3
C35
DDRD_DQ3_3/DDR1_DQ7_3 NC/DDR1_PAR
M48
P38,M48 SSD CRB NC
<24> DDR_D_D3_4 DDRD_DQ3_4/DDR1_DQ7_4 NC/DDR1_ACT# M_1_ALERT_N
C38 M49 RH13 2 1 0_0201_1%
<24> DDR_D_D3_5 DDRD_DQ3_5/DDR1_DQ7_5 NC/DDR1_ALERT#
B38
A38
<24> DDR_D_D3_7 DDRD_DQ3_7/DDR1_DQ7_7 3 of 19
ICL-U_BGA1526
@
A A

P008 - ICL-U(3/13)LPDDR4/x
5 4 3 2 1
5 4 3 2 1
BOOT HALT CONSENT STRAP A0 PERSONALITY STRAP TLS CONFIDENTIALITY ESPI OR EC LESS
SPI0_MOSI(NO INTERNAL PU/PD) SPI0_IO2(NO INTERNAL PU/PD) SPI0_IO3 GPP_C2/SMBALERT#(INTERNAL PD 20K) GPP_C5 (Internal 20 K internal Pull Down): SML0ALERT#
0 = Enable 0 = Enable 0 = Enable 0 = TLS CONFIDENTIALITY DISABLE 0 = Enable eSPI. (Default)

1 = Disable +V3.3A_1.8A_PCH_SPI 1 = Disable +V3.3A_1.8A_PCH_SPI 1 = Disable +V3.3A_1.8A_PCH_SPI 1 = TLS CONFIDENTIALITY ENABLE +3V_PRIM 1 = Disable eSPI. +3V_PRIM
RH643 1 2 100K_0201_5% RH141 1 2 100K_0201_5% RH635 1 2 100K_0201_5% RH666 1 @ 2 4.7K_0201_5%
SOC_SPI_0_D0 RH641 1 @ 2 4.7K_0201_5% SOC_SPI_0_D2 RH142 1 @ 2 4.7K_0201_5% SOC_SPI_0_D3 RH636 1 @ 2 100K_0201_5% GPP_C2 RH692 1 2 4.7K_0201_5% GPP_C5 RH98 1 @ 2 20K_0201_5%
D D
UC1E
SOC_SPI_0_CLK_R RH719 1 2 4.99_0201_1% SOC_SPI_0_CLK DB42

<66> SOC_SPI_0_CLK_R SOC_SPI_0_D0_R SOC_SPI_0_D0 SPI0_CLK
RH720 1 2 4.99_0201_1% Strap Pin DD43 DK27
<66> SOC_SPI_0_D0_R SOC_SPI_0_D1_R SOC_SPI_0_D1 SPI0_MOSI GPP_C0/SMBCLK SMB_CLK <79>
RH721 1 2 4.99_0201_1% DF43 DP24
<66> SOC_SPI_0_D1_R SOC_SPI_0_D2_R RH722 1 2 4.99_0201_1% SOC_SPI_0_D2 SPI0_MISO SMBUS GPP_C1/SMBDATA GPP_C2 SMB_DATA <79> MIPI60
Strap Pin DF42 DL24
SOC_SPI_0_D3_R RH723 1 2 4.99_0201_1% SOC_SPI_0_D3 DD41 SPI0_IO2 SPI 0 GPP_C2/SMBALERT#
Strap Pin
SOC_SPI_0_CS#0_R RH736 1 2 0_0201_5% SOC_SPI_0_CS#0 DB43 SPI0_IO3 +3V_PRIM
SOC_SPI_0_CS#1_R RH735 1 2 0_0201_5% SOC_SPI_0_CS#1 DF41 SPI0_CS0# DK24 SML0_SMBCLK
SOC_SPI_0_CS#2 DB41 SPI0_CS1# GPP_C3/SML0CLK DJ24 SML0_SMBDATA SML0_SMBCLK <46,48> BB_L&BB_R
<66> SOC_SPI_0_CS#2 SPI0_CS2# SML 0 GPP_C4/SML0DATA DP22 GPP_C5 SML0_SMBDATA <46,48> (For support Vpro)
GPP_C5/SML0ALERT# SML0_SMBDATA 499_0201_1% 1 2 RH144
DV16 SML0_SMBCLK 499_0201_1% 1 2 RH143
RH687 1 2 100K_0201_5% SOC_SPI_0_CLK DT16 GPP_E11/SPI1_CLK/BK1/SBK1 DN22 SML1_SMBCLK
GPP_E13/SPI1_MOSI/BK3/SBK3 GPP_C6/SML1CLK/SUSWARN_N/SUSPWRDNACK SML1_SMBDATA SML1_SMBCLK <42,44,46,48> BB_L&BB_R
DU18 DL22
DT18 GPP_E12/SPI1_MISO/BK2/SBK2 SPI 1
SML1 GPP_C7/SML1DATA/SUSACK# PD_L&PD_R
SML1_SMBDATA <42,44,46,48> SML1_SMBCLK 1K_0201_5% 1 2 RH606
DW18 GPP_E1/SPI1_IO2 SML1_SMBDATA 1K_0201_5% 1 2 RH607
1K_0201_5% 1 2 RH640 SOC_SPI_0_D0 DW16 GPP_E2/SPI1_IO3 CR47 ESPI_CLK RC569 2 1 49.9_0201_1%
<79> MIPI60_SPI0_MOSI MIPI60@ GPP_E10/SPI1_CS_N/BK0/SBK0 GPP_A5/ESPI_CLK ESPI_IO0_R RC336 10_0201_1% ESPI_CLK_5105 <58,79>
DU16 CN45 1 2
SOC_SPI_0_D2 GPP_E8/SATALED#/SPI1_CS1# GPP_A0/ESPI_IO0 ESPI_IO1_R ESPI_IO0 <58,79> ESPI_CS#
1K_0201_5% 1 2 RH634 CN48 RC367 1 2 10_0201_1% 75K_0201_1% 1 @ 2 RC712
<79> MIPI60_SPI0_IO2 GPP_A1/ESPI_IO1 ESPI_IO2_R ESPI_IO1 <58,79> ESPI_RESET#
MIPI60@ CN49 RC368 1 2 10_0201_1% 75K_0201_1% 1 2 RC711
DV19 eSPI GPP_A2/ESPI_IO2 CN47 ESPI_IO3_R RC369 1 2 10_0201_1%
ESPI_IO2 <58,79> ESPI 1.8V
CL_CLK GPP_A3/ESPI_IO3 ESPI_CS# ESPI_IO3 <58,79>
DW19 MLINK CT45
NO support C-Link DT19 CL_DATA
CL_RST#
GPP_A4/ESPI_CS#
GPP_A6/ESPI_RESET#
CR46 ESPI_RESET# ESPI_CS# <58,79>
ESPI_RESET# <58,79>
5 of 19
Closed to ROM ICL-U_BGA1526
C SPI_0_D0_ROM SOC_SPI_0_D0_R C
RH23 1 2 49.9_0201_1% @
SPI_0_CLK_ROM RH24 1 2 49.9_0201_1% SOC_SPI_0_CLK_R Serial Peripheral Interface (SPI) Topology Guidelines
SPI_0_D1_ROM RH25 1 2 49.9_0201_1% SOC_SPI_0_D1_R
SPI_0_D2_ROM RH26 1 2 49.9_0201_1% SOC_SPI_0_D2_R EMI Request
SPI_0_D3_ROM RH27 1 2 49.9_0201_1% SOC_SPI_0_D3_R SOC_SPI_0_CLK
PCH SPI RF Request
1
@RF@
SMB_CLK CC655 1 2 33P_0201_50V8J
RC734 @EMI@
TPM 33_0201_5%
SML0_SMBCLK CC656
@RF@
1 2 33P_0201_50V8J
2
@RF@
JSPI 1
SML1_SMBCLK CC657 1 2 33P_0201_50V8J
NPI pop D20 JSPI1 2

CC659 @EMI@
33P_0201_50V8J ESPI_CLK_5105 CC658
@RF@
1 2 33P_0201_50V8J
MP pop RC745 SOC_SPI_0_CS#1_R

SOC_SPI_0_D0_R
1
1
SPI ROM ( 32MByte )

2
D20 SOC_SPI_0_D1_R 3 2
+3V_PRIM SOC_SPI_0_CLK_R 3
ROM is Quad SPI

+3V_SPI 1 2 4
SOC_SPI_0_CS#0_R 5 4
RB751S40T1G_SOD523-2 6 5 11
<78> PROM_BIOS_R
SOC_SPI_0_D3_R 6 G1
UH8 7 12
SOC_SPI_0_CS#0_R 1 8 2 @ 1 8 7 G2
SPI_0_D1_ROM CS# VCC SPI_0_D3_ROM +3V_SPI 8
2 7 0_0402_5% RC745 9
SPI_0_D2_ROM DO IO3 SPI_0_CLK_ROM 1 9
3 6 CH35 10
4 IO2 CLK 5 SPI_0_D0_ROM 10
GND DI 9 0.1U_0201_10V6K ACES_50521-01041-P01_10P
ThemalPad 2 CONN@
W25Q256JVEIQ_WSON8_8X6
XTAL_38P4M_IN PCH_RTCX2
Follow Pebble Creek MLK
+3V_SPI XTAL_38P4M_OUT RH17 1 2 200K _0201_1% PCH_RTCX1 RH16 1 2 10M_0201_1%
@ UH9
2
SOC_SPI_0_CS#0_R 1 8
CS# VCC YH1 RH637
B B
SPI_0_D1_ROM 2 7 SPI_0_D3_ROM 1 3 0_0201_5%
SO/SIO1 RESET#/SIO3 2 4
SPI_0_D2_ROM 3 6 SPI_0_CLK_ROM
2 2
1
WP#/SIO2 SCLK 38.4MHZ_10PF_8Y38420005 YC1
4 5 SPI_0_D0_ROM CH10 CH11 1 2 PCH_RTCX2_R
GND SI/SIO0 10P_0201_50V8J 10P_0201_50V8J
1 1
MX25L25645GM2I-10G_SO8
32.768KHZ_12.5PF_9H03200042
Reserve SO8 footprint for BIOS debug conn 1 CRB XTAL ESR = 50K MAX 1
Intel SPEC :
CH12 CH13
CL = Specified Crystal Capacitive Load = 10 pF 15P_0201_50V8J 15P_0201_50V8J
UC1J Series Resistance < or = 30 Ω 2 2
Frequency Tolerance < or 100 PPM
Aging ± 3 PPM
<52> CLK_PCIE_N0 CJ3 CF5
CJ5 CLKOUT_PCIE_N0 CLKOUT_PCIE_N5 CF3
<52> CLK_PCIE_P0 CLKOUT_PCIE_P0 CLKOUT_PCIE_P5
RH40 1 2 10K_0201_5% DK33 DP40 SUSCLK
WLAN---> +3VS GPP_D5/SRCCLKREQ0# GPP_H11/SRCCLKREQ5#
<52> CLKREQ_PCIE#0
<67> CLK_PCIE_N1 CL2 1
CL1 CLKOUT_PCIE_N1 DL48 PCH_RTCX1 CH49 @EMI@
<67> CLK_PCIE_P1 CLKOUT_PCIE_P1 RTCX1 PCH_RTCX2
RH727 1 2 10K_0201_5% DN34 RTC DL49
SSD--> +3VS GPP_D6/SRCCLKREQ1# RTCX2 0.1U_0201_10V6K +RTCVCC_R
<67> CLKREQ_PCIE#1 PCH_RTCRST# 2 1
CL3 DT47
CLKOUT_PCIE_N2 RTCRST# PCH_RTCRST# <63,79>
CL5 DK46 SRTCRST# CH47
DP34 CLKOUT_PCIE_P2 SRTCRST# 1U_0201_6.3V6K
GPP_D7/SRCCLKREQ2# DF49 SUSCLK 1 2 2 PCH_RTCRST#
GPD8/SUSCLK SUSCLK <52,67> RH573 20K_0201_5%
CK3
CK4 CLKOUT_PCIE_N3 1 2 SRTCRST#
DP36 CLKOUT_PCIE_P3 DW8 XTAL_38P4M_IN_CPU RH14 1 2 0_0201_5% XTAL_38P4M_IN RH572 20K_0201_5%
GPP_D8/SRCCLKREQ3# XTAL_IN XTAL_38P4M_OUT_CPU RH15 XTAL_38P4M_OUT 1
XTAL DU8 1 2 0_0201_5%
CJ2 XTAL_OUT
<70> CLK_PCIE_N4 CH46
CJ1 CLKOUT_PCIE_N4 1U_0201_6.3V6K
<70> CLK_PCIE_P4 CLKOUT_PCIE_P4 CLK_BIASREF 2
RH39 1 2 10K_0201_5% DN40 DU6 RH475 1 2 60.4_0201_1%
Card Reader---> +3VS GPP_H10/SRCCLKREQ4# XCLK_BIASREF
<70> CLKREQ_PCIE#4
10 of 19
PDG_An RC delay circuit with a t i me del ay i n t he
ICL-U_BGA1526
range of 18– 25 ms s houl d be pr ovi ded. The ci rcuit
@ should be connected to VCCRTC.
A A

P009 - ICL-U(4/13)SPI,SMB,ESPI
5 4 3 2 1
5 4 3 2 1
+3VS
RC222 2 1 49.9K_0201_1% UART_2_CRXD_DTXD

RC223 2 1 49.9K_0201_1% UART_2_CTXD_DRXD
RC655 2 1 49.9K_0201_1% UART_2_CRTS_DCTS
RC656 2 1 49.9K_0201_1% UART_2_CCTS_DRTS
RH713 1 @ 2 100K_0201_5% PCH_TBT_PERST#
NO REBOOT CPUNSSC CLOCK FREQ TOP SWAP OVERRIDE
+3V_PRIM
RC682 1 @ 2 10K_0201_5% MEDIACARD_IRQ# GPP_B23 (Internal 20 K Pull Down) GPP_B14 / SPKR (Internal 20 K Pull Down)
RH646 1 @ 2 100K_0201_5% PCH_TBT_PERST# GPP_B18/GSPI0_MOS (Internal 20 K Pull Down)
0 = 38.4 MHz clock (direct from crystal) (default) 0 = Disable "Top Swap" mode. (Default)
0 = REBOOT ENABLED
1 = 19.2 MHz clock (from internal divider) 1 = Enable "Top Swap" mode.
1 = NO REBOOT +3V_PRIM +3V_PRIM
+3VS
D D
NRB_BIT RH621 1 @ 2 4.7K_0201_5% GPP_B23 RH647 1 @ 2 4.7K_0201_5% SPKR RH667 1 @ 2 8.2K_0201_5%
RH300 1 2 10K_0201_5% PCH_TBT_PERST# +1.8VS

RH688 2 @ 1 100K_0201_5% HDA_BIT_CLK
ISH_I2C_1_SDA RC667 2 1 1K_0201_5%
ISH_I2C_1_SCL RC668 2 1 1K_0201_5%
+3VS
Check follow CRB 573129 UC1F
SSD_PWR_EN
<67> SSD_PWR_EN SML0B_SMBDATA
CH48 DV33 SML0B_SMBDATA <58>
RC339 1 @ 2 10K_0201_5% TPM_GPP_B17_SMI#_NMI NRB_BIT GPP_B16/GSPI0_CLK GPP_D13/ISH_UART0_RXD SML0B_SMBCLK
Strap Pin CF48 DW33
SML0B_SMBCLK <58> EC
RC338 1 @ 2 10K_0201_5% TPM_PIRQ# TPM_GPP_B17_SMI#_NMI CF47 GPP_B18/GSPI0_MOSI GPP_D14/ISH_UART0_TXD DT33
0_0201_5% 2 1 MEDIACARD_IRQ# CH49 GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS_N/GSPI2_CS1_N/IMGCLKOUT5 DU33 RC727 1 @ 2 0_0201_5% +3VS
<70> MEDIACARD_IRQ#_R SML0BALERT#
RH645 CH47 GPP_B15/GSPI0_CS0# GPP_D16/ISH_UART0_CTS_N/CNV_WCEN
TPM_GPP_B17_SMI#_NMI <56> SPKR GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1# SIO_EXT_WAKE#
RC254 1 @ 2 0_0201_5% UART DK22
<66> TPM_PIRQ#_R TPM_PIRQ# TPM_PIRQ# GPP_C12/UART1_RXD/ISH_UART1_RXD SIO_EXT_WAKE# <58> HOST_SD_WP#
RC255 1 2 0_0201_5% CL47 GSPI DW24 RC717 2 1 10K_0201_5%
Remove 0 ohm CK47 GPP_B20/GSPI1_CLK GPP_C13/UART1_TXD/ISH_UART1_TXD DV24
DBC_EN <38>
CK46 GPP_B22/GSPI1_MOSI GPP_C14/UART1_RTS#/ISH_UART1_RTS# DU24
<71> PCH_3.3V_TS_EN P_DET# GPP_B21/GSPI1_MISO GPP_C15/UART1_CTS#/ISH_UART1_CTS#
<39> P_DET# CH45
GPP_B23 GPP_B19/GSPI1_CS0#
Strap Pin CL48 CN43
GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1# GPP_B5/ISH_I2C0_SDA CN42
PCH_TBT_PERST# DP21 GPP_B6/ISH_I2C0_SCL
<46,48> PCH_TBT_PERST# GPP_C8/UART0_RXD ISH_I2C_1_SDA
DK21 CN41 +3V_PRIM
<79> SBIOS_TX
RH732 2 1 ENBKL_TS DL21 GPP_C9/UART0_TXD I2C / ISH GPP_B7/ISH_I2C1_SDA CL43 ISH_I2C_1_SCL ISH_I2C_1_SDA <39,63> ALS/G-sensor/P-sensor
+3VS For TS lid open request <6,38> PANEL_BKLEN
0_0201_5% P_SENSOR_PWR_SAVE# DJ22 GPP_C10/UART0_RTS# GPP_B8/ISH_I2C1_SCL ISH_I2C_1_SCL <39,63>
<39> P_SENSOR_PWR_SAVE# GPP_C11/UART0_CTS# SIO_EXT_WAKE#
CL41 RC671 2 1 10K_0201_5%
UART_2_CRXD_DTXD DT22 UART GPP_B9/I2C5_SDA/ISH_I2C2_SDA CJ39
P_SENSOR_PWR_SAVE# <79> UART_2_CRXD_DTXD UART_2_CTXD_DRXD GPP_C20/UART2_RXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL SML0B_SMBDATA
RC748 1 @ 2 10K_0201_5% DW22 DU36 RC672 2 1 1K_0201_5%
<79> UART_2_CTXD_DRXD UART_2_CRTS_DCTS GPP_C21/UART2_TXD GPP_D0/ISH_GP0 SML0B_SMBCLK
DV22 DV36 RC673 2 1 1K_0201_5%
P_DET# <79> UART_2_CRTS_DCTS UART_2_CCTS_DRTS GPP_C22/UART2_RTS# GPP_D1/ISH_GP1 ACC1_INT2#
RC749 1 2 10K_0201_5% DU22 DW36
<79> UART_2_CCTS_DRTS GPP_C23/UART2_CTS# GPP_D2/ISH_GP2 ACC1_INT2# <63>
DT36
DT24 ISH GPP_D3/ISH_GP3 DU34 P_INT#
TS
<38>
<38>
I2C_0_SDA
I2C_0_SCL
DT23
DW23
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_D17/ISH_GP4
GPP_D18/ISH_GP5
GPP_E15/ISH_GP6
DW34
DT14
DU14
P_INT# <39>
Check P_INT#
ACC1_INT2#
RC738
RC739
1
1
@
@
2 10K_0201_5%
2 10K_0201_5%
<63> I2C_1_SDA GPP_C18/I2C1_SDA GPP_E16/ISH_GP7 ALS_ALERT# <39>
DU23
TP <63> I2C_1_SCL GPP_C19/I2C1_SCL
C C
DU41 I2C ISH_GP2 for 2nd Accelerometer INT2#
DV41 GPP_H4/I2C2_SDA ISH_GP4 for P_INT#
GPP_H5/I2C2_SCL ISH_GP7 for ALS_ALERT#
DW41 +1.8VS
DT41 GPP_H6/I2C3_SDA
GPP_H7/I2C3_SCL
0_0201_5% 2 @ 1 RH714 GPP_H8 DT40 P_INT# RC741 2 1 10K_0201_5%
GPP_H9 DW40 GPP_H8/I2C4_SDA/CNV_MFUART2_RXD ACC1_INT2# RC742 2 1 10K_0201_5%
GPP_H9/I2C4_SCL/CNV_MFUART2_TXD 6 of 19
ICL-U_BGA1526
@
+3VS
DDR_CHA_EN RH738 1 @ 2 100K_0201_5%

DDR_CHB_EN RH739 1 @ 2 100K_0201_5%
DDR_CHA_EN RH740 1 @ 2 100K_0201_5%

DDR_CHB_EN RH741 1 @ 2 100K_0201_5%
+3VS
UC1G
CE46 SPK1_DET# RH745 1 2 100K_0201_5%
HDA_BIT_CLK GPP_G6/SD_CLK AUD_PWR_EN <71> SPK2_DET#
CY46 CC48 RH746 1 2 100K_0201_5%
HDA_SYNC GPP_R0/HDA_BCLK/I2S0_SCLK GPP_G1/SD_DATA0 SPK2_DET# <57>
CV49 CC49
HDA_SDOUT CY47 GPP_R1/HDA_SYNC/I2S0_SFRM GPP_G2/SD_DATA1 CC47 DDR_CHA_EN
HDA_SDIN0 CV45 GPP_R2/HDA_SDO/I2S0_TXD GPP_G3/SD_DATA2 CF45 DDR_CHB_EN
<56> HDA_SDIN0 GPP_R3/HDA_SDI0/I2S0_RXD GPP_G4/SD_DATA3 CNVI_EN#_R
DA47 CC45 RH729 1 2 0_0201_5%
GPP_R4/HDA_RST# GPP_G0/SD_CMD CNVI_EN# <52,71>
CF49
CAM_DET# need to reserve pull high <39>

0_0201_5%
CAM_DET#
@ RH715 GPP_A23
DP33
GPP_D19/I2S_MCLK
SD3.0 GPP_G7/SD_WP
GPP_G5/SD_CD#
CE47
SPK1_DET# <57>
HOST_SD_WP# <70>
2 1 DC45 DK38
GPP_R5 DA49 GPP_A23/I2S1_SCLK GPP_H0/CNV_BT_I2S_SDO DG38
DA45 GPP_R5/HDA_SDI1/I2S1_SFRM GPP_H1/SD_PWR_EN_N/CNV_BT_I2S_SDO
Reserved for debug DA48 GPP_R6/I2S1_TXD CJ43 SD3_RCOMP RC20 1 2 200_0201_1%
B GPP_R7/I2S1_RXD SD3_RCOMP B
CT49
CNV_RF_RESET# <52> CNV_RF_RESET#

CNV_RF_RESET# CT48 GPP_A7/I2S2_SCLK
GPP_A8/I2S2_SFRM/CNV_RF_RESET# WOV_DMIC_CLK0
Intel DMIC for WOV function
75K_0201_5% 2 1 RH114 CV47 DG36 RH705 1 @ 2 33_0201_5%
CLKREQ_CNV# <38> TS_RST# GPP_A10/I2S2_RXD GPP_S6/SNDW4_CLK/DMIC_CLK0 WOV_DMIC_DATA0 RH706 PCH_DMIC_CLK12 <39>
10K_0201_5% 2 @ 1 RH728 CT47 DG34 1 @ 2 33_0201_5%
<52> CLKREQ_CNV# GPP_A9/I2S2_TXD/MODEM_CLKREQ GPP_S7/SNDW4_DATA/DMIC_DATA0 PCH_DMIC_DATA12 <39>
SNDW_RCOMP 1
SPCE p.30 PU or PD 100K-180K CY39 CV38 RC16 1 2 200_0201_1%
PDG define only JFP need to PD 10K. CY38 GPP_S0/SNDW1_CLK SNDW_RCOMP CC654 @
GPP_S1/SNDW1_DATA 27P_0201_25V8
AUDIO 2
DB39
DD38 GPP_S2/SNDW2_CLK
GPP_S3/SNDW2_DATA
0_0201_5% 2 @ 1 RH716 GPP_S4 DF38
GPP_S5 DD39 GPP_S4/SNDW3_CLK/DMIC_CLK1
GPP_S5/SNDW3_DATA/DMIC_DATA1
Reserved for debug 7 of 19
ICL-U_BGA1526
@
HDA for AUDIO FLASH DESCRIPTOR SECURITY OVERRIDE RF Request. Place near CPU side
GPP_R2/HDA_SDO (Internal 20 K Pull Down)
RH113 1 2 33_0201_1% HDA_BIT_CLK
<56> HDA_BIT_CLK_R HDA_SYNC
<56> HDA_SYNC_R RH111 1 2 33_0201_1% 0 = ENABLE (DEFAULT)
RH112 1 2 33_0201_1% HDA_SDOUT @RF@
<56> HDA_SDOUT_R HDA_SDIN0 CC727 1 2 2.2P_0201_50V8B
56P_0201_25V8J
56P_0201_25V8J
22P_0201_50V8J
1 1 1 1 = DISABLE (ME can update)

CH50
CH51
CH40
2 2 2@
1 2 ME_FWP_PCH 1 2 HDA_SDOUT
<58> ME_FWP
RH218 0_0201_5% RH217 1K_0201_1%
@RF@ @RF@
A A

P010 - ICL-U(5/13)HDA,I2C,ISH
5 4 3 2 1
5 4 3 2 1
3V SELECT STRAP STRAP FOR SPI 1.8V/3.3V SEL

INTRUDER#
INPUT3VSEL
0 = SPI voltage is 3.3V
0 = 3.3V +/-5%
1 = SPI voltage is 1.8V
1 =3.0V +/-5% +3VALW_DSW
+RTCVCC
1M_0201_1% 2 @ 1 RH64
follow 574200-icl-mow-ww44-2018
INTRUDER#
RH301 1 @ 2 4.7K_0201_5% 1M_0201_1% 2 1 RH671
0.1U_0201_10V6K 2 1 CC653
D INPUT3VSEL RH298 1 2 100K_0201_5% @ D
UC1K +3V_PRIM
SIO_SLP_SUS# DM49 CY42 SIO_PWRBTN#_R RH57 1 2 0_0201_5%

<16,47,49,58> SIO_SLP_SUS# SIO_SLP_S5# SLP_SUS# GPD3/PWRBTN# AC_PRESENT_R AC_PRESENT SIO_PWRBTN# <58,79> PCH_RSMRST#_AND
DF45 DE46 RH312 1 2 0_0201_5% RH592 1 @ 2 10K_0201_5%
Microchip suggest 100K on RH575 <79> SIO_SLP_S5#
<58,78,79> SIO_SLP_S4#
SIO_SLP_S4# DC48 GPD10/SLP_S5# GPD1/ACPRESENT DH48 PCH_BATLOW# AC_PRESENT <58> TBT_I2C_INT# RC687 1 2 10K_0201_5%
SIO_SLP_S3# DF47 GPD5/SLP_S4# GPD0/BATLOW#
<58,78,79> SIO_SLP_S3# SIO_SLP_A# GPD4/SLP_S3# TBT_I2C_INT# PCH_RSMRST#_AND
DH47 CL39 TBT_I2C_INT# <42,44,46,48> RH591 1 2 100K_0201_5%
PCH_DPWROK <79> SIO_SLP_A# SIO_SLP_S0# GPD6/SLP_A# GPP_B11/PMCALERT# CPU_C10_GATE#_R
2 1 CL45 DU40 RH280 1 2 0_0201_5%
<66,79> SIO_SLP_S0# GPP_B12/SLP_S0# GPP_H18/CPU_C10_GATE# CPU_C10_GATE# <78>
1M_0201_1% RH575 DG40
2 1 SIO_SLP_WLAN# DE49 GPP_H3/SX_EXIT_HOLDOFF_N/CNV_BT_I2S_SDO
<71> SIO_SLP_WLAN# GPD9/SPL_WLAN#
0.01U_0402_16V7K @ CH48 DN48 DL45 WAKE# RH207 1 2 0_0201_5%
SLP_LAN# WAKE# PCH_PCIE_WAKE# <58>
PCH_RSMRST#_AND DG49 DE47 LAN_WAKE#_R RH600 1 2 0_0201_5% LAN_WAKE#
<63,78> PCH_RSMRST#_AND SYS_RESET# RSMRST# GPD2/LAN_WAKE# LAN_WAKE# <58>
DK19 DF48 +3VALW_DSW
<79> SYS_RESET# PCH_PLTRST# SYS_RESET# GPD11/LANPHYPC/DSWLDO_MON
CM49
GPP_B13/PLTRST# CE4 VCCST_OVERRIDE
VCCST_OVERRIDE CF2 VCCST_PWRGD_CPU RH587 1 2 60.4_0201_1% VCCST_PWRGD LAN_WAKE# RH601 1 2 10K_0201_5%
PCH_DPWROK VCCST_PWRGD VCCSTPWRGOOD_TCSS VCCST_PWRGD <78> PCH_BATLOW#
DR48 CE3 RH460 1 2 100K_0201_5%
<58> PCH_DPWROK PCH_PWROK DSW_PWROK VCCSTPWRGOOD_TCSS AC_PRESENT RH297
DN47 CF1 CPUPWRGD 1 2 10K_0201_5%
SYS_PWROK 0_0201_5% 2 1 RH594 SYS_PWROK_R DP19 PCH_PWROK PROCPWRGD PCH_PCIE_WAKE# RH653 1 2 1K_0201_5%
<58,79> SYS_PWROK SYS_PWROK DC47 GPD7 1
GPD7 TP101
INPUT3VSEL DN49 PAD~D TP@
INTRUDER# Strap PinDR47 INPUT3VSEL
INTRUDER#
+3VS
11 of 19
ICL-U_BGA1526
2
@
RH733
100K_0201_5%
1
C C
RH625 1 2 0_0201_5%
if pop UC29, RC244 also need pop
RC430 1 2 0_0201_5% +3VS +3VS
VCCST_OVERRIDE_R 0_0201_5% 2 1 RH584 VCCST_OVERRIDE UH6 @

<78> VCCST_OVERRIDE_R
5
0_0201_5% 2 1 RH586 VCCSTPWRGOOD_TCSS +3VS
CC77 @ RC244 @ 1
P
<79> MIPI60_DBRESET#_R <91> PCH_PWROK_P B PCH_PWROK
2 1 10K_0201_5% EMI@ 4
1K_0201_5% 2 @ 1 RC647 VCCST_PWRGD VCCST_PWRGD O
UC29 @ CC649 1 2 100P_0201_50V8J <78> IMVP_VR_ON_P 2 MC74VHC1G08DFT2G_SC70-5
G
1K_0201_5% 2 MIPI60@ 1 RC247 PCH_RSMRST#_AND A
<79> PM_RSMRST_PWRGD_MIPI60
1
+3VS 0.1U_0201_10V6K EMI@
PLACE 1K SERIES RESISTOR NEAR RSMRST_N AND VCCST_PWRGD 1
3
“ T” JUNCTION POINT, NOT NEAR MIPI60 B 4 SYS_RESET#_R 2 1 SYS_RESET# CC650 1 2 100P_0201_50V8J
CPUPWRGD
RC433 1 @ 2 8.2K_0201_5% ME_RESET# 2 O RC432 1K_0201_5%
G
A @EMI@
RC434 1 @ 2 8.2K_0201_5% MC74VHC1G08DFT2G_SC70-5 SYS_RESET# CC651 1 2 0.1U_0201_10V6K
3
+1.05V_VCCST
RH95 2 1 1K_0201_1% H_THERMTRIP# +3V_PRIM

ESD Request:place near CPU side
RH80 2 1 49.9_0201_1% H_CATERR#
2
RH588 2 1 1K_0201_5% VCCST_PWRGD UC1D +3V_PRIM CC652
PLACE 'RA' CLOSE TO MCP - WITHIN 1.5 INCH CRB P.35 0.1U_0201_10V6K
H_CATERR# J4 P3 MIPI60_CPU_JTAG_TCLK 1
MIPI60_CPU_JTAG_TCLK <79>
5
+1.05V_VCCSTG PECI_EC CD5 CATERR# PROC_TCK K5 MIPI60_CPU_JTAG_TDI
<58> PECI_EC MIPI60_CPU_JTAG_TDI <79> UH1
H_PROCHOT# RC614 1 2 499_0201_1% H_PROCHOT#_R C3 PECI PROC_TDI K3 MIPI60_CPU_JTAG_TDO PCH_PLTRST# 1
P
<16,58,86,91> H_PROCHOT# H_THERMTRIP# PROCHOT# PROC_TDO MIPI60_CPU_JTAG_TMS MIPI60_CPU_JTAG_TDO <79> B
<58> H_THERMTRIP# E3 P4 4
H_PROCHOT# THRMTRIP# PROC_TMS MIPI60_CPU_JTAG_TMS <79> O PCH_PLTRST#_EC <46,48,52,66,67,70,79>
RH96 2 1 1K_0201_5% N1 2
MIPI60_CPU_JTAG_TRST# <79>
G
PROC_TRST# A
1
RH4 2 1 49.9_0201_1% CPU_POPI_RCOMP CJ41
RH5 2 1 49.9_0201_1% PCH_OPI_RCOMP DU3 PROC_POPIRCOMP N5 MIPI60_PCH_JTAG_TRST# RH46
MC74VHC1G08DFT2G_SC70-5
MIPI60_PCH_JTAG_TRST# <79>
3
RH6 2 @ 1 49.9_0201_1% EDRAM_OPIO_RCOMP A14 PCH_OPIRCOMP JTAG PCH_TRST# R5 MIPI60_PCH_JTAG_TCLK
+3VS RH7 @ CPU_EOPIO_RCOMP RSVD_25 PCH_TCK MIPI60_PCH_JTAG_TDI MIPI60_PCH_JTAG_TCLK <79>
2 1 49.9_0201_1% B14 K1 100K_0201_5%
RSVD_26 PCH_TDI MIPI60_PCH_JTAG_TDO MIPI60_PCH_JTAG_TDI <79>
K2
MIPI60_PCH_JTAG_TDO <79>
2
PCH_TDO MIPI60_PCH_JTAG_TMS
<79> DBG_PMODE Strap PinDL15 N3
MIPI60_PCH_JTAG_TMS <79>
RH631 1 2 10K_0201_5% PCH_TOUCHPAD_INTR# DBG_PMODE PCH_TMS N2 MIPI60_PCH_JTAGX
MEM_INTERLEAVED PCH_JTAGX MIPI60_PCH_JTAGX <79>
DV11
TOUCH_SCREEN_PD# DT11 GPP_E3/CPU_GP0 P6
+3V_PRIM PCH_TOUCHPAD_INTR# GPP_E7/CPU_GP1 PROC_PRDY# MIPI60_PRDY# <79> +1.05V_VCCSTG
CR38 M6
<63> PCH_TOUCHPAD_INTR# GPP_B3/CPU_GP2 PROC_PREQ# MIPI60_PREQ# <79>
CR39
GPP_B4/CPU_GP3
RH709 1 2 100K_0201_5% SIO_SLP_S0# GPP_E6 Strap PinDT12 PLACE WITHIN 1.1INCH OF MCP
GPP_H2 GPP_E6 MIPI60_PCH_JTAG_TDI RC151 1 MIPI60@ 2 51_0201_5%
B Strap PinDJ38 B
DL38 GPP_H2/CNV_BT_I2S_SDO MIPI60_PCH_JTAG_TMS RC203 1 MIPI60@ 2 51_0201_5%
GPP_H19/TIME_SYNC04 of 19 MIPI60_PCH_JTAG_TDO RC202 1 2 100_0201_5%
ICL-U_BGA1526 TDI&TMS KEEP STUB TO MINIMUM
+3VS @ MIPI60_CPU_JTAG_TDI RC146 1 @ 2 51_0201_5%
MIPI60_CPU_JTAG_TMS RC181 1 @ 2 51_0201_5%
MIPI60_CPU_JTAG_TDO RC150 1 2 100_0201_5%
2
TDO PLACE WITHIN 1.1INCH OF SOC

RH655 @
100K_0201_5%
PLACE WITHIN 1.1INCH OF SOC
PCH GLITCH ISSUE MITIGATION(PDG p.306) EMI request,Place near CPU side. MIPI60_CPU_JTAG_TCLK RC145 1 2 51_0201_5%
1
MIPI60_PCH_JTAG_TCLK RC180 1 @ 2 51_0201_5%

@ D468 RH683 1 2 100K_0201_5% SIO_SLP_S3# MIPI60_PCH_JTAG_TRST# RC201 1 @ 2 51_0201_5%
2 1 TOUCH_SCREEN_PD# MIPI60_PCH_JTAGX RC344 1 @ 2 51_0201_5%
<38> TOUCH_SCREEN_PD#_R
CH53 1 @ 2 0.33U_0201_6.3V6M @EMI@
RB751S40T1G_SOD523-2 MIPI60_PCH_JTAG_TDO CC735 1 2 0.1U_0201_25V6K
RH684 1 2 100K_0201_5% SIO_SLP_S4#
0_0201_5% 2 @ 1 RH654 @EMI@
CH54 1 @ 2 0.33U_0201_6.3V6M MIPI60_PCH_JTAG_TDI CC736 1 2 0.1U_0201_25V6K
@ RH743 RH685 1 2 100K_0201_5% SIO_SLP_A# @EMI@

2 1 MIPI60_PCH_JTAGX CC737 1 2 0.1U_0201_25V6K
LID_CL_TS_FP# <58,77>
CH55 1 @ 2 0.33U_0201_6.3V6M
0_0201_5% @EMI@
RH682 1 2 100K_0201_5% SIO_SLP_WLAN# H_THERMTRIP# CC738 1 2 0.1U_0201_25V6K
CH52 1 @ 2 0.33U_0201_6.3V6M @EMI@

H_PROCHOT#_R CC739 1 2 0.1U_0201_25V6K
+3VALW RH686 1 2 100K_0201_5% SIO_SLP_SUS#
CH56 1 @ 2 0.33U_0201_6.3V6M JTAG ODT DISABLE MAF/SAF STRAP(eSPI Flash Sharing Mode) +3V_PRIM
2
RC147 RH629 1 @ 2 10K_0201_5%

100K_0201_5% RH689 1 @ 2 100K_0201_5% SIO_SLP_S0#
MEM_INTERLEAVED RH630 1 @ 2 10K_0201_5%
GPP_E6 GPP_H2/CNV_BT_I2S_SDI(INTERNAL PD 20K)
1
RH690 1 @ 2 100K_0201_5% PCH_PLTRST#

0 = JTAG ODT DISABLED 0 = MAF (Master Attached Flash)
3
D2 D1 RH691 1 @ 2 100K_0201_5% SIO_SLP_S5#

1 = JTAG ODT ENABLED 1 = SAF (Slave Attached Flash)
DIMM TYPE
A 5 2 CH57 1 @ 2 0.33U_0201_6.3V6M +3V_PRIM +3V_PRIM A
G2 G1
DISPOFF_R#
RH660 1 2 100K_0201_5% RH618 1 @ 2 2.2K_0201_5% HIGH Interleave

PMDXB600UNE_DFN1010B-6
QC2A
S2 S1
GPP_E6 RH661 1 @ 2 4.7K_0201_5% GPP_H2 RH617 1 @ 2 20K_0201_5%
LOW Non-Interleave
4
1
QC2B
EVT2_33
2
RH744
0_0201_5%
1
DISPOFF# <38> Security Classification Compal Secret Data Compal Electronics, Inc.
P011 - ICL-U(6/13)GPIO
Date: Tuesday, January 29, 2019 Sheet 11 of 100
5 4 3 2 1
5 4 3 2 1
UC1H
D D
CV7 DJ8
CV6 PCIE7_RXN PCIE1_RXN/USB31_1_RXN DJ6
PCIE7_RXP PCIE1_RXP/USB31_1_RXP
DD3 DJ2
PCIE7_TXN PCIE1_TXN/USB31_1_TXN
DD5 DJ1
PCIE7_TXP PCIE1_TXP/USB31_1_TXP
CT6 DG9 USB3_CRX_DTX_N2 <79>
CT7 PCIE8_RXN PCIE2_RXN/USB31_2_RXN DG7
DA3
DA5
PCIE8_RXP
PCIE8_TXN
PCIE2_RXP/USB31_2_RXP
PCIE2_TXN/USB31_2_TXN
DJ3
DJ5
USB3_CRX_DTX_P2
USB3_CTX_DRX_N2
<79>
<79> USB debug
PCIE8_TXP PCIE2_TXP/USB31_2_TXP USB3_CTX_DRX_P2 <79>
CP7 PCIe DE7

<67> PCIE_CRX_DTX_N9 PCIE9_RXN PCIE3_RXN/USB31_3_RXN PCIE_CRX_DTX_N3 <52>
CP6 DE9
<67>
<67>
PCIE_CRX_DTX_P9
PCIE_CTX_DRX_N9 DA2
DA1
PCIE9_RXP
PCIE9_TXN
PCIE3_TXN/USB31_3_TXN
DF3
DF5
PCIE_CRX_DTX_P3
PCIE_CTX_DRX_N3
<52>
<52> WLAN
<67> PCIE_CTX_DRX_P9 PCIE9_TXP PCIE3_TXP/USB31_3_TXP PCIE_CTX_DRX_P3 <52>
CM7 PCIe / USB3.1 DC7

<67> PCIE_CRX_DTX_N10 PCIE10_RXN PCIE4_RXN/USB31_4_RXN
<67> PCIE_CRX_DTX_P10 CM6 DC9
PCIE10_RXP PCIE4_RXP/USB31_4_RXP
<67> PCIE_CTX_DRX_N10 CY3 DF2
PCIE10_TXN PCIE4_TXN/USB31_4_TXN
CY4 DF1
PCIe SSDX4 <67> PCIE_CTX_DRX_P10
CK7
PCIE10_TXP PCIE4_TXP/USB31_4_TXP
DA6
<67> PCIE_CRX_DTX_N11
PCIe Gen3 <67>
<67>
PCIE_CRX_DTX_P11
PCIE_CTX_DRX_N11
CK6
CW2
PCIE11_RXN/SATA0_RXN
PCIE11_RXP/SATA0_RXP
PCIE5_RXN/USB31_5_RXN
DA7
DE4
CW1 PCIE11_TXN/SATA0_TXN PCIE5_TXN/USB31_5_TXN DE3
<67> PCIE_CTX_DRX_P11 PCIE11_TXP/SATA0_TXP PCIE5_TXP/USB31_5_TXP
<67> PCIE_CRX_DTX_N12 CJ6
PCIE12_RXN/SATA1A_RXN PCIe / SATA CY7
PCIE6_RXN/USB31_6_RXN
<67> PCIE_CRX_DTX_P12 CJ7 CY6
PCIE12_RXP/SATA1A_RXP PCIE6_RXP/USB31_6_RXP
C
<67> PCIE_CTX_DRX_N12 CW5 DD1 C
PCIE12_TXN/SATA1A_TXN PCIE6_TXN/USB31_6_TXN
DD2
PCIE6_TXP/USB31_6_TXP
<67> PCIE_CTX_DRX_P12 CW3
CG7 PCIE12_TXP/SATA1A_TXP DN8
CG6
CT3
PCIE13_RXN
PCIE13_RXP
USB2N_1
USB2P_1
DP8
USB20_N1
USB20_P1
<79>
<79> USB debug
CT5 PCIE13_TXN DK11
PCIE13_TXP USB2N_2
DJ11
PCIe USB2P_2
CE6
CE7 PCIE14_RXN DP13
PCIE14_RXP USB2N_3
CT2 DN13
PCIE14_TXN USB2P_3
CT1
PCIE14_TXP DK10
CC5
CC6 PCIE15_RXN/SATA1B_RXN
USB2N_4
USB2P_4
DJ10
USB20_N4
USB20_P4
<50>
<50> Type-C_R
PCIE15_RXP/SATA1B_RXP
CR3 DL5
CR4
PCIE15_TXN/SATA1B_TXN
PCIE15_TXP/SATA1B_TXP PCIe / SATA
USB2N_5
USB2P_5
DL3
USB20_N5
USB20_P5
<77>
<77> FPR
CA6 DP11
CardreaderX1 <70>
<70>
PCIE_CRX_DTX_N16
PCIE_CRX_DTX_P16 CA5
CP1
PCIE16_RXN/SATA2_RXN
PCIE16_RXP/SATA2_RXP USB2.0
USB2N_6
USB2P_6
DN11
<70> PCIE_CTX_DRX_N16
PCIe Gen2 <70> PCIE_CTX_DRX_P16 CP2
PCIE16_TXN/SATA2_TXN
PCIE16_TXP/SATA2_TXP USB2N_7
DK13
DJ13
USB2P_7
DW12
CR42 GPP_E0/SATAXPCIE0/SATAGP0 DN6
+3V_PRIM
Check <67> SSD_IFDET
CR43 GPP_A12/SATAXPCIE1/SATAGP1
GPP_A13/SATAXPCIE2/SATAGP2
USB2N_8
USB2P_8
DP6
USB20_N8
USB20_P8
<50>
<50> Type-C_L
USB_OC0# DW14 DL2
B 10K_0201_5% 2 @ 1 RH604 USB_OC0#

USB_OC3# CT43
GPP_E9/USB_OC0#
GPP_A16/USB_OC3#
USB2N_9
USB2P_9
DL1
USB20_N9
USB20_P9
<39>
<39> UF Camera B
10K_0201_5% 2 @ 1 RH605 USB_OC3# DU12 DP10
<71> SD_PWR_EN
DU11
GPP_E4/DEVSLP0 USB2N_10
DN10
USB20_N10 <52>
BT
Check <67> SSD_DEVSLP
CV48
GPP_E5/DEVSLP1
GPP_A11/SATA_DEVSLP2
USB2P_10
USB_ID
DL6 USB2_ID RH8
USB20_P10
1
<52>
2 10K_0201_5%
DT38
GPP_H12/M2_SKT2_CFG0 USB2_VBUSSENSE RH9
DW38 DL11 1 2 10K_0201_5%
GPP_H13/M2_SKT2_CFG1 USB_VBUSSENSE
DV38
DU38 GPP_H14/M2_SKT2_CFG2 DN5 USB2_COMP RH10 1 2 113_0201_1%
GPP_H15/M2_SKT2_CFG3 USB2_COMP
100_0201_1% 2 1 RH1 PCIE_RCOMPN DN1 CD3
PCIE_RCOMPP PCIE_RCOMPN RSVD_81
DN3
PCIE_RCOMPP
8 of 19
ICL-U_BGA1526
@
A A

P012 - ICL-U(7/13)PCIE,USB
5 4 3 2 1
5 4 3 2 1
UC1I
D12 DP27 MEM_CONFIG0

C12 CSI_E_CLK_N GPP_F8/EMMC_DATA0 DU30 MEM_CONFIG1
B12 CSI_E_CLK_P GPP_F9/EMMC_DATA1 DT30 MEM_CONFIG2
A12 CSI_E_DN_0 GPP_F10/EMMC_DATA2 DT29 MEM_CONFIG3
G13 CSI_E_DP_0 GPP_F11/EMMC_DATA3 DV30 MEM_CONFIG4
F13 CSI_E_DN_1 GPP_F12/EMMC_DATA4 DU29
CSI_E_DP_1 GPP_F13/EMMC_DATA5 DW30
K10 eMMC GPP_F14/EMMC_DATA6 DW29
L10 CSI_F_CLK_N GPP_F15/EMMC_DATA7 DV28
L8 CSI_F_CLK_P GPP_F7/EMMC_CMD DW28
M8 CSI_F_DN_0 GPP_F16/EMMC_RCLK DN27
M11 CSI_F_DP_0 GPP_F17/EMMC_CLK DT28
L11 CSI_F_DN_1 GPP_F18/EMMC_RESET# DU28 EMMC_RCOMP RC17 1 2 200_0201_1%
CSI_F_DP_1 EMMC_RCOMP
D D9 D
C9 CSI_D_CLK_N DV45
CSI_D_CLK_P CNV_WT_D0N CNV_CTX_DRX_N0 <52>
A7 DU45
CSI_D_DN_0 CNV_WT_D0P CNV_CTX_DRX_P0 <52>
B7 DU44
CSI_D_DP_0 CNV_WT_D1N CNV_CTX_DRX_N1 <52>
B9 DT44
CSI_D_DN_1 CNV_WT_D1P CNV_CTX_DRX_P1 <52>
A9 DL42
CSI_D_DP_1 CNV_WT_CLKN CLK_CNV_CTX_DRX_N <52>
D7 DK42
CSI_D_DN_2/CSI_C_DN_0 CNV_WT_CLKP CLK_CNV_CTX_DRX_P <52>
C7
D8
C8
CSI_D_DP_2/CSI_C_DP_0
CSI_D_DN_3/CSI_C_CLK_N CSI2 CNV_WR_D0N
DP44
DN44
CNV_CRX_DTX_N0 <52> CNVi
CSI_D_DP_3/CSI_C_CLK_P CNV_WR_D0P CNV_CRX_DTX_P0 <52>
DG42 CNV_CRX_DTX_N1 <52>
G11 CNV_WR_D1N DG44
CSI_H_CLK_N CNV_WR_D1P CNV_CRX_DTX_P1 <52>
J11 DK44 CLK_CNV_CRX_DTX_N <52>
F6 CSI_H_CLK_P CNVi CNV_WR_CLKN DJ44
CSI_H_DN_0 CNV_WR_CLKP CLK_CNV_CRX_DTX_P <52>
G6
G10 CSI_H_DP_0 DT45 CNV_WT_RCOMP RC15 1 2 150_0201_1%
F10 CSI_H_DN_1 CNV_WT_RCOMP
G8 CSI_H_DP_1 DL29 CNV_BRI_CRX_DTX
CSI_H_DN_2/CSI_G_DN_0 GPP_F1/CNV_BRI_RSP/UART0_RXD CNV_RGI_CTX_DRX CNV_BRI_CRX_DTX <52>
J8 DP31Strap Pin RC503 1 2 22_0201_1%
CSI_H_DP_2/CSI_G_DP_0 GPP_F2/CNV_RGI_DT/UART0_TXD CNV_BRI_CTX_DRX CNV_RGI_CTX_R_DRX <52>
K6 DL31 Strap Pin RC504 1 2 22_0201_1%
CSI_H_DN_3/CSI_G_CLK_N GPP_F0/CNV_BRI_DT/UART0_RTS# CNV_RGI_CRX_DTX CNV_BRI_CTX_R_DRX <52>
L6 DN29 CNV_RGI_CRX_DTX <52>
CSI_H_DP_3/CSI_G_CLK_P GPP_F3/CNV_RGI_RSP/UART0_CTS#
100_0201_1% 2 1 RC8 CSI_RCOMP B4 DJ29 GPP_F4 2 @ 1
CSI_RCOMP GPP_F4/CNV_RF_RESET# DP29 0_0201_5% RC746
Memory Type Configuration Strap pin
DT34 GPP_F6/CNV_PA_BLANKING DL27
<42,44,46,48> RT_FORCE_PWR GPP_D4/IMGCLKOUT0 GPP_F19/A4WP_PRESENT GPP_F5 +1.8V_PRIM
DP38 DK29
DK36 GPP_H20/IMGCLKOUT1 GPP_F5/MODEM_CLKREQ
DL36 GPP_H21/IMGCLKOUT2 RH612 1 @ 2 10K_0201_5% MEM_CONFIG0 RH129 1 @ 2 10K_0201_5%
DN38 GPP_H22/IMGCLKOUT3
GPP_H23/IMGCLKOUT4 RH613 1 @ 2 10K_0201_5% MEM_CONFIG1 RH139 1 @ 2 10K_0201_5%
+1.8V_PRIM
RH614 1 @ 2 10K_0201_5% MEM_CONFIG2 RH145 1 @ 2 10K_0201_5%
9 of 19
ICL-U_BGA1526 RH615 1 @ 2 10K_0201_5% MEM_CONFIG3 RH185 1 @ 2 10K_0201_5%
@ CNV_BRI_CRX_DTX RH724 1 @ 2 20K_0201_5%
CNV_RGI_CRX_DTX RH725 1 @ 2 20K_0201_5% RH616 1 @ 2 10K_0201_5% MEM_CONFIG4 RH665 1 @ 2 10K_0201_5%
Pin Name Micron 8GB Micron 16GB Micron 32GB Hynix 8GB Hynix 16GB Hynix 32GB Samsung 8GB Samsung 16GB Samsung 32GB Samsung 16GB Hynix 16GB Samsung 4GB Micron 4GB Hynix 4GB
SA0000BX50L SA0000BX60L SA0000BX70L SA0000BYX0L SA0000AW20L SA0000C7V0L SA0000C6K0L SA0000AU40L SA0000C6L0L SA0000BYW0L SA0000AV70L SA0000BWF0L SA0000AD10L
C
OLD and NO SUPPORT OLD and NO SUPPORT TBD NEW NEW C
MEM_CONFIG0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
MEM_CONFIG1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
MEM_CONFIG2 0 0 0 0 1 1 1 1 0 0 0 0 1 1
MEM_CONFIG3 0 0 0 0 0 0 0 0 1 1 1 1 1 1
MEM_CONFIG4 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DRAM Option R1 DRAM Config Option

X76 (Resistor pop location)
MEM_CONFIG4 MEM_CONFIG3 MEM_CONFIG2 MEM_CONFIG1 MEM_CONFIG0
Micron 4GB/3733
X7678131L06 X76_M4GB_R1@ X76_M4GB_R1@ X76_M4GB_R1@ X76_M4GB_R1@ X76_M4GB@ X76_M4GB@ X76_M4GB@ X76_M4GB@ X76_M4GB@
UD1 UD2 UD3 UD4 RH665 RH615 RH614 RH139 RH129
MT53B256M32D1NP-053 WT MT53B256M32D1NP-053 WT MT53B256M32D1NP-053 WT MT53B256M32D1NP-053 WT 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
SA0000BWF0L SA0000BWF0L SA0000BWF0L SA0000BWF0L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Micron 8GB/4266
MT53E512M32D2NP-046 WT MT53E512M32D2NP-046 WT MT53E512M32D2NP-046 WT MT53E512M32D2NP-046 WT 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
SA0000BX50L SA0000BX50L SA0000BX50L SA0000BX50L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Micron 16GB/4266
MT53E1G32D4NQ-046 WT MT53E1G32D4NQ-046 WT MT53E1G32D4NQ-046 WT MT53E1G32D4NQ-046 WT 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
SA0000BX60L SA0000BX60L SA0000BX60L SA0000BX60L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Micron 32GB/4266 X76_M32GB@ X76_M32GB@ X76_M32GB@ X76_M32GB@ X76_M32GB@

X76_M32GB_R1@ X76_M32GB_R1@ X76_M32GB_R1@ X76_M32GB_R1@ RH665 RH185 RH145 RH613 RH129
X7678131L11 UD1 UD2 UD3 UD4 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
MT53E2G32D8QD-046 WT MT53E2G32D8QD-046 WT MT53E2G32D8QD-046 WT MT53E2G32D8QD-046 WT SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
B SA0000BX70L SA0000BX70L SA0000BX70L SA0000BX70L B
Hynix 4GB/3733
X76_H4GB_R1@ X76_H4GB_R1@ X76_H4GB_R1@ X76_H4GB_R1@ X76_H4GB@ X76_H4GB@ X76_H4GB@ X76_H4GB@ X76_H4GB@
X7678131L07
H9HCNNN8KUMLHR-NME H9HCNNN8KUMLHR-NME H9HCNNN8KUMLHR-NME H9HCNNN8KUMLHR-NME 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
SA0000AD10L SA0000AD10L SA0000AD10L SA0000AD10L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Hynix 8GB/4266
X7678131L05 X76_H8GB_R1@ X76_H8GB_R1@ X76_H8GB_R1@ X76_H8GB_R1@ X76_H8GB@ X76_H8GB@ X76_H8GB@ X76_H8GB@ X76_H8GB@
H9HCNNNBKMALHR-NEE H9HCNNNBKMALHR-NEE H9HCNNNBKMALHR-NEE H9HCNNNBKMALHR-NEE 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
SA0000BYX0L SA0000BYX0L SA0000BYX0L SA0000BYX0L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Hynix 16GB/4266(NEW)
H9HCNNNCPMALHR-NEE H9HCNNNCPMALHR-NEE H9HCNNNCPMALHR-NEE H9HCNNNCPMALHR-NEE 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
SA0000BYW0L SA0000BYW0L SA0000BYW0L SA0000BYW0L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Hynix 32GB/3733
H9HCNNNFAMALTR-NME H9HCNNNFAMALTR-NME H9HCNNNFAMALTR-NME H9HCNNNFAMALTR-NME 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
SA0000C7V0L SA0000C7V0L SA0000C7V0L SA0000C7V0L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Samsung 4GB/3733
X7678131L04 X76_S4GB_R1@ X76_S4GB_R1@ X76_S4GB_R1@ X76_S4GB_R1@ X76_S4GB@ X76_S4GB@ X76_S4GB@ X76_S4GB@ X76_S4GB@
K4F8E304HB-MGCJ K4F8E304HB-MGCJ K4F8E304HB-MGCJ K4F8E304HB-MGCJ 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
SA0000AV70L SA0000AV70L SA0000AV70L SA0000AV70L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Samsung 8GB/4266
K4U6E3S4AA-MGCL K4U6E3S4AA-MGCL K4U6E3S4AA-MGCL K4U6E3S4AA-MGCL 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
SA0000C6K0L SA0000C6K0L SA0000C6K0L SA0000C6K0L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Samsung 16GB/4266(NEW)
K4UBE3D4AA-MGCL K4UBE3D4AA-MGCL K4UBE3D4AA-MGCL K4UBE3D4AA-MGCL 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
A SA0000C6L0L SA0000C6L0L SA0000C6L0L SA0000C6L0L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280 A
Samsung 32GB/4266
K4UCE3Q4AA-MGCL K4UCE3Q4AA-MGCL K4UCE3Q4AA-MGCL K4UCE3Q4AA-MGCL 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
SA0000CGN0L SA0000CGN0L SA0000CGN0L SA0000CGN0L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280

P013 - ICL-U(8/13)CSI,CNVi,EMMC
5 4 3 2 1
5 4 3 2 1
D D
+VCCIN 1.The total Length of Data and Clock (from CPU to each VR) must be equal (± 0. 1 i nch).
2.Route the Alert signal between the Clock and the Data signals.
CAD Note: Place the PU resistors close to CPU
Max2V/70A(Processor EDS 572795 rev 1.32)
UC1L +1.05V_VCCST
A19 CPU POWER 1 OF 3 CJ35

VCCIN_1 VCCIN_52
AC12 CK10
VCCIN_2 VCCIN_53
1
V13 J32
W12
VCCIN_3
VCCIN_4
VCCIN_54
VCCIN_55
CL34 SVID DATA RC604
Y13 CL35 100_0201_1%
K29 VCCIN_5 VCCIN_56 CN34
VCCIN_6 VCCIN_57
K31 CN35
2
B19 VCCIN_7 VCCIN_58 CP33
B23 VCCIN_8 VCCIN_59 CR34
B27 VCCIN_9 VCCIN_60 A29 SOC_SVID_DAT 2 1
VCCIN_10 VCCIN_61 SVID_DAT <91>
B29 CR35 0_0201_5% RC603
VCCIN_11 VCCIN_62
BN10 CT33
VCCIN_12 VCCIN_63
C BP11 CT34 C
VCCIN_13 VCCIN_64
BP9 CT35
VCCIN_14 VCCIN_65
BR10 CU33
BT11 VCCIN_15 VCCIN_66 D19 +1.05V_VCCST
VCCIN_16 VCCIN_67
A21 D21
BT9 VCCIN_17 VCCIN_68 D23
BU10 VCCIN_18 VCCIN_69 D24
VCCIN_19 VCCIN_70
1
BV36 D27
BV9
VCCIN_20
VCCIN_21
VCCIN_71
VCCIN_72
AA12 SVID ALERT# RC602
BW10 D29 56_0201_5%
VCCIN_22 VCCIN_73
BW36 F19
VCCIN_23 VCCIN_74
BW9 F21
2
BY10 VCCIN_24 VCCIN_75 F23
VCCIN_25 VCCIN_76
C19 F24
C23 VCCIN_26 VCCIN_77 F27 SOC_SVID_ALERT# 2 1
VCCIN_27 VCCIN_78 SVID_ALERT# <91>
A23 F29 0_0201_5% RC601
VCCIN_28 VCCIN_79
C27 G1
C29 VCCIN_29 VCCIN_80 G19
VCCIN_30 VCCIN_81
CA36 G23
CA9 VCCIN_31 VCCIN_82 AB1
VCCIN_32 VCCIN_83 +1.05V_VCCST
CB10 G27
VCCIN_33 VCCIN_84
CC11 G29
VCCIN_34 VCCIN_85
CC36 H19
VCCIN_35 VCCIN_86
CC9 H23
VCCIN_36 VCCIN_87
1
CD10 H27
CE11 VCCIN_37
VCCIN_38
VCCIN_88
VCCIN_89
H29 SVID CLK
A24 J18 RC606 @
VCCIN_39 VCCIN_90 100_0201_5%
CE34 J20
VCCIN_40 VCCIN_91
CE35 J22
2
B CF10 VCCIN_41 VCCIN_92 J23 B
CF33 VCCIN_42 VCCIN_93 AB13
VCCIN_43 VCCIN_94 SOC_SVID_CLK
CG11 J26 2 1 SVID_CLK <91>
VCCIN_44 VCCIN_95 0_0201_5% RC605
CG34 J28
VCCIN_45 VCCIN_96
CG35 K17
CH10 VCCIN_46 VCCIN_97 K19
VCCIN_47 VCCIN_98 1
J30 K21
VCCIN_48 VCCIN_99 C4195 @RF@
CJ11 K23
A27 VCCIN_49 VCCIN_100 K24 33P_0201_50V8J
VCCIN_50 VCCIN_101 2
CJ34 K27
VCCIN_51 VCCIN_102
M1 Trace Length Match<25 mils
12 of 19 VCCIN_103 U1 Must be routed as differential pair to VR
SOC_SVID_ALERT# VCCIN_104
H1
SOC_SVID_CLK H2 VIDALERT# F17 VCCIN_SENSE_R RC683 1 2 0_0201_1%
SOC_SVID_DAT VIDSCK VCCIN_SENSE VSSIN_SENSE_R VCCIN_SENSE <91>
H3 G17 RC684 1 2 0_0201_1%
VIDSOUT VSSIN_SENSE VSSIN_SENSE <91>
ICL-U_BGA1526
@
A A

P014 - ICL-U(9/13)CPU PWR,SVID
5 4 3 2 1
5 4 3 2 1
+1.1V_MEM +1.1V_MEM +1.1V_MEM

EMC CAPS
PLACE <160mil FROM SOC VDDQ,
WITH EACH PAIR <470mil APART
CC130
CC131
CC132
CC133
CC134
CC135
CC136
CC137
CC138
CC139
CC140
CC141
CC142
CC643
CC646
CC644
CC647
CC645
CC648
CC660
CC663
CC662
CC664
CC661
CC665
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
EMI@ 2.2P_0201_25V8C
EMI@ 2.2P_0201_25V8C
EMI@ 2.2P_0201_25V8C
@EMI@ 2.2P_0201_25V8C
@EMI@ 2.2P_0201_25V8C
@EMI@ 2.2P_0201_25V8C
12P_0201_25V8J
12P_0201_25V8J
12P_0201_25V8J
12P_0201_25V8J
12P_0201_25V8J
12P_0201_25V8J
D D
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
10U_0402_10V6M
10U_0402_10V6M
10U_0402_10V6M
@ @ @
@EMI@
@EMI@
@EMI@
EMI@
EMI@
EMI@
Primary side cap
Follow PDG rev1.1 P.545
+1.1V_MEM
1.1V/3.5A(Processor EDS 572795 rev 1.32)

UC1M
AA37 CPU POWER 2 OF 3 BP39

AG36 VDDQ_1 VDDQ_31 BR37
VDDQ_2 VDDQ_32
AJ36 BT38
AL36 VDDQ_3 VDDQ_33 AC35
AL49 VDDQ_4 VDDQ_34 BU37
+VCCST_CPU +VCCSTG_CPU AN36 VDDQ_5 VDDQ_35 BU49
VDDQ_6 VDDQ_36
AP37 CA39
VDDQ_7 VDDQ_37
AR36 CB49
VDDQ_8 VDDQ_38
C AR37 L38 C
VDDQ_9 VDDQ_39
AT36 L49
VDDQ_10 VDDQ_40
1 1 1 1 AT49 N36
AA49 VDDQ_11 VDDQ_41 T49
CC154 @ CC153 CC155 @ CC156 VDDQ_12 VDDQ_42
AV36 AC37
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M AW37 VDDQ_13 VDDQ_43 AD35
2 2 2 2 AY36 VDDQ_14 VDDQ_44 AD36
VDDQ_15 VDDQ_45
BA37 AE36
VDDQ_16 VDDQ_46
BA49 AF49
BB36 VDDQ_17 VDDQ_47
VDDQ_18
BD36 C33
VDDQ_19 RSVD_78
BE37
VDDQ_20
C33,A33,B33 is RSVD
BF36
VDDQ_21 RSVD_2
A33 Intel recommended NC VCC1P8A shape from VR to VCC1P8A pins should have:
BF37 B33 +VCC1P8A a. total length L of < 22mm between VR and BGA.
+VCCST_CPU +1.05V_VCCST AB36 VDDQ_22 RSVD_3
VDDQ_23 b. Average width W of 1.8mm.
BF49 BG9 +VCC1P8A
VDDQ_24 VCC1P8A_1
BG36
VDDQ_25 VCC1P8A_2
BJ9 1.8V/0.7A
1 2 BJ36 BM9
RC592 0.01_0603_1% VDDQ_26 VCC1P8A_3
BL37 BW1
BM49 VDDQ_27 VCC1P8A_4 BW2 +VCCSTG_OUT
VDDQ_28 VCC1P8A_5
BN37 1 1 1
+VCCST_CPU VDDQ_29
BP38 R35
+VCCSTG_OUT_LGC +1.05V_VCCSTG VDDQ_30 VCCSTG_OUT_3 CC129 CC308 @ CC188 @
V34
+VCCSTG_CPU VCCSTG_OUT_4 10U_0402_6.3V6M 22U_0603_6.3V6M 10U_0402_10V6M
CB1 T34
VCCST VCCSTG_OUT_5 2 2 2
1.05V/0.8A VCCSTG_OUT_6
U35
1 2 BY1 AB34
VCCSTG VCCSTG_OUT_7 RSVD_W35
RC659 0.01_0603_1% 1.05V/0.15A RSVD_74
W35 1
TP72 TP@ PAD~D
+VCCSTG_OUT AA35 RSVD_AA35 1
RSVD_75 RSVD_Y34 TP71 TP@ PAD~D
Y34 1
B RSVD_76 TP73 TP@ PAD~D B
F33 +VCC1P05_OUTPUT_PLL
+VCCSTG_OUT_LGC G33 VCCSTG_OUT_1 +VCC_SFR_OC
VCCSTG_OUT_2 +VCC_SFR_OC
CD2
VCCPLL
E5
VCCSTG_OUT_LGC
1.05V/0.09A
+VCCSTG_OUT CG38
VCCPLL_OC_1
VCCPLL_OC_2
CG41 1.1V/0.16A
CG42 1 1 1
VCCPLL_OC_3 +VCCIO_OUT
1 CG49
VCCPLL_OC_4 @ @
CC144 CC145 CC189
CC191 AD7 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
1U_0201_6.3V6M 13 of 19 VCCIO_OUT 2 2 2
2 ICL-U_BGA1526
@
@
+VCC1P05_OUTPUT_PLL
1 1
CC147 CC148 @
1U_0201_6.3V6M 1U_0201_6.3V6M
2 2
A A

P015 - ICL-U(10/13)CPU PWR
5 4 3 2 1
5 4 3 2 1
1.8V/32A(Processor EDS 572795 rev 1.32) +VCCDSW_1P05 +3V_PRIM

+VCCIN_AUX
+3V_PRIM
UC1N breakout with a 3.8mm width plane
AH1 CPU POWER 3 OF 3 DF23 1 1 1
VCCIN_AUX_1 VCCPRIM_3P3_2
AW10
DG26 3.3V/0.202A
AY11 DG28 CC183 CC170 @ CC171 @
VCCIN_AUX_3 VCCPRIM_3P3_4 1U_0201_6.3V6M 1U_0201_6.3V6M
D
AY9 PLACE NEAR DF23 0.1U_0201_10V6K D
VCCIN_AUX_4 2 2 2
BA10
VCCIN_AUX_5
+VCCPRIM_1P8 PLACE NEAR DD34 PLACE NEAR DG26
BB9
CH1 VCCIN_AUX_6 DF15
CK11
DF17 1.8V/1.3A
CL10 DF18
CM11 VCCIN_AUX_9 VCCPRIM_1P8_4 DF20
CN1 VCCIN_AUX_10 VCCPRIM_1P8_5 DG17 +VCCDPHY_1P24
AJ1 VCCIN_AUX_11 VCCPRIM_1P8_6 DG18 +VCCPRIM_1P8 +1.8V_PRIM
CN10 VCCIN_AUX_12 VCCPRIM_1P8_7 DG20
CP11 DF34 breakout with a 5mm width plane
CR10 VCCIN_AUX_14 VCCPRIM_1P8_9 1 2
CT11 VCCIN_AUX_15 RC587 0.01_0603_1%
VCCIN_AUX_16 1
CU10 1 1 1
CV1 VCCIN_AUX_17 +VCCLDOSTD_OUT_0P85 CC184
VCCIN_AUX_18 4.7U_0201_6.3V6M CC173 @ CC174 @ CC175 @
CV11
VCCIN_AUX_19 +VCCA_CLKLDO_1P8 2 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
CW10 DW37 PLACE NEAR DW32
VCCIN_AUX_20 VCCLDOSTD_0P85 2 2 2
CY11
VCCIN_AUX_21
0.85V_DeCap only WITHIN 3MM FROM PLACE NEAR DG20
DC1 DW15 +VCCDPHY_1P24 PACKAGE
VCCIN_AUX_22 VCCA_CLKLDO_1P8
AL1
VCCIN_AUX_23
1.8V/0.165A
P13 DW32 +VCCDSW_1P05
VCCIN_AUX_24 VCCDPHY_1P24
R12
VCCIN_AUX_25
1.24V_DeCap only
T13 DD34 +VCC1.05_OUT_FET
VCCIN_AUX_26 VCCDSW_1P05
U12
VCCIN_AUX_27
1.05V_DeCap only PDG p.545 use XFL4012-601ME
DC11 BY2
VCCIN_AUX_28 VCC1P05_1
DE12 CB2 1.05V_Loopback SDS p.23 use UHP252012 , now use
DF12 VCCIN_AUX_29 VCC1P05_2 CC1 +VCC1P05_OUTPUT_PLL
VCCIN_AUX_30 VCC1P05_3
AM1 +VCCLDOSTD_OUT_0P85 CRB p.62 use 0.6UH/5A
AN1 VCCIN_AUX_31 CD1 +VCCA_CLKLDO_1P8 +1.8V_PRIM
VCCIN_AUX_32 VCCPLL
AT11
VCCIN_AUX_33
1.05V/0.09A GND shield around the VCC trace routing
AT9 DG31
AU10 VCCIN_AUX_34 VCCPRIM_1P05_1 0.68UH_UHP252012NF-R68M_3A_20% 1 @ 2 LC1
VCCIN_AUX_35
Trace Length Match<25 mils AV9 DG29 1
TP100 TP@ 1 1 PLACE NEAR DW15
VCCIN_AUX_36 VCCPRIM_1P05_2 PAD~D
Must be routed as differential pair to VR 0.8mm width plane
RC685 1 2 0_0201_1% VCCIN_AUX_VCCSENSE_R BF9 DF29 +VCC1.05_OUT_PCH CC260 CC185 1 2
<89> VCCIN_AUX_VCCSENSE VCCIN_AUX_VCCSENSE VCCPRIM_1P05_3
1
RC686 1 2 0_0201_1% VCCIN_AUX_VSSSENSE_R BD9 1U_0201_6.3V6K 1U_0201_6.3V6K RC120 0.01_0603_1%
C <89> VCCIN_AUX_VSSSENSE VCCIN_AUX_VSSSENSE +VCCPRTC_3P3 2 2 C
DF31 PLACE NEAR DW37 1
VCCPRIM_1P05_4
+V1.05A_BYPASS 1.05V_Loopback WITHIN 3MM FROM RC589
DG33 +3VALW_DSW PACKAGE CC177 @ 0.1_0402_1%
VCCRTC 1U_0201_6.3V6M
+VNN_BYPASS DJ15 3.3V/0.002A
2
VCC_V1P05EXT_1P05 2
1.05V/0.2A DE31 +3V_1.8V_HDA 1
VCCDSW_3P3
+VCCPFUSE_3P3 CY34
VCC_VNNEXT_1P05
3.3V/0.004 A
1.05V/0.2A VCCPGPPR
DF26 CC176
+VCCPRIM_1P8 DC33 3.3V,1.8V,1.5V/0.005A 47U_0603_6.3V6M
VCCPRIM_3P3_1 CL38 CORE_VID0_R RC690 1 2 0_0201_1% CORE_VID0 2
GPP_B0/CORE_VID0 CORE_VID1_R CORE_VID1 CORE_VID0 <78,89>
+V3.3A_1.8A_PCH_SPI DD35 CJ38 RC689 1 2 0_0201_1%
VCCPRIM_1P8_1 GPP_B1/CORE_VID1 VRALERT#_R CORE_VID1 <78,89>
CN38 VRALERT# RC688 1 2 0_0201_5%
GPP_B2/VRALERT# VRALERT#_R <83> +VCCPRTC_3P3 +RTCVCC
DB34
VCCSPI
3.3V/0.003A
14 of 19 2.6mm width plane RC696
ICL-U_BGA1526 1 2 +3VALW_DSW
@
0.01_0402_1% breakout with a 1.4mm width plane
1 1
RC699 1 2 0_0201_5% PCH_PRIM_EN_R 1 2 CC181 CC182

<11,47,49,58> SIO_SLP_SUS# PCH_PRIM_EN <88> 1
0.1U_0201_10V6K 1U_0201_6.3V6M
<78> VCCDSW_EN_GPIO 2 2
DC1 0_0402_5% PLACE NEAR DG33 CC180 @
1M_0201_5%
1
VCCDSW_EN_Q 1U_0201_6.3V6M
0.1U_0402_25V6
RC697 1 2 0_0201_5% 2 1 RC698 1 @ 2 0_0201_5% RC505
<58> VCCDSW_EN
@ RC508
@ CC511
1
1uF cap should place after the 0.1uF cap. 2 PLACE NEAR DE31
RB751S40T1G_SOD523-2
0.1uF cap should place before the 1uF cap.
2
DC2
2
1 2
<58,78> ALW_PWRGD_3V_5V
Power reserved
+3V_PRIM
For volume segment platform this rail is disabled. +1.8V_PRIM
B Keep the pin floating (do not short this pin to ground). B
2
+3V_PRIM +V3.3A_1.8A_PCH_SPI
RC744 +3VALW
+V1.05A_BYPASS RC583 20K_0201_5%
0_0402_5% CORE_VID0 @ RC609 2 1 10K_0201_5%
RC595 1 @ 2 100K_0201_5% 1 2
1
+VNN_BYPASS D21 @ RC611 2 1 10K_0201_5%

VRALERT#_R 1 2 CORE_VID0 RC663 2 1 10K_0201_5%
1 H_PROCHOT# <11,58,86,91> CORE_VID1 CORE_VID1
RC648 1 @ 2 100K_0201_5% +1.8V_PRIM RC582 CC30 @ RC664 2 1 10K_0201_5% @ RC610 2 1 10K_0201_5%
0_0402_5% 0.1U_0201_10V6K RB751S40T1G_SOD523-2
1 @ 2 @ RC612 2 1 10K_0201_5%
2
Follow #575759 p.32
+3V_PRIM RC168 LC2 +3V_1.8V_HDA

+3V_PRIM 0_0402_5% BLM18EG221TN1D_2P~D
1 @ 2 +3V_1.8V_HDA_R 1 2
Close to RC164
1 2 2
+1.8V_PRIM RC165 RF@ RF@ 1
@ CC164 0_0402_5% CC167 CC168 CC23
10P_0201_25V8 1 2 2.2P_0201_25V 2.2P_0201_25V 0.1U_0201_10V6K
2 1 1
2
A A
+3V_PRIM +VCCPFUSE_3P3
RC747
0.01_0402_1%
1 2

P016 - ICL-U(11/13)PCH Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
5 4 3 2 1
5 4 3 2 1
UC1O UC1P UC1Q

D GND 1 OF 3 GND 2 OF 3 DJ33 GND 3 OF 3 F11 D
A11 AF45 BT3 CR37 DJ36 VSS_297 VSS_362 F31
A46 VSS_1 VSS_75 AF47 BT39 VSS_149 VSS_223 CR45 DJ42 VSS_298 VSS_363 F45
BA45 VSS_2 VSS_76 AG1 BT41 VSS_150 VSS_224 CR49 DK3 VSS_299 VSS_364 F47
VSS_3 VSS_77 VSS_151 VSS_225 VSS_300 VSS_365
BA47 AG11 BT42 CT37 DK4 F8
BB11 AG3 BT43 CT39 DK49 G21
BB3 VSS_5 VSS_79 AG38 BT7 VSS_153 VSS_227 CT42 DK6 VSS_302 VSS_367 G24
BB7 AG39 BU45 CT9 DK8 G3
BC37 VSS_7 VSS_81 AG41 BU47 VSS_155 VSS_229 CU45 DL10 VSS_304 VSS_369 G31
BD3 A31 BV1 CU47 DL13 G36
BD38 AG42 BV11 CU49 DL44 G49
BD39 AG43 BV2 CV3 DL47 G5
BD41 AG5 BV3 CV34 DM47 H17
A48 AG9 BV7 CV35 DN15 H21
BD42 VSS_13 VSS_87 AH2 BW3 VSS_161 VSS_235 CV5 DN19 VSS_310 VSS_375 H24
BD43 VSS_14 VSS_88 AH37 BW37 VSS_162 VSS_236 CV9 DN24 VSS_311 VSS_376 H31
BD45 VSS_15 VSS_89 AH45 BW5 VSS_163 VSS_237 CY41 DN31 VSS_312 VSS_377 H33
BD49 VSS_16 VSS_90 AH49 BW6 VSS_164 VSS_238 CY45 DN36 VSS_313 VSS_378 H36
BD5 AJ2 BW7 CY49 DN42 H45
BD6 AJ3 BY37 CY9 DP45 H49
BD7 A34 BY45 D13 DR49 J10
BE1 AK37 BY49 D17 DT1 J13
BE2 VSS_21 VSS_95 AL2 C11 VSS_169 VSS_243 D31 DT10 VSS_318 VSS_383 J16
BF3 AL45 C13 D44 DT15 J36
A49 VSS_23 VSS_97 AL47 C14 VSS_171 VSS_245 D49 DT20 VSS_320 VSS_385 J6
BF45 VSS_24 VSS_98 AL6 C17 VSS_172 VSS_246 DA10 DT27 VSS_321 VSS_386 K11
BF47 VSS_25 VSS_99 AM2 C21 VSS_173 VSS_247 DA33 DT3 VSS_322 VSS_387 K33
BF7 AM37 C24 DA9 DT32 K8
BG3 AN2 C31 DB32 DT37 L36
C BG41 AN38 C34 DB35 DT42 L39 C
BG7 AN39 C39 DB38 DT49 L41
BH37 A36 C48 DB45 DT6 L42
BJ1 VSS_31 VSS_105 AN41 C49 VSS_179 VSS_253 DB47 DT7 VSS_328 VSS_393 L43
BJ2 AN42 C6 DB49 DT8 L45
BJ3 VSS_33 VSS_107 AN43 CA3 VSS_181 VSS_255 DC3 DU1 VSS_330 VSS_395 L47
AA45 VSS_34 VSS_108 AN45 CA38 VSS_182 VSS_256 DC49 DU10 VSS_331 VSS_396 M10
BJ41 AN49 CA41 DC5 DU15 M3
BJ43 AN6 CA42 DC6 DU2 M36
BJ45 VSS_37 VSS_111 AR1 CA43 VSS_185 VSS_259 DD37 DU20 VSS_334 VSS_399 M5
BJ49 AR11 CA7 DD42 DU27 N45
BJ7 AR2 CB37 DE10 DU32 N49
BM11 VSS_40 VSS_114 AR3 CB45 VSS_188 VSS_262 DE13 DU37 VSS_337 VSS_402 P11
BM3 A39 CB47 DE17 DU48 P41
BM45 VSS_42 VSS_116 AR7 CC3 VSS_190 VSS_264 DE18 DU49 VSS_339 VSS_404 P8
BM47 AR9 CC7 DE20 DU7 R3
BM5 AT3 CE37 DE22 DV2 R37
AA47 VSS_45 VSS_119 AT45 CE45 VSS_193 VSS_267 DE23 DV44 VSS_342 VSS_407 T11
BM6 AT47 CE49 DE26 DV48 T36
BM7 VSS_47 VSS_121 AT5 CE9 VSS_195 VSS_269 DE28 DV8 VSS_344 VSS_409 T41
BP1 AT6 CG37 DE29 DW1 T43
BP2 AT7 CG39 DE33 DW10 T45
BP3 AU37 CG43 DE45 DW2 T47
BP43 AV11 CG45 DE6 DW20 U3
BP7 VSS_52 VSS_126 A42 CG47 VSS_200 VSS_274 DF13 DW27 VSS_349 VSS_414 U37
BR45 VSS_53 VSS_127 AV3 CG9 VSS_201 VSS_275 DF22 DW44 VSS_350 VSS_415 U5
BR49 AV38 CH3 DF28 DW46 V11
AB11 AV39 CH5 DF33 DW48 V36
AB3 AV41 CJ37 DF35 DW49 V45
B AB38 VSS_57 VSS_131 AV42 CJ42 VSS_205 VSS_279 DF39 DW7 VSS_354 VSS_419 V49 B
AB39 VSS_58 VSS_132 AV43 CJ9 VSS_206 VSS_280 DG10 E11 VSS_355 VSS_420 V9
AB41 AV45 CK45 DG12 E34 W37
A17 AV49 CK49 DG13 E36 Y36
AB42 AV7 CK9 DG15 E39 Y38
AB43 VSS_62 VSS_136 AY3 CL37 VSS_210 VSS_284 DG22 E42 VSS_359 VSS_424 Y43
AB5 A44 CL42 DG23 E6 Y9
AB6 AY7 CL49 DG47 DE15
AC45 VSS_65 VSS_139 B17 CM45 VSS_213 VSS_287 DG6 VSS_427
VSS_66 VSS_140 VSS_214 VSS_288 17 of 19
AC49 B2 CM47 DH1
VSS_67 VSS_141 VSS_215 VSS_289 ICL-U_BGA1526
AD10 B21 CM9 DH3
VSS_68 VSS_142 VSS_216 VSS_290
AD11 B24 CN3 DH45 @
AD34 B3 CN37 DH5
AD37 VSS_70 VSS_144 B31 CN39 VSS_218 VSS_292 DJ19
A3 B48 CN5 DJ21
AE6 VSS_72 VSS_146 BA1 CP9 VSS_220 VSS_294 DJ27
AF37 BA2 CR32 DJ31
15 of 19 16 of 19
ICL-U_BGA1526 ICL-U_BGA1526
@ @
A A

P017 - ICL-U(12/13)GND
5 4 3 2 1
5 4 3 2 1
UC1S
AG6 RESERVED SIGNALS A47

<79> MIPI60_CFG0# CFG_0 RSVD_TP_1
AE7 B47
AG7
<79> MIPI60_CFG2# CFG_2 TP_C1
AD9 C1 1
<79> MIPI60_CFG3# CFG_3 RSVD_57 TP_E1 TP59 TP@ PAD~D
AE9 E1 1
<79> MIPI60_CFG4# CFG_4 RSVD_58 TP60 TP@ PAD~D
AB9
<79> MIPI60_CFG5# CFG_5
AJ6 CT32
AB7 CV32
V10
<79> MIPI60_CFG8# CFG_8 TP_G15
AJ5 G15 1
<79> MIPI60_CFG9# CFG_9 RSVD_79 TP_F15 TP8 TP@ PAD~D
Y10 F15 1
<79> MIPI60_CFG10# CFG_10 RSVD_80 TP7 TP@ PAD~D
D AJ7 D
<79> MIPI60_CFG11# CFG_11 TP_BW11
AB10 BW11 1
<79> MIPI60_CFG12# CFG_12 RSVD_TP_5 TP_CA11 TP3 TP@ PAD~D
AL7 CA11 1
<79> MIPI60_CFG13# CFG_13 RSVD_TP_6 TP4 TP@ PAD~D
AL9
<79> MIPI60_CFG14# CFG_14
AJ9 C16
<79> MIPI60_CFG15# CFG_15 VSS_428
A16
V6 VSS_429
<79> MIPI60_CFG_STB0_DN CFG_16
<79> MIPI60_CFG_STB0_DP V7 C2
CFG_17 RSVD_55 A4
RSVD_56
<79> MIPI60_CFG_STB1_DN Y6
CFG_18
<79> MIPI60_CFG_STB1_DP Y7 DP5
CFG_19 RSVD_65
DR5
49.9_0201_1% RC2 CFG_RCOM RSVD_66
1 2 AD6
CFG_RCOMP
D14
T9 RSVD_59 E16
<79> MIPI60_MBP0# BPM#0 RSVD_60
T7
<79> MIPI60_MBP1# BPM#1
MBP2# T10 DV6
T6 BPM#2 RSVD_TP_13 DW6
MBP3#
BPM#3 RSVD_TP_14
BJ11 DP2
RSVD_62 RSVD_TP_24
BL10 DP1
+VCCIO_OUT RSVD_63 RSVD_TP_25
AV1 DW4
RSVD_TP_17 RSVD_TP_15
DV4
RC723 1 @ 2 10K_0201_5% MBP2# AT2 RSVD_TP_16
RC724 1 @ 2 10K_0201_5% MBP3# AT1 RSVD_TP_18 CM33 TP_CM33 1
RSVD_TP_20 TP_3 TP_DB10 TP16 TP@ PAD~D
AU1 DB10 1
RSVD_TP_19 TP_4 TP15 TP@ PAD~D
AU2
RSVD_TP_21 TP_R1
R1 1
RSVD_TP_12 TP18 TP@ PAD~D
C AV2 C
RSVD_TP_22 TP_DW3
DW3 1
RSVD_TP_7 TP_DV3 TP17 TP@ PAD~D
DP3 DV3 1
RSVD_67 RSVD_TP_8 TP19 TP@ PAD~D
DT2
RSVD_68
DH49
AR10 RSVD_TP_9
AP10 RSVD_69 DL8
RSVD_71 RSVD_TP_23
BP36
RSVD_70 TP_DW47
BM36 DW47 1 PAD~D
RSVD_72 TP_1 TP_DV47 TP23 TP@
DV47 1 PAD~D
TP_2 TP24 TP@
J15 DU47
VSS_430 VSS_432
K15
VSS_431 P10
RSVD_TP_26
C5
D4 SKTOCC#
RSVD_77
A5
RSVD_64 19 of 19
ICL-U_BGA1526
@
UC1R
1 TP_N34 N34 DA11 TP_DA11 1
PAD~D TP@ TP88 TP_AK10 RSVD_TP_28 RSVD_TP_35 TP_CL32 TP96 TP@ PAD~D
1 AK10 RESERVED SIGNALS CL32 1
PAD~D TP@ TP89 RSVD_TP_29 RSVD_TP_36 TP_CN32 TP97 TP@ PAD~D
BT36 CN32 1
TP_AH10 RSVD_7 RSVD_TP_37 TP98 TP@ PAD~D
1 AH10 CY35
PAD~D TP@ TP90 1 TP_BC10 BC10
RSVD_TP_30 RSVD_32
DB37
PAD~D TP@ TP91 1 TP_CH33 CH33
RSVD_TP_31 RSVD_33
DF37
PAD~D TP@ TP92 RSVD_TP_32 RSVD_34
B CJ32 BF11 IST_TP_0 1 B
TP_AM10 RSVD_12 IST_TP_0 IST_TP_1 TP62 TP@ PAD~D
1 AM10 BD11 1
PAD~D TP@ TP93 TP_BH10 RSVD_TP_33 IST_TP_1 IST_TRIG_0 TP61 TP@ PAD~D
1 BH10 BE10 1
PAD~D TP@ TP94 TP_J34 RSVD_TP_34 IST_TRIG_0 IST_TRIG_1 TP64 TP@ PAD~D
1 J34 BF10 1
PAD~D TP@ TP95 RSVD_TP_27 IST_TRIG_1 TP63 TP@ PAD~D
Y11 CW33 PCH_IST_TP_0 1
RSVD_L34 RSVD_9 PCH_IST_TP_0 PCH_IST_TP_1 TP66 TP@ PAD~D
1 L34 CY32 1
PAD~D TP@ TP67 RSVD_10 PCH_IST_TP_1 TP65 TP@ PAD~D
AJ11 CY37
RSVD_17 RSVD_27
CG32 CV37
RSVD_21 RSVD_28
CK33
BP41 RSVD_22 G34
RSVD_20 RSVD_35
AL11 H34
BG11 RSVD_23 RSVD_46 DJ34
RSVD_24 RSVD_48
AN11 DK31
RSVD_16 RSVD_49
M13 DK15
RSVD_M34 RSVD_18 RSVD_50
1 M34 CP3
PAD~D TP@ TP68 RSVD_19 RSVD_51
CP5
RSVD_52 AN9
RSVD_53 AN7
RSVD_54
AF10
RSVD_36
DU42 AE11
RSVD_42 RSVD_37
DW42 H5
D33 RSVD_43 RSVD_38 D1
L13 RSVD_44 RSVD_39 DJ40
RSVD_45 RSVD_40
K13 DK40
RSVD_47 RSVD_41
A A
ICL-U_BGA1526
@

P018 - ICL-U(13/13)RSVD,MIPI60
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P019 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P020 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P021 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P022 - Reserve
5 4 3 2 1
5 4 3 2 1
+VDDQ_MEM
UD1A
DDRA +VDDQ_MEM
UD2A
DDRB
D D
1 2 A5 J8 DDR_A_CLK RD21 1 2 240_0201_1% A5 J8 DDR_B_CLK
ZQ0 CK_ta DDR_A_CLK# DDR_A_CLK <7> ZQ0 CK_ta DDR_B_CLK# DDR_B_CLK <7>
RD2 240_0201_1% J9 J9
CK_ca DDR_A_CLK# <7> CK_ca DDR_B_CLK# <7>
+1.1V_MEM 1 2 A8 P8 DDR_A_CLK +1.1V_MEM RD22 1 2 240_0201_1% A8 P8 DDR_B_CLK

RD1 240_0201_1% ZQ1 CK_tb P9 DDR_A_CLK# ZQ1 CK_tb P9 DDR_B_CLK#
CK_cb CK_cb
DDR_A_CA0 H2 J4 DDR_A_CKE0 DDR_B_CA0 H2 J4 DDR_B_CKE0

<7> DDR_A_CA0 CA0a CKE0a DDR_A_CKE0 <7> <7> DDR_B_CA0 CA0a CKE0a DDR_B_CKE0 <7>
2
DDR_A_CA1 J2 DDR_B_CA1 J2
<7> DDR_A_CA1 DDR_A_CA2 CA1a DDR_A_CKE1 <7> DDR_B_CA1 DDR_B_CA2 CA1a DDR_B_CKE1
RD25 H9 J5 RD29 H9 J5
<7> DDR_A_CA2 DDR_A_CA3 CA2a CKE1a DDR_A_CKE1 <7> <7> DDR_B_CA2 DDR_B_CA3 CA2a CKE1a DDR_B_CKE1 <7>
0_0201_5% <7> DDR_A_CA3 H10 0_0201_5% <7> DDR_B_CA3 H10
DDR_A_CA4 H11 CA3a P4 DDR_A_CKE0 DDR_B_CA4 H11 CA3a P4 DDR_B_CKE0
<7> DDR_A_CA4 DDR_A_CA5 CA4a CKE0b <7> DDR_B_CA4 DDR_B_CA5 CA4a CKE0b
J11 J11
1 <7> DDR_A_CA5 <7> DDR_B_CA5
1
CA5a P5 DDR_A_CKE1 CA5a P5 DDR_B_CKE1
DDR_A_ODTA CKE1b DDR_B_ODTA CKE1b
DDR_A_CA0 R2 DDR_B_CA0 R2
DDR_A_CA1 P2 CA0b DDR_B_CA1 P2 CA0b
1
1
DDR_A_CA2 R9 CA1b H4 DDR_A_CS#0 DDR_B_CA2 R9 CA1b H4 DDR_B_CS#0
DDR_A_CA3 CA2b CS0a DDR_A_CS#0 <7> DDR_B_CA3 CA2b CS0a DDR_B_CS#0 <7>
RD26 @ R10 RD30 @ R10
0_0201_5% DDR_A_CA4 R11 CA3b H3 DDR_A_CS#1 0_0201_5% DDR_B_CA4 R11 CA3b H3 DDR_B_CS#1
DDR_A_CA5 CA4b CS1a DDR_A_CS#1 <7> DDR_B_CA5 CA4b CS1a DDR_B_CS#1 <7>
P11 P11
CA5b R4 DDR_A_CS#0 ODT PD reserved -- CRB P.84 CA5b R4 DDR_B_CS#0
ODT PD reserved -- CRB P.83
2
2
CS0b CS0b
DDR_A_ODTA G2 R3 DDR_A_CS#1 DDR_B_ODTA G2 R3 DDR_B_CS#1
DDR_A_ODTB T2 ODTa CS1b DDR_B_ODTB T2 ODTa CS1b
ODTb ODTb
A1 C3 A1 C3
+1.1V_MEM A2 DNU_1 DMI0a C10 +1.1V_MEM A2 DNU_1 DMI0a C10
A11 DNU_2 DMI1a A11 DNU_2 DMI1a
A12 DNU_3 Y3 A12 DNU_3 Y3
DNU_4 DMI0b SHORTEST PATH TO GND DNU_4 DMI0b SHORTEST PATH TO GND
B1 Y10 B1 Y10
B12 DNU_5 DMI1b B12 DNU_5 DMI1b
DNU_6 DNU_6
2
2
AA1 AA1
RD27 AA12 DNU_7 T11 DDR_DRAMRST#_R RD31 AA12 DNU_7 T11 DDR_DRAMRST#_R
DNU_8 RESET DDR_DRAMRST#_R <7,24> DNU_8 RESET
0_0201_5% AB1 0_0201_5% AB1
AB2 DNU_9 AB2 DNU_9
AB11 DNU_10 AB11 DNU_10
1
1
DDR_A_ODTB DNU_12 DDR_B_ODTB DNU_12
DDR_A_D3_2 B2 AA2 DDR_A_D0_6 DDR_B_D1_7 B2 AA2 DDR_B_D3_6

<7> DDR_A_D3_2 DDR_A_D0_6 <7> <7> DDR_B_D1_7 DDR_B_D3_6 <7>
1
1
DDR_A_D3_0 C2 DQ0a DQ0b Y2 DDR_A_D0_1 DDR_B_D1_6 C2 DQ0a DQ0b Y2 DDR_B_D3_2
<7> DDR_A_D3_0 DDR_A_D3_1 DQ1a DQ1b DDR_A_D0_5 DDR_A_D0_1 <7> <7> DDR_B_D1_6 DDR_B_D1_2 DQ1a DQ1b DDR_B_D3_0 DDR_B_D3_2 <7>
RD28 @ E2 V2 RD32 @ E2 V2
0_0201_5% F2 U2 0_0201_5% F2 U2
F4 U4 F4 U4
E4 V4 E4 V4
ODT PD reserved -- CRB P.83 <7> DDR_A_D3_5 DDR_A_D0_2 <7> <7> DDR_B_D1_0 DDR_B_D3_7 <7>
2
2
DDR_A_D3_6 C4 DQ5a DQ5b Y4 DDR_A_D0_0 DDR_B_D1_3 C4 DQ5a DQ5b Y4 DDR_B_D3_5
C B4 AA4 B4 AA4 C
B11 AA11 B11 AA11
C11 Y11 C11 Y11
E11 V11 E11 V11
<7> DDR_A_D2_3 DDR_A_D2_6 F11 DQ10a DQ10b U11 DDR_A_D1_1 DDR_A_D1_2 <7> ODT PD reserved -- CRB P.84 <7> DDR_B_D0_6 DDR_B_D0_5 F11 DQ10a DQ10b U11 DDR_B_D2_4 DDR_B_D2_2 <7>
F9 U9 F9 U9
E9 V9 E9 V9
C9 Y9 C9 Y9
B9 AA9 B9 AA9
<7> DDR_A_D2_2 DQ15a DQ15b DDR_A_D1_7 <7> <7> DDR_B_D0_0 DQ15a DQ15b DDR_B_D2_7 <7>
DDR_A_DQS3 D3 W3 DDR_A_DQS0 DDR_B_DQS1 D3 W3 DDR_B_DQS3

<7> DDR_A_DQS3 DDR_A_DQS#3 DQS0_ta DQS0_tb DDR_A_DQS#0 DDR_A_DQS0 <7> <7> DDR_B_DQS1 DDR_B_DQS#1 DQS0_ta DQS0_tb DDR_B_DQS#3 DDR_B_DQS3 <7>
E3 V3 DDR_A_DQS#0 <7> E3 V3 DDR_B_DQS#3 <7>
<7> DDR_A_DQS#3 DQS0_ca DQS0_cb <7> DDR_B_DQS#1 DQS0_ca DQS0_cb
DDR_A_DQS2 D10 W10 DDR_A_DQS1 DDR_B_DQS0 D10 W10 DDR_B_DQS2
<7> DDR_A_DQS2 DDR_A_DQS#2 DQS1_ta DQS1_tb DDR_A_DQS#1 DDR_A_DQS1 <7> <7> DDR_B_DQS0 DDR_B_DQS#0 DQS1_ta DQS1_tb DDR_B_DQS#2 DDR_B_DQS2 <7>
E10 V10 DDR_A_DQS#1 <7> E10 V10 DDR_B_DQS#2 <7>
<7> DDR_A_DQS#2 DQS1_ca DQS1_cb <7> DDR_B_DQS#0 DQS1_ca DQS1_cb
H9HCNNNBUUMLHR-NLM_FBGA200 H9HCNNNBUUMLHR-NLM_FBGA200
@ @
+1.8V_MEM UD1C UD1B

+VDDQ_MEM
95mA 323mA +1.8V_MEM UD2C UD2B
F1 B3 A3 N4 +VDDQ_MEM
F12 VDD1_1 VDDQ_1 B5 A10 VSS_1 VSS_30 N9
VDD1_2 VDDQ_2 VSS_2 VSS_31
95mA 323mA
G4 B8 C1 N11 F1 B3 A3 N4
G9 VDD1_3 VDDQ_3 B10 C5 VSS_3 VSS_32 P1 F12 VDD1_1 VDDQ_1 B5 A10 VSS_1 VSS_30 N9
T4 VDD1_4 VDDQ_4 D1 C8 VSS_4 VSS_33 P3 G4 VDD1_2 VDDQ_2 B8 C1 VSS_2 VSS_31 N11
T9 VDD1_5 VDDQ_5 D5 C12 VSS_5 VSS_34 P10 G9 VDD1_3 VDDQ_3 B10 C5 VSS_3 VSS_32 P1
U1 VDD1_6 VDDQ_6 D8 D2 VSS_6 VSS_35 P12 T4 VDD1_4 VDDQ_4 D1 C8 VSS_4 VSS_33 P3
U12 VDD1_7 VDDQ_7 D12 D4 VSS_7 VSS_36 T1 T9 VDD1_5 VDDQ_5 D5 C12 VSS_5 VSS_34 P10
VDD1_8 VDDQ_8 F3 D9 VSS_8 VSS_37 T3 U1 VDD1_6 VDDQ_6 D8 D2 VSS_6 VSS_35 P12
+1.1V_MEM VDDQ_9 F10 D11 VSS_9 VSS_38 T5 U12 VDD1_7 VDDQ_7 D12 D4 VSS_7 VSS_36 T1
A4 VDDQ_10 U3 E1 VSS_10 VSS_39 T8 VDD1_8 VDDQ_8 F3 D9 VSS_8 VSS_37 T3
422mA VDD2_1 VDDQ_11 VSS_11 VSS_40 +1.1V_MEM VDDQ_9 VSS_9 VSS_38
A9 U10 E5 T10 F10 D11 T5
F5 VDD2_2 VDDQ_12 W1 E8 VSS_12 VSS_41 T12 A4 VDDQ_10 U3 E1 VSS_10 VSS_39 T8
422mA VDD2_1 VDDQ_11 VSS_11 VSS_40
F8 W5 E12 V1 A9 U10 E5 T10
H1 VDD2_4 VDDQ_14 W8 G1 VSS_14 VSS_43 V5 F5 VDD2_2 VDDQ_12 W1 E8 VSS_12 VSS_41 T12
H5 VDD2_5 VDDQ_15 W12 G3 VSS_15 VSS_44 V8 F8 VDD2_3 VDDQ_13 W5 E12 VSS_13 VSS_42 V1
H8 VDD2_6 VDDQ_16 AA3 G5 VSS_16 VSS_45 V12 H1 VDD2_4 VDDQ_14 W8 G1 VSS_14 VSS_43 V5
H12 VDD2_7 VDDQ_17 AA5 G8 VSS_17 VSS_46 W2 H5 VDD2_5 VDDQ_15 W12 G3 VSS_15 VSS_44 V8
K1 VDD2_8 VDDQ_18 AA8 G10 VSS_18 VSS_47 W4 H8 VDD2_6 VDDQ_16 AA3 G5 VSS_16 VSS_45 V12
K3 VDD2_9 VDDQ_19 AA10 G12 VSS_19 VSS_48 W9 H12 VDD2_7 VDDQ_17 AA5 G8 VSS_17 VSS_46 W2
K10 VDD2_10 VDDQ_20 J1 VSS_20 VSS_49 W11 K1 VDD2_8 VDDQ_18 AA8 G10 VSS_18 VSS_47 W4
K12 VDD2_11 J3 VSS_21 VSS_50 Y1 K3 VDD2_9 VDDQ_19 AA10 G12 VSS_19 VSS_48 W9
N1 VDD2_12 G11 J10 VSS_22 VSS_51 Y5 K10 VDD2_10 VDDQ_20 J1 VSS_20 VSS_49 W11
N3 VDD2_13 NC_1 K5 J12 VSS_23 VSS_52 Y8 K12 VDD2_11 J3 VSS_21 VSS_50 Y1
N10 VDD2_14 NC_2 K8 K2 VSS_24 VSS_53 Y12 +VDDQ_MEM N1 VDD2_12 G11 J10 VSS_22 VSS_51 Y5
N12 VDD2_15 NC_3 N5 K4 VSS_25 VSS_54 AB3 N3 VDD2_13 NC_1 K5 J12 VSS_23 VSS_52 Y8
B VDD2_16 NC_4 VSS_26 VSS_55 VDD2_14 NC_2 VSS_24 VSS_53 B
R1 N8 K9 AB5 N10 K8 K2 Y12
VDD2_17 NC_5 VSS_27 VSS_56 VDD2_15 NC_3 VSS_25 VSS_54
R5
VDD2_18
K11
VSS_28 VSS_57
AB8 1 CD45 1 CD46 1 CD47 1 CD48 1 CD49 1 CD50 1 CD91 N12
VDD2_16 NC_4
N5 K4
VSS_26 VSS_55
AB3
R8 N2 AB10 R1 N8 K9 AB5
R12 VDD2_19 VSS_29 VSS_58 R5 VDD2_17 NC_5 K11 VSS_27 VSS_56 AB8
VDD2_20 VDD2_18 VSS_28 VSS_57
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
U5 R8 N2 AB10
U8 VDD2_21 H9HCNNNBUUMLHR-NLM_FBGA200 2 2 2 2 2 2 2 R12 VDD2_19 VSS_29 VSS_58
VDD2_22 VDD2_20
@EMI@
@EMI@
@EMI@
@EMI@
@EMI@
@EMI@
@EMI@
AB4 @ U5
AB9 VDD2_23 U8 VDD2_21 H9HCNNNBUUMLHR-NLM_FBGA200
VDD2_24 AB4 VDD2_22
VDD2_23 @
AB9
H9HCNNNBUUMLHR-NLM_FBGA200 VDD2_24
@
H9HCNNNBUUMLHR-NLM_FBGA200
UD1 +VDDQ_MEM
@
UD2
1 1 1 1 1 1 1
CD27 CD28 CD43 CD44 CD65 CD66 CD81
+1.8V_MEM +1.1V_MEM +VDDQ_MEM
+1.8V_MEM +1.1V_MEM
2.2P_0201_50V8B
2.2P_0201_50V8B
2.2P_0201_50V8B
2.2P_0201_50V8B
2.2P_0201_50V8B
2.2P_0201_50V8B
2.2P_0201_50V8B
+VDDQ_MEM
2 2 2 2 2 2 2
1
CD67 CD68 CD69 CD70 CD71 CD72 CD73 CD74 CD75 CD76 CD77 CD78 CD79 CD80
1
@EMI@
@EMI@
@EMI@
@EMI@
@EMI@
@EMI@
@EMI@
CD51 CD52 CD53 CD54 CD55 CD56 CD57 CD58 CD59 CD60 CD61 CD62 CD63 CD64
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
2
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
2
2
+1.1V_MEM +VDDQ_MEM
EMC CAPS +1.8V_MEM +1.1V_MEM +VDDQ_MEM
+1.8V_MEM
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD308 CD306 CD311 CD89 CD90 CD312 CD12 CD304 CD313 CD7 CD307 CD314 CD87 CD88 CD315
1 1 1
CD305 CD303 CD310 RF@ RF@ RF@ RF@ RF@
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
RF@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
100P_0201_50V8J
10U_0402_6.3V6M
10U_0402_6.3V6M
2 2 2
A A

Issued Date 2020/10/01 2018/10/01 Title
Deciphered Date
P023 - LPDDR4/x Channel A/B
Size Document Number Re v
0.1 (X00)
5 4 3 2 1
5 4 3 2 1
D
+VDDQ_MEM
UD3A
DDRC +VDDQ_MEM
UD4A
DDRD D
1 2 A5 J8 DDR_C_CLK RD23 1 2 240_0201_1% A5 J8 DDR_D_CLK

ZQ0 CK_ta DDR_C_CLK# DDR_C_CLK <8> ZQ0 CK_ta DDR_D_CLK# DDR_D_CLK <8>
RD4 240_0201_1% J9 DDR_C_CLK# <8> J9 DDR_D_CLK# <8>
CK_ca CK_ca
1 2 A8 P8 DDR_C_CLK +1.1V_MEM RD24 1 2 240_0201_1% A8 P8 DDR_D_CLK
+1.1V_MEM RD3 240_0201_1% ZQ1 CK_tb P9 DDR_C_CLK# ZQ1 CK_tb P9 DDR_D_CLK#
CK_cb CK_cb
DDR_C_CA0 H2 J4 DDR_C_CKE0 DDR_D_CA0 H2 J4 DDR_D_CKE0

<8> DDR_C_CA0 DDR_C_CKE0 <8> <8> DDR_D_CA0 DDR_D_CKE0 <8>
2
DDR_C_CA1 J2 CA0a CKE0a DDR_D_CA1 J2 CA0a CKE0a
<8> DDR_C_CA1 CA1a <8> DDR_D_CA1 CA1a
2
DDR_C_CA2 H9 J5 DDR_C_CKE1 RD37 DDR_D_CA2 H9 J5 DDR_D_CKE1
<8> DDR_C_CA2 DDR_C_CA3 CA2a CKE1a DDR_C_CKE1 <8> <8> DDR_D_CA2 DDR_D_CA3 CA2a CKE1a DDR_D_CKE1 <8>
RD33
<8> DDR_C_CA3 H10 0_0201_5% <8> DDR_D_CA3 H10
DDR_C_CA4 H11 CA3a P4 DDR_C_CKE0 DDR_D_CA4 H11 CA3a P4 DDR_D_CKE0
0_0201_5% <8> DDR_C_CA4 <8> DDR_D_CA4
DDR_C_CA5 J11 CA4a CKE0b DDR_D_CA5 J11 CA4a CKE0b
<8> DDR_C_CA5 <8> DDR_D_CA5
1
CA5a P5 DDR_C_CKE1 CA5a P5 DDR_D_CKE1
1
CKE1b DDR_D_ODTA CKE1b

DDR_C_ODTA DDR_C_CA0 R2 DDR_D_CA0 R2
DDR_C_CA1 P2 CA0b DDR_D_CA1 P2 CA0b
CA1b CA1b
1
DDR_C_CA2 R9 H4 DDR_C_CS#0 DDR_D_CA2 R9 H4 DDR_D_CS#0
DDR_C_CS#0 <8> DDR_D_CS#0 <8>
1
DDR_C_CA3 R10 CA2b CS0a RD38 @ DDR_D_CA3 R10 CA2b CS0a

RD34 @ DDR_C_CA4 R11 CA3b H3 DDR_C_CS#1 0_0201_5% DDR_D_CA4 R11 CA3b H3 DDR_D_CS#1
DDR_C_CA5 CA4b CS1a DDR_C_CS#1 <8> DDR_D_CA5 CA4b CS1a DDR_D_CS#1 <8>
0_0201_5% P11 P11
CA5b R4 DDR_C_CS#0 CA5b R4 DDR_D_CS#0
2
CS0b CS0b
2
DDR_C_ODTA G2 R3 DDR_C_CS#1 DDR_D_ODTA G2 R3 DDR_D_CS#1

DDR_C_ODTB T2 ODTa CS1b DDR_D_ODTB T2 ODTa CS1b
ODTb ODTb
A1 C3 A1 C3
A2 DNU_1 DMI0a C10 +1.1V_MEM A2 DNU_1 DMI0a C10
+1.1V_MEM A11 DNU_2 DMI1a A11 DNU_2 DMI1a
A12 DNU_3 Y3 A12 DNU_3 Y3
B1 DNU_4 DMI0b Y10 B1 DNU_4 DMI0b Y10
B12 DNU_5 DMI1b B12 DNU_5 DMI1b
2
AA1 DNU_6 AA1 DNU_6
DNU_7 DNU_7
2
AA12 T11 DDR_DRAMRST#_R RD39 AA12 T11 DDR_DRAMRST#_R

DNU_8 RESET DDR_DRAMRST#_R <7,23> DNU_8 RESET
RD35 AB1 0_0201_5% AB1
0_0201_5% AB2 DNU_9 AB2 DNU_9
1
1
DNU_12 DDR_D_ODTB DNU_12

DDR_C_ODTB
DDR_C_D3_5 B2 AA2 DDR_C_D0_0 DDR_D_D3_0 B2 AA2 DDR_D_D1_1
<8> DDR_C_D3_5 DQ0a DQ0b DDR_C_D0_0 <8> <8> DDR_D_D3_0 DQ0a DQ0b DDR_D_D1_1 <8>
1
DDR_C_D3_6 C2 Y2 DDR_C_D0_2 DDR_D_D3_2 C2 Y2 DDR_D_D1_6
<8> DDR_C_D3_6 DDR_C_D0_2 <8> <8> DDR_D_D3_2 DDR_D_D1_6 <8>
1
DDR_C_D3_1 E2 DQ1a DQ1b V2 DDR_C_D0_1 RD40 @ DDR_D_D3_4 E2 DQ1a DQ1b V2 DDR_D_D1_7

<8> DDR_C_D3_1 DDR_C_D3_0 DQ2a DQ2b DDR_C_D0_4 DDR_C_D0_1 <8> <8> DDR_D_D3_4 DDR_D_D3_1 DQ2a DQ2b DDR_D_D1_4 DDR_D_D1_7 <8>
C RD36 @ F2 U2 0_0201_5% F2 U2 C
0_0201_5% F4 U4 F4 U4
E4 V4 E4 V4
2
DDR_C_D3_7 C4 DQ5a DQ5b Y4 DDR_C_D0_6 DDR_D_D3_6 C4 DQ5a DQ5b Y4 DDR_D_D1_3
2
DDR_C_D3_3 B4 DQ6a DQ6b AA4 DDR_C_D0_5 DDR_D_D3_7 B4 DQ6a DQ6b AA4 DDR_D_D1_2
B11 AA11 B11 AA11
C11 Y11 C11 Y11
E11 V11 E11 V11
<8> DDR_C_D2_4 DDR_C_D2_2 F11 DQ10a DQ10b U11 DDR_C_D1_2 DDR_C_D1_7 <8> ODT PD reserved -- CRB P.86 <8> DDR_D_D2_1 DDR_D_D2_0 F11 DQ10a DQ10b U11 DDR_D_D0_6 DDR_D_D0_5 <8>
ODT PD reserved -- CRB P.85 <8> DDR_C_D2_2 DDR_C_D2_5 F9 DQ11a DQ11b U9 DDR_C_D1_0 DDR_C_D1_2 <8> <8> DDR_D_D2_0 DDR_D_D2_5 F9 DQ11a DQ11b U9 DDR_D_D0_3 DDR_D_D0_6 <8>
E9 V9 E9 V9
C9 Y9 C9 Y9
B9 AA9 B9 AA9
<8> DDR_C_D2_6 DQ15a DQ15b DDR_C_D1_4 <8> <8> DDR_D_D2_6 DQ15a DQ15b DDR_D_D0_1 <8>
DDR_C_DQS3 D3 W3 DDR_C_DQS0 DDR_D_DQS3 D3 W3 DDR_D_DQS1

<8> DDR_C_DQS3 DDR_C_DQS#3 DQS0_ta DQS0_tb DDR_C_DQS#0 DDR_C_DQS0 <8> <8> DDR_D_DQS3 DDR_D_DQS#3 DQS0_ta DQS0_tb DDR_D_DQS#1 DDR_D_DQS1 <8>
E3 V3 DDR_C_DQS#0 <8> E3 V3 DDR_D_DQS#1 <8>
<8> DDR_C_DQS#3 DQS0_ca DQS0_cb <8> DDR_D_DQS#3 DQS0_ca DQS0_cb
DDR_C_DQS2 D10 W10 DDR_C_DQS1 DDR_D_DQS2 D10 W10 DDR_D_DQS0
<8> DDR_C_DQS2 DDR_C_DQS#2 DQS1_ta DQS1_tb DDR_C_DQS#1 DDR_C_DQS1 <8> <8> DDR_D_DQS2 DDR_D_DQS#2 DQS1_ta DQS1_tb DDR_D_DQS#0 DDR_D_DQS0 <8>
E10 V10 DDR_C_DQS#1 <8> E10 V10 DDR_D_DQS#0 <8>
<8> DDR_C_DQS#2 DQS1_ca DQS1_cb <8> DDR_D_DQS#2 DQS1_ca DQS1_cb
H9HCNNNBUUMLHR-NLM_FBGA200 H9HCNNNBUUMLHR-NLM_FBGA200
@ @
+1.8V_MEM UD3C +VDDQ_MEM UD3B
95mA 323mA +1.8V_MEM UD4C +VDDQ_MEM UD4B

F1 B3 A3 N4
F12 VDD1_1 VDDQ_1 B5 A10 VSS_1 VSS_30 N9
95mA 323mA
G4 B8 C1 N11 F1 B3 A3 N4
G9 VDD1_3 VDDQ_3 B10 C5 VSS_3 VSS_32 P1 F12 VDD1_1 VDDQ_1 B5 A10 VSS_1 VSS_30 N9
T4 VDD1_4 VDDQ_4 D1 C8 VSS_4 VSS_33 P3 G4 VDD1_2 VDDQ_2 B8 C1 VSS_2 VSS_31 N11
T9 VDD1_5 VDDQ_5 D5 C12 VSS_5 VSS_34 P10 G9 VDD1_3 VDDQ_3 B10 C5 VSS_3 VSS_32 P1
U1 VDD1_6 VDDQ_6 D8 D2 VSS_6 VSS_35 P12 T4 VDD1_4 VDDQ_4 D1 C8 VSS_4 VSS_33 P3
U12 VDD1_7 VDDQ_7 D12 D4 VSS_7 VSS_36 T1 T9 VDD1_5 VDDQ_5 D5 C12 VSS_5 VSS_34 P10
VDD1_8 VDDQ_8 F3 D9 VSS_8 VSS_37 T3 U1 VDD1_6 VDDQ_6 D8 D2 VSS_6 VSS_35 P12
+1.1V_MEM VDDQ_9 F10 D11 VSS_9 VSS_38 T5 U12 VDD1_7 VDDQ_7 D12 D4 VSS_7 VSS_36 T1
A4 VDDQ_10 U3 E1 VSS_10 VSS_39 T8 VDD1_8 VDDQ_8 F3 D9 VSS_8 VSS_37 T3
422mA VDD2_1 VDDQ_11 VSS_11 VSS_40 +1.1V_MEM VDDQ_9 VSS_9 VSS_38
A9 U10 E5 T10 F10 D11 T5
F5 VDD2_2 VDDQ_12 W1 E8 VSS_12 VSS_41 T12 A4 VDDQ_10 U3 E1 VSS_10 VSS_39 T8
422mA VDD2_1 VDDQ_11 VSS_11 VSS_40
F8 W5 E12 V1 A9 U10 E5 T10
H1 VDD2_4 VDDQ_14 W8 G1 VSS_14 VSS_43 V5 F5 VDD2_2 VDDQ_12 W1 E8 VSS_12 VSS_41 T12
H5 VDD2_5 VDDQ_15 W12 G3 VSS_15 VSS_44 V8 F8 VDD2_3 VDDQ_13 W5 E12 VSS_13 VSS_42 V1
H8 VDD2_6 VDDQ_16 AA3 G5 VSS_16 VSS_45 V12 H1 VDD2_4 VDDQ_14 W8 G1 VSS_14 VSS_43 V5
H12 VDD2_7 VDDQ_17 AA5 G8 VSS_17 VSS_46 W2 H5 VDD2_5 VDDQ_15 W12 G3 VSS_15 VSS_44 V8
K1 VDD2_8 VDDQ_18 AA8 G10 VSS_18 VSS_47 W4 H8 VDD2_6 VDDQ_16 AA3 G5 VSS_16 VSS_45 V12
K3 VDD2_9 VDDQ_19 AA10 G12 VSS_19 VSS_48 W9 H12 VDD2_7 VDDQ_17 AA5 G8 VSS_17 VSS_46 W2
K10 VDD2_10 VDDQ_20 J1 VSS_20 VSS_49 W11 K1 VDD2_8 VDDQ_18 AA8 G10 VSS_18 VSS_47 W4
K12 VDD2_11 J3 VSS_21 VSS_50 Y1 K3 VDD2_9 VDDQ_19 AA10 G12 VSS_19 VSS_48 W9
N1 VDD2_12 G11 J10 VSS_22 VSS_51 Y5 K10 VDD2_10 VDDQ_20 J1 VSS_20 VSS_49 W11
B VDD2_13 NC_1 VSS_23 VSS_52 VDD2_11 VSS_21 VSS_50 B
N3 K5 J12 Y8 K12 J3 Y1
N10 VDD2_14 NC_2 K8 K2 VSS_24 VSS_53 Y12 N1 VDD2_12 G11 J10 VSS_22 VSS_51 Y5
N12 VDD2_15 NC_3 N5 K4 VSS_25 VSS_54 AB3 N3 VDD2_13 NC_1 K5 J12 VSS_23 VSS_52 Y8
R1 VDD2_16 NC_4 N8 K9 VSS_26 VSS_55 AB5 N10 VDD2_14 NC_2 K8 K2 VSS_24 VSS_53 Y12
R5 VDD2_17 NC_5 K11 VSS_27 VSS_56 AB8 N12 VDD2_15 NC_3 N5 K4 VSS_25 VSS_54 AB3
R8 VDD2_18 N2 VSS_28 VSS_57 AB10 R1 VDD2_16 NC_4 N8 K9 VSS_26 VSS_55 AB5
R12 VDD2_19 VSS_29 VSS_58 R5 VDD2_17 NC_5 K11 VSS_27 VSS_56 AB8
U5 VDD2_20 R8 VDD2_18 N2 VSS_28 VSS_57 AB10
U8 VDD2_21 H9HCNNNBUUMLHR-NLM_FBGA200 R12 VDD2_19 VSS_29 VSS_58
AB4 VDD2_22 @ U5 VDD2_20
AB9 VDD2_23 U8 VDD2_21 H9HCNNNBUUMLHR-NLM_FBGA200
VDD2_24 VDD2_22
AB4 @
AB9 VDD2_23
H9HCNNNBUUMLHR-NLM_FBGA200 VDD2_24
@
H9HCNNNBUUMLHR-NLM_FBGA200
@
UD3 UD4
+1.8V_MEM +1.1V_MEM +VDDQ_MEM +1.8V_MEM +1.1V_MEM +VDDQ_MEM
1
1
CD29 CD30 CD31 CD32 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 CD41 CD42 CD13 CD14 CD15 CD16 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
2
2
+1.8V_MEM +1.1V_MEM +VDDQ_MEM +1.1V_MEM +VDDQ_MEM
+1.8V_MEM
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD10 CD11 CD316 CD5 CD6 CD317 CD85 CD86 CD318 CD3 CD4 CD320 CD83 CD84 CD321
1 1 1
RF@ RF@ RF@ CD8 CD9 CD319 RF@ RF@
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
RF@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
100P_0201_50V8J
10U_0402_6.3V6M
10U_0402_6.3V6M
2 2 2
A A

Deciphered Date
P024 - LPDDR4/x Channel C/D
0.1 (X00)
5 4 3 2 1
A B C D E
1 1
LPDDR4X@ RD41 1 2 0_0201_5% RD400

<58> MEM_PG 0.6V_VDDQ_PG <87>
RD42 1 2 0_0201_5% 0.6V_VDDQ_EN 1 2
1.1V_MEM_PG <86> 0.6V_VDDQ_EN_P <87>
1M_0201_5%
1
0.1U_0402_25V6
0_0402_5%
@ RD300
@ CD309
1
2 2
1.1V_MEM_EN <78,86>
2
+0.6V_VDDQP:LPDDR4X
2
2
RD43 +1.1V_MEM:LPDDR4
LPDDR4X@ 0_0201_5%
1
0.6V_VDDQ_EN
+0.6V_VDDQ LPDDR4X@
+VDDQ_MEM
2
RD45
RD44 0_1206_5%
LPDDR4@ 0_0201_5% 1 2
1 +1.1V_MEM LPDDR4@
RD46
0_1206_5%
1 2
RD43 RD45 RD44 RD46

LPDDR4(1.1V) : @ @
LPDDR4X(1.1v&0.6V): @ @
3 3
4 4

P025 - LPDDR4&4X BOM OPTION
A B C D E
5 4 3 2 1
D D
C C
B B
A A

P026 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P027 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P028 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P029 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P030 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P031 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P032 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P033 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P034 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P035 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P036 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P037 - Reserve
5 4 3 2 1
5 4 3 2 1
LCD VDD POWER eDP Conn

+3VALW +LCDVDD +LCDVDD
+3VALW eDP* Bit Rates 8.1 Gb/s (HBR3)
5
U7
1 +LCDVDD_R 1
R24
2
1
C1 1 2 0.1U_0201_10V6K EDP_TXP0_C In TCON side , RX Equalizat i oni s CTLE + DFE
1 <6> EDP_TXP0
C37
IN OUT
2 0.01_0603_1%
C41
10U_0402_6.3V6M
DFE=Decision feedback equalizer
2
1U_0201_6.3V6M
ENVDD 4
GND
3
2
<6> EDP_TXN0
C2 1 2 0.1U_0201_10V6K EDP_TXN0_C
CTLE=Cont i nuous Ti me Li near Equali zer
EN OC LCD_TST
<58> LCD_TST
SY6288C20AAC_SOT23-5
+LCDVDD EDP_HPD
<6,58> EDP_HPD
<58> SOLC SOLC
D1 BIA_PWM 1 EMI@ 2 BIA_PWM_R

1
2 LV1 BLM15PX221SN1D_2P
<58> LCD_VCC_TEST_EN
C38
1 ENVDD 0.1U_0201_10V6K
D 2 TOUCH_SCREEN_PD#_R D
<11> TOUCH_SCREEN_PD#_R TS_INT#
<6> ENVDD_PCH 3 <6> TS_INT#
1
C3 1 2 0.1U_0201_10V6K EDP_TXP1_C TS_RST#
2 <6> EDP_TXP1 <10> TS_RST#
R25
BAT54CW_SOT323-3 90.9K_0201_1% C760 @ TS_DET
EDP_TXN1_C <6> TS_DET
0.33U_0201_6.3V6M C4 1 2 0.1U_0201_10V6K
1 <6> EDP_TXN1
2
1 2 DBC_EN_R
<10> DBC_EN
RH622 0_0201_5%
eDP BackLight Power

JEDP1
C5 1 2 0.1U_0201_10V6K EDP_TXP2_C BIA_PWM_R 1 2 LCD_TST
<6> EDP_TXP2 1 2
DISPOFF# 3 4
SOLC 5 3 4 6
EDP_TXN2_C EDP_HPD 5 6 +LCDVDD
C6 1 2 0.1U_0201_10V6K 7 8
<6> EDP_TXN2 7 8 EDP_AUXN_C
B+ +INV_PWR_SRC 9 10
11 9 10 12 EDP_AUXP_C
13 11 12 14
R87 1 @ 2 0.01_0603_1% 15 13 14 16 EDP_TXP0_C
17 15 16 18 EDP_TXN0_C
S TR AO6405 1P TSOP6 F3 19 17 18 20
+INV_PWR_SRC_R 1 2 21 19 20 22 EDP_TXP1_C
D
6 23 21 22 24 EDP_TXN1_C
60mil 60mil
S
4 5 3A_32V_F0603FA3000V032T 25 23 24 26
2 27 25 26 28 EDP_TXP2_C
Q15 1 29 27 28 30 EDP_TXN2_C
29 30
1
1 G 31 32
TS_DET 33 31 32 34 EDP_TXP3_C
3
C1224 R231 I2C_0_SDA_R 35 33 34 36 EDP_TXN3_C

0.1U_0402_25V7K 1M_0402_5% I2C_0_SCL_R 37 35 36 38
0.1U_0402_25V6
10U_0603_25V6M
2 EDP_TXP3_C TS_INT# 37 38 DBC_EN_R
@
<6> EDP_TXP3 C7 1 2 0.1U_0201_10V6K 39 40
1
2
39 40
1
TS_RST# 41 42 TOUCH_SCREEN_PD#_R
C1223
EN_INVPWR_R 41 42
C87
C8 1 2 0.1U_0201_10V6K EDP_TXN3_C 43 44
<6> EDP_TXN3 +INV_PWR_SRC
2
Power Power
1
R931
R932
45 46
+3VS_TS Power Power
R30
1
47 48
GND GND
2.1K_0402_1%
2.1K_0402_1%
100K_0402_5% 49 50
51 GND GND 52
2
53 GND GND 54
55 GND GND 56
2
57 GND GND 58
59 GND GND 60
<58> EN_INVPWR GND GND
6
3
C 61 62 C
GND GND
1
63 64
R29 2 2 1 5 65 PTH PTH 66
100K_0201_5% R633 0_0201_5% C9 1 2 0.1U_0201_10V6K EDP_AUXP_C 67 PTH PTH 68
<6> EDP_AUXP PTH PTH
Q16A
L2N7002DW1T1G_SC88-6 Q16B
2
4
L2N7002DW1T1G_SC88-6 C10 1 2 0.1U_0201_10V6K EDP_AUXN_C I-PEX_20698-042E-01
<6> EDP_AUXN
CONN@
BackLight PWM Control

For factory test request
DBC_EN_R
TP@ PAD~50 TP115 1
LCD_TST
D2 TP@ PAD~50 TP116 1
2 1 EDP_HPD
<58> PANEL_BKEN_EC +INV_PWR_SRC TP@ PAD~50 TP117
+LCDVDD +3VS_TS TP@ PAD~50 TP118 1 SOLC
1 DISPOFF# TP@ PAD~50 TP119 1 DISPOFF#
DISPOFF# <11> BIA_PWM_R
TP@ PAD~50 TP120 1
2
I2C_0_SDA_R
<6,10> PANEL_BKLEN 3 TP@ PAD~50 TP121 1
I2C_0_SCL_R
0.1U_0201_10V6K
10U_0402_6.3V6M
33P_0402_50V8J
R31 TP@ PAD~50 TP122 1
2 TOUCH_SCREEN_PD#_R
0.1U_0201_10V6K
15P_0201_50V8J
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1U_0603_25V6K
100K_0201_5%
1 1 1 1 1 1 1 1 TP@ PAD~50 TP123 1
1
1 TS_INT#
BAT54CW_SOT323-3 C761 @ TP@ PAD~50 TP124
TS_RST#
C46
C47
C48
C451
C452
C58 @EMI@
C52
C49
C50
0.33U_0201_6.3V6M TP@ PAD~50 TP125 1
1
1 TP@ PAD~50 TP126 1 +3VS_TS
2
2 2 2 2 2 2 2 2 TP@ PAD~50 TP127 1 +LCDVDD
D3 TP@ PAD~50 TP128 1 +INV_PWR_SRC
2 RF@
<58> BIA_PWM_EC
1 BIA_PWM
1
<6> EDP_BIA_PWM 3 1
R32 @
10K_0201_5% C750
BAT54CW_SOT323-3 680P_0402_50V7K
2
2
B +3VS_TS B
TS_DET R237 1 2 100K_0201_5%

B+ I2C_0_SCL_R R239 1 2 2.2K_0201_1%
I2C_0_SDA_R
For BL_PWR_SRC & LCDVDD monitor +LCDVDD
TS_RST#
TS_INT#
R238
R245
1
1
2 2.2K_0201_1%
2 100K_0201_5%
R288 1 2 100K_0201_5%
E
3
2
B QV18 I2C_0_SCL_R R1015 2 1 0_0201_5%
1
LMBT3906N3T5G_SOT883-3 I2C_0_SDA_R I2C_0_SCL <10>

R1016 2 1 0_0201_5% I2C_0_SDA <10>
1
+INV_PWR_SRC R658
C
1
R621 100K_0201_5%
10K_0201_5%
2
TS_DET
2
2
47K_0201_5%
2 1 PANEL_PWRGD R651 2 1 0_0201_5% TS_INT#

PANEL_MONITOR <58>
R627
DV11 TS_RST#
2200P_0402_50V7K
0.1U_0201_25V6K
0.1U_0201_10V6K
1
1
200K_0201_5%
TOUCH_SCREEN_PD#_R
1
1M_0201_5%
1
1
CV633
C419
R624
C418
1
R677
C
BL_PWR_MONITOR
2
2
2
B 2
2
E
3
QV19
LMBT3904N3T5G_SOT883-3
+3VALW
D465
D466
D471
D486
2
2
R652 2 1 0_0201_5%
PESD5V0H1BSF_SOD962-2-2
E
3
2
B QV20
1
1
+LCDVDD
EMI@
EMI@
EMI@
EMI@
C
1
R622
10K_0201_5%
A A
2
2
47K_0201_5%
2 1
R628
DV12
2200P_0402_50V7K
0.1U_0201_25V6K
1
1
200K_0201_5%
1
CV651
C420
R623
C
LCDVDD_MONITOR
2
2
2
B
2
E
3
QV21

Deciphered Date
P038 - eDP,Touch Screen
0.1 (X00)
5 4 3 2 1
5 4 3 2 1
For factory test request

+3VS +3V_ALS
Camera
TP@PAD~50 TP134
TP@PAD~50 TP135
1
1
ISH_I2C_1_SCL_R
ISH_I2C_1_SDA_R
1
F5
2 ALS
0.5A_65V_T0603FF0500TM DMIC
TP@PAD~50 TP138 1 ALS_ALERT#_R
R6116 1 2 0_0201_5% ISH_I2C_1_SCL_R
<10,63> ISH_I2C_1_SCL ISH_I2C_1_SDA_R
R6117 1 2 0_0201_5%
<10,63> ISH_I2C_1_SDA CAM_DET#_R
R6208 1 2 0_0201_5%
<10> CAM_DET#
TP@PAD~50 TP142 1
+CAM_PWR
TP@PAD~50 TP143 1 USB20_P9
D +DVDD_MIC <12> USB20_P9 D
TP@PAD~50 TP144 1 USB20_N9
+3V_ALS <12> USB20_N9
DMIC_CLK12 JUFC1
<56> DMIC_CLK12
TP@PAD~50 TP145 1 CAM_DET#_R DMIC_DATA12 1 2
<56> DMIC_DATA12 1 2
3 4
+P_VCC 3 4
5 6
P_SENSOR_PWR_SAVE# 5 6 ISH_I2C_1_SCL_R
7 8
P_DET# 9 7 8 10 ISH_I2C_1_SDA_R
9 10
11 12
+3VS P_INT# 11 12
13 14
<10> P_INT# S_BIO 13 14
15 16
+1.8VS R6223 @ 0_0201_5% +P_VCC 15 16
1 2 17 18
F6 @ 17 18 DMIC_CLK12
19 20
R6224 1 @ 2 0_0201_5% +P_VCC_R 1 2 21 19 20 22 DMIC_DATA12
23 21 22 24
0.5A_65V_T0603FF0500TM 25 23 24 26
+DVDD_MIC 25 26
27 28
27 28
29 30
+3V_ALS 29 30 ISH_I2C_1_SDA_R
31 32
31 32 ISH_I2C_1_SCL_R
33 34
R6118 0_0201_5% ALS_ALERT#_R 33 34
1 2 35 36
S_BIO <10> ALS_ALERT# 35 36 USB20_N9
TP@PAD~50 TP158 1 37 38
USB20_P9 P_DET# 37 38 USB20_P9
39 40
USB20_N9 <10> P_DET# P_SENSOR_PWR_SAVE# CAM_DET#_R 39 40
<10> P_SENSOR_PWR_SAVE# 41 42
41 42
AZ5B75-01B.R7G_CSP0603P2Y2
43 44
B+_CAM Power Power
45 46
+CAM_PWR Power Power
1
D485 D484
C 47 48 C
GND GND
49 50
GND GND
51 52
53 GND GND 54
B+_CAM_R B+_CAM GND GND
55 56
EMI@ EMI@ RV75 57 GND GND 58
1 2 59 GND GND 60
2
GND GND
61 62
2A_65V_T0603FF2000TM GND GND
63 64
PTH PTH
65 66
PTH PTH
67 68
PTH PTH
Need check FPC layout I-PEX_20698-042E-01

CONN@
+1.8VS
10K_0201_5% ALS_ALERT#
Intel DMIC for WOV function
2 1 R6157
Bypass cap close to CONN

+3VS
1.8V LDO on middle board
+DVDD_MIC +CAM_PWR
B B+ B+_CAM_R +3V_PRIM +DVDD_MIC B
0.1U_0201_10V6K
0.1U_0201_10V6K
F1
QZ10
1U_0201_6.3V6M
1 2
SI3457BDV-T1-E3_TSOP6~D
1 1 1
C1540
C1539
0.5A_65V_T0603FF0500TM
40mil
D
CC17
6
40mil
S
4 5
2 2 2 2
1 1
1
C3314 R5867 R655 1 @ 2 0_0402_5% DMIC_DATA12

<10> PCH_DMIC_DATA12
3
1000P_0402_50V7K 270K_0402_5%
2
1
C3315 R634 1 @ 2 0_0402_5% DMIC_CLK12

<10> PCH_DMIC_CLK12
2
0.1U_0201_25V6K
2
1
R5868
47K_0402_5%
2
1
D
IRCAM_EN 2
<58> IRCAM_EN 2N7002KW_SOT323-3
G
QZ11
A A
S
3

P039 - UF Camera,MIC,ALS
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P040 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P041 - Reserve
5 4 3 2 1
5 4 3 2 1
+5VALW_L_TBT
1 Close pin 1,2 1 Close pin 25

+TBT_VBUS_L CPD7 CPD8
+TBT_VBUS_L_PD 10U_0402_10V6M 22U_0603_10V6M
TP110 2 2
TP@
PAD~D
1
EMI@ 1 2 LT11
HCB2012KF-800T50_2P
EMI@ 1 2 LT13
2200P_0201_25V7K
2200P_0201_25V7K
0.01U_0201_25V6K
100P_0201_50V8J
0.1U_0201_25V6K
10U_0603_25V6M
1U_0402_25V6K
HCB2012KF-800T50_2P +TBT_VBUS_L_PD +VIN_3V3_L_TBT +CHG_VIN_20V
1M_0201_1%
1000P_0201_50V7K
100P_0201_50V8J
1
CT34
0.1U_0201_25V6K
1U_0402_25V6K
1U_0402_25V6K
1 1 1 1 1 2 1 1 1 1 1 1
EMI@ CT338
EMI@ CT339
EMI@ CT340
EMI@ CT341
EMI@ CT318
EMI@ CT319
EMI@ CT342
EMI@ CT343
EMI@ CT344
EMI@ CT345
EMI@ CT346
@EMI@ RT150
Close pin 3,4 1 1 Close pin 13,14 1 Close pin 5 2 Close pin 11,12 2
2 2 2 2 2 1 2 2 2 2 2 2
EMI@
CPD42 CPD49 CPD5 CPD40 CPD47
2
D 1U_0402_25V6K 1U_0402_25V6K 10U_0402_10V6M 10U_0603_25V6M 10U_0603_25V6M D
2 2 2 1 1
+3VALW +VIN_3V3_L_TBT
RPD84 1 2 0.01_0402_1%
PD_L_GPIO17
PD_L_GPIO16 +VCC3V3_TBT_L_LDO +VCC1V8_TBT_L_LDO
+VCC3V3_TBT_L_LDO
UPD5 @
1 Close pin 9 Close pin 35
48
49
1 PD_EE_CS#_L
+CHG_VIN_20V UPD1 +TBT_VBUS_L_PD 1 8
CPD4 CPD6 PD_EE_MISO_L 2 CS# VCC 7 PD_HOLD#_L
GPIO16(PEXT1)
GPIO17(PEXT2)
10U_0402_10V6M 4.7U_0402_6.3V6M PD_EE_WP#_L DO(IO1) HOLD#(IO3) PD_EE_CLK_L
20V/3.5A 11
PP_HV1_1 VBUS2_1
3 3.5A 3
WP#(IO2) CLK
6
+5VALW_L_TBT 12 4 2 2 4 5 PD_EE_MOSI_L
+5VALW +5VALW_L_TBT PP_HV1_2 VBUS2_2 GND DI(IO0)
1 13 W25Q64FVSSIG_SO8
PP_HV2_1 VBUS1_1
5V/3.5A 2
PP_HV2_2 VBUS1_2
14
1
RPD121 1 2 0.01_1206_1%
+VIN_3V3_L_TBT 25 D461 @ESD@
PP1_CABLE
C1_CC1
24 TBT_L_CC1
TBT_L_CC2 TBT_L_CC1 <43>
NSR20F30NXT5G_DSN2-2 Reserve SO8 footprint for PD debug conn
5 26 TBT_L_CC2 <43>
VIN_3V3 C1_CC2
2
3V/25 mA 9 +VCC3V3_TBT_L_LDO
+VCC3V3_TBT_L_LDO LDO_3V3 PD_L_GPIO18
35 50 (36) PD_EE_MISO:
+VCC1V8_TBT_L_LDO LDO_1V8 C1_USB_P(GPIO18) PD_L_GPIO19
53
C1_USB_N(GPIO19) RPD11 1 2 3.3K_0201_5% PD_EE_CS#_L
BUSPOWER ADCIN1_L_PD 6 RPD12 1 2 3.3K_0201_5% PD_EE_MISO_L '0' - SPI-less
ADCIN2_L_PD ADCIN1 I2C1_PD_L_CLK RPD13 3.3K_0201_5% PD_HOLD#_L
I2C Address 10 27 1 2
ADCIN2 I2C1_SCL I2C1_PD_L_DAT PD_EE_WP#_L
I2C1_SDA
28 I2C Port 1 to System Control RPD14 1 2 3.3K_0201_5% '1' - SPI
29 I2C1_PD_L_INT# RPD181 1 @ 2 10K_0201_5% PD_EE_MISO_L
I2C1_IRQ
<50> PD_L_USB_MUX1_EN
RPD187 1 2 0_0201_5% PD_L_USB_MUX1_EN_R 16 32 I2C2_PD_L_CLK
RPD124 1 2 0_0201_5% TCP0_RST#_R GPIO0 I2C2_SCL I2C2_PD_L_DAT +VCC3V3_TBT_L_LDO +VCC3V3_TBT_L_LDO
<46> TCP0_RST# 17 33 I2C Port 2 to Thunderbolt Controller
PD_L_GPIO2 18 GPIO1 I2C2_SDA 34 I2C2_PD_L_INT#
RPD126 1 2 0_0201_5% PD_TCP0_LS_EN_R 30 GPIO2 I2C2_IRQ UPD3
<47> PD_TCP0_LS_EN PD_L_GPIO4 HPD1(GPIO3) PD_EE_CS#_L
31 1 8
RPD194 1 @ 2 0_0201_5% I2C3_PD_L_CLK 21 GPIO4 36 PD_EE_MISO_L PD_EE_MISO_L 2 /CS VCC 7 PD_HOLD#_L
GPIO5 SPI_MISO(GPIO8) DO(IO1) /HOLD(IO3) 1
RPD142 1 @ 2 0_0201_5% I2C3_PD_L_DAT 22 37 PD_EE_MOSI_L PD_EE_WP#_L 3 6 PD_EE_CLK_L
I2C3 on TGL RPD155 1 @ 2 0_0201_5% I2C3_PD_L_INT# 23 GPIO6 SPI_MOSI(GPIO9) 38 PD_EE_CLK_L 4 /WP(IO2) CLK 5 PD_EE_MOSI_L CPD1
C GPIO7 SPI_CLK(GPIO10) GND DI(IO0) C
<44,82> PD_L_R_PROCHOT#
RPD185 1 2 0_0201_5% PD_L_PROCHOT# 40 39 PD_EE_CS#_L 9 0.1U_0201_10V6K
MUX_L_FLIP# RPD127 1 2 0_0201_5% MUX_L_FLIP#_R 41 GPIO12 SPI_SS(GPIO11) thermal pad 2
<50> MUX_L_FLIP# GPIO13
<50> PD_L_DDM_MUX1_EN
RPD123 1 2 0_0201_5% PD_L_DDM_MUX1_EN_R 42 +VCC3V3_TBT_L_LDO W25Q64FVZPIG_WSON8_6X5
RPD130 1 2 0_0201_5% RT_L_FORCE_PWR 43 GPIO14(PWM) 44 HRESET_L_PD RPD88 1 2 0_0201_5%
<13,44,46,48> RT_FORCE_PWR GPIO15(PWM) HRESET
<44> PD_R_SLAVE_IN RPD174 1 @ 2 0_0201_5% PD_L_SINK_ARB_MASTER_OUT 54 JDB1
RPD172 1 2 0_0201_5% PD_L_SINK_ARB_SLAVE_IN 55 GPIO20 1
<44> PD_L_SLAVE_IN GPIO21 PD_L_DRAIN1 1 PD_EE_CLK_L
Left PD Controller SPI FLASH
8 2
+VCC3V3_TBT_L_LDO DRAIN1_1 15 2 3 PD_EE_MOSI_L
DRAIN1_2 19 3 4 PD_EE_MISO_L
20 DRAIN1_3 58 4 5 PD_EE_CS#_L
45 GND_1 DRAIN1_4 5 6
46 GND_4 7 PD_L_DRAIN2 6 7 I2C1_PD_L_CLK TBT_L_CC1 CPD3 1 2 220P_0201_25V6K
47 GND_5 DRAIN2_1 52 7 8 I2C1_PD_L_DAT TBT_L_CC2 CPD2 1 2 220P_0201_25V6K
51 GND_6 DRAIN2_2 56 8 9 I2C2_PD_L_CLK
59 GND_2 DRAIN2_3 57 9 10 I2C2_PD_L_DAT
GND_3 DRAIN2_4 10
SA0000C3N00 @ 11
10K_0201_5% 2 @ 1 RPD183 PD_L_PROCHOT# GND1 12
TPS65987DDHRSHR_VQFN56_7X7
GND2 I2C1_PD_L_CLK RPD163 1 2 0_0201_5%
MUX_L_FLIP# I2C1_PD_L_DAT UPD_SMBCLK_Q <44,50,58>
10K_0201_5% 2 1 RPD129 RPD164 1 2 0_0201_5%
I2C1_PD_L_INT# UPD_SMBDAT_Q <44,50,58>
ACES_50521-01041-P01 RPD17 1 2 0_0201_5%
10K_0201_5% 2 1 RPD170 TCP0_RST# CONN@ UPD_L_SMBINT# <58>
I2C2_PD_L_CLK RPD21 1 2 0_0201_5%
I2C2_PD_L_DAT SML1_SMBCLK <9,44,46,48>
RPD22 1 2 0_0201_5%
I2C2_PD_L_INT# SML1_SMBDATA <9,44,46,48>
RPD112 1 2 0_0201_5%
PD_L_SINK_ARB_SLAVE_IN TBT_I2C_INT# <11,44,46,48>
10K_0201_5% 2 1 RPD189
100K_0201_5% 2 1 RPD190 PD_L_USB_MUX1_EN_R
100K_0201_5% 2 1 RPD191 PD_L_DDM_MUX1_EN_R
1M_0201_5% 2 @ 1 RPD169 TCP0_RST#
100K_0201_5% 2 @ 1 RPD128 MUX_L_FLIP#

BUSPOWER Config
BP_NoWait value 0.7~0.78 I2C Address Divider:010b
+VCC3V3_TBT_L_LDO
Reserved for debug
+VCC3V3_TBT_L_LDO
B B
1
PD_L_GPIO18 @ RPD204 1 2 0_0201_5% PD_L_GPIO19
PD_L_GPIO17 @ RPD139 1 2 0_0201_5% PD_L_GPIO2 RPD92
R1
1
PD_L_GPIO4 @ RPD141 1 2 0_0201_5% PD_L_GPIO16 100K_0201_1%
RPD90
R1 100K_0201_1%
2
ADCIN1_L_PD
2
ADCIN2_L_PD
1
RPD91
R2
1
300K_0201_1%
RPD100
R2 100K_0201_1%
2
2
A A

P042 - TYPE-C Port L_PD
5 4 3 2 1
5 4 3 2 1
LEFT Type-C Connector +TBT_VBUS_L
+TBT_VBUS_L
+TBT_VBUS_L +TBT_VBUS_L
2
CT347
AZ4520-01F.R7G_DFN1610P2E2
10U_0603_25V6M
1
JUSBC1
1
A1 B12
CT30 1 2 0.22U_0201_6.3V6M TBT_0_TTX_C_DRX_P1 GND GND
<46> TBT_0_TTX_RD_DRX_P1 TBT_0_TTX_C_DRX_P1 TBT_0_TRX_RD_DTX_P1
A2 B11 TBT_0_TRX_RD_DTX_P1 <46>
D TBT_0_TTX_C_DRX_N1 SSTXP1 SSRXP1 TBT_0_TRX_RD_DTX_N1 D
D459 ESD@
A3 B10 TBT_0_TRX_RD_DTX_N1 <46>
SSTXN1 SSRXN1
CT310 1 2 A4 B9 2 1 CT313
2
0.1U_0201_25V6K VBUS VBUS 0.1U_0201_25V6K
TBT_L_CC1 A5 B8 TBT_0_SBU2
TBT_0_TTX_C_DRX_N1 <42> TBT_L_CC1 CC1 SBU2 TBT_0_SBU2 <46>
<46> TBT_0_TTX_RD_DRX_N1 CT31 1 2 0.22U_0201_6.3V6M
SW_USB20_1_P8_R A6 B7 SW_USB20_2_N8_R
SW_USB20_1_N8_R A7 DP1 DN2 B6 SW_USB20_2_P8_R
DN1 DP2
TBT_0_SBU1 A8 B5 TBT_L_CC2
<46> TBT_0_SBU1 SBU1 CC2 TBT_L_CC2 <42>
CT312 1 2 A9 B4 2 1 CT311
CT32 1 2 0.22U_0201_6.3V6M TBT_0_TTX_C_DRX_P2 0.1U_0201_25V6K VBUS VBUS 0.1U_0201_25V6K
<46> TBT_0_TTX_RD_DRX_P2 TBT_0_TRX_RD_DTX_N2 TBT_0_TTX_C_DRX_N2
A10 B3
<46> TBT_0_TRX_RD_DTX_N2 TBT_0_TRX_RD_DTX_P2 SSRXN2 SSTXN2 TBT_0_TTX_C_DRX_P2
A11 B2
<46> TBT_0_TRX_RD_DTX_P2 SSRXP2 SSTXP2
A12 B1
GND GND
CT33 1 2 0.22U_0201_6.3V6M TBT_0_TTX_C_DRX_N2 1 4

<46> TBT_0_TTX_RD_DRX_N2 GND GND
2 5
3 GND GND 6
GND GND
DEREN_560Q10-002H
CONN@
TBT_0_SBU1 TBT_0_SBU2
1
C C
2 2
RT118 @ RT119 @
@ CT206 1M_0201_1% @ CT207 1M_0201_1%
100P_0201_50V8J 100P_0201_50V8J
1 1
2
R93 1 @ 2 0_0402_5%~D
D75 ESD@ D76 ESD@ D407 ESD@ D408 ESD@

ML6 EMI@
1 2 SW_USB20_1_N8_R TBT_0_TTX_RD_DRX_P1 1 2 1 2 TBT_0_TTX_RD_DRX_P2 SW_USB20_1_P8_R 1 2 1 2 SW_USB20_1_N8_R
<50> SW_USB20_1_N8
4 3 SW_USB20_1_P8_R PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2 AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2

<50> SW_USB20_1_P8
HCM1012GH900BP_4P
TBT_0_TTX_RD_DRX_N1 1 2 1 2 TBT_0_TTX_RD_DRX_N2 SW_USB20_2_P8_R 1 2 1 2 SW_USB20_2_N8_R
R94 1 @ 2 0_0402_5%~D
PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2 AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2

D79 ESD@ D80 ESD@
D411 ESD@ D412 ESD@
R95 1 @ 2 0_0402_5%~D TBT_0_TRX_RD_DTX_P1 1 2 1 2 TBT_0_TRX_RD_DTX_P2
TBT_L_CC1 1 2 1 2 TBT_0_SBU1
ML7 EMI@ PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2

1 2 SW_USB20_2_N8_R D81 ESD@ D82 ESD@ AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2
<50> SW_USB20_2_N8
B TBT_0_TRX_RD_DTX_N1 1 2 1 2 TBT_0_TRX_RD_DTX_N2 D413 ESD@ D414 ESD@ B
4 3 SW_USB20_2_P8_R
<50> SW_USB20_2_P8 TBT_0_SBU2 TBT_L_CC2
1 2 1 2
HCM1012GH900BP_4P PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
R121 1 @ 2 0_0402_5%~D AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2

ESD Diodes should be located as
close as possible to USBC.
A A

P043 - TYPE-C Conn L
5 4 3 2 1
5 4 3 2 1
+5VALWB_R_TBT
+TBT_VBUS_R +TBT_VBUS_R_PD
TP111
1 Close pin 1,2 1 Close pin 25
TP@
PAD~D CPD17 CPD18
1
EMI@ 1 2 LT12 10U_0402_10V6M 22U_0603_10V6M
HCB2012KF-800T50_2P 2 2
EMI@ 1 2 LT14
2200P_0201_25V7K
2200P_0201_25V7K
0.01U_0201_25V6K
100P_0201_50V8J
0.1U_0201_25V6K
10U_0603_25V6M
1U_0402_25V6K
HCB2012KF-800T50_2P
1M_0201_1%
1000P_0201_50V7K
100P_0201_50V8J
1
CT37
0.1U_0201_25V6K
1U_0402_25V6K
1U_0402_25V6K
1 1 1 1 1 2 1 1 1 1 1 1
EMI@ C4227
EMI@ CT348
EMI@ CT349
EMI@ CT350
EMI@ CT351
EMI@ CT325
EMI@ CT352
EMI@ CT353
EMI@ CT354
EMI@ CT355
EMI@ CT356
@EMI@ RT151
+TBT_VBUS_R_PD
+VIN_3V3_R_TBT +CHG_VIN_20V
EMI@
2 2 2 2 2 1 2 2 2 2 2 2 Close pin 3,4 Close pin 13,14
1 1
2
CPD41 CPD51 1 Close pin 5 2 Close pin 11,12 2
1U_0402_25V6K 1U_0402_25V6K
2 2 CP10 CPD19 CPD48
10U_0402_10V6M 10U_0603_25V6M 10U_0603_25V6M
D 2 1 1 D
PD_R_GPIO17
PD_R_GPIO16
+VIN_3V3_R_TBT
+3VALW +VCC3V3_TBT_R_LDO +VCC1V8_TBT_R_LDO
48
49
+CHG_VIN_20V UPD2 +TBT_VBUS_R_PD
RPD93 1 2 0.01_0402_1%
GPIO16(PEXT1)
GPIO17(PEXT2)
20V/3.5A 11 3 3.5A +VCC3V3_TBT_R_LDO
PP_HV1_1 VBUS2_1 1 Close pin 9 1 Close pin 35
+5VALWB_R_TBT 12 4
PP_HV1_2 VBUS2_2 CPD14 CPD16 UPD6 @
1 13 10U_0402_10V6M 4.7U_0402_6.3V6M PD_EE_CS#_R 1 8
PP_HV2_1 VBUS1_1 2 2 PD_EE_MISO_R CS# VCC PD_HOLD#_R
5V/3.5A 2 14 2 7
1
PP_HV2_2 VBUS1_2 PD_EE_WP#_R 3 DO(IO1) HOLD#(IO3) 6 PD_EE_CLK_R
+VIN_3V3_R_TBT 25 D462 @ESD@ 4 WP#(IO2) CLK 5 PD_EE_MOSI_R
PP1_CABLE 24 TBT_R_CC1 NSR20F30NXT5G_DSN2-2 GND DI(IO0)
+5VALWB +5VALWB_R_TBT C1_CC1 TBT_R_CC2 TBT_R_CC1 <45>
5 26 W25Q64FVSSIG_SO8
VIN_3V3 C1_CC2 TBT_R_CC2 <45>
2
3V/25 mA 9
+VCC3V3_TBT_R_LDO LDO_3V3 PD_R_GPIO18
RPD96 1 2 0.01_1206_1% 35 50
+VCC1V8_TBT_R_LDO LDO_1V8 C1_USB_P(GPIO18)
C1_USB_N(GPIO19)
53 PD_R_GPIO19 Reserve SO8 footprint for PD debug conn
BUSPOWER ADCIN1_R_PD 6
ADCIN2_R_PD 10 ADCIN1 27 I2C1_PD_R_CLK
I2C Address
ADCIN2 I2C1_SCL I2C1_PD_R_DAT
28 I2C Port 1 to System Control
I2C1_SDA 29 I2C1_PD_R_INT#
I2C1_IRQ +VCC3V3_TBT_R_LDO
<50> PD_R_USB_MUX1_EN RPD188 1 2 0_0201_5% PD_R_USB_MUX1_EN_R 16 32 I2C2_PD_R_CLK
(36) PD_EE_MISO:
RPD132 1 2 0_0201_5% TCP2_RST#_R 17 GPIO0 I2C2_SCL 33 I2C2_PD_R_DAT
<48> TCP2_RST# I2C Port 2 to Thunderbolt Controller
PD_R_GPIO2 18 GPIO1 I2C2_SDA 34 I2C2_PD_R_INT# RPD59 1 2 3.3K_0201_5% PD_EE_CS#_R
RPD134 1 2 0_0201_5% PD_TCP2_LS_EN_R 30 GPIO2 I2C2_IRQ RPD60 1 2 3.3K_0201_5% PD_EE_MISO_R '0' - SPI-less
<49> PD_TCP2_LS_EN PD_R_GPIO4 HPD1(GPIO3) PD_HOLD#_R
31 RPD61 1 2 3.3K_0201_5%
2 0_0201_5% I2C3_PD_R_CLK GPIO4 PD_EE_MISO_R PD_EE_WP#_R
RPD199 1 @ 21 36 RPD62 1 2 3.3K_0201_5% '1' - SPI
RPD146 1 @ 2 0_0201_5% I2C3_PD_R_DAT 22 GPIO5 SPI_MISO(GPIO8) 37 PD_EE_MOSI_R RPD182 1 @ 2 10K_0201_5% PD_EE_MISO_R
I2C3 on TGL RPD131 1 @ 2 0_0201_5% I2C3_PD_R_INT# 23 GPIO6 SPI_MOSI(GPIO9) 38 PD_EE_CLK_R
RPD186 1 2 0_0201_5% PD_R_PROCHOT# 40 GPIO7 SPI_CLK(GPIO10) 39 PD_EE_CS#_R
<42,82> PD_L_R_PROCHOT# MUX_R_FLIP# GPIO12 SPI_SS(GPIO11)
<50> MUX_R_FLIP#
RPD135 1 2 0_0201_5% MUX_R_FLIP#_R 41
RPD157 1 2 0_0201_5% PD_R_DDM_MUX1_EN_R 42 GPIO13 +VCC3V3_TBT_R_LDO +VCC3V3_TBT_R_LDO
<50> PD_R_DDM_MUX1_EN GPIO14(PWM)
<13,42,46,48> RT_FORCE_PWR RPD138 1 2 0_0201_5% RT_R_FORCE_PWR 43 44 HRESET_R_PD RPD97 1 2 0_0201_5%
C GPIO15(PWM) HRESET C
<42> PD_L_SLAVE_IN
RPD171 1 2 0_0201_5% PD_R_SINK_ARB_MASTER_OUT 54 UPD4
RPD173 1 @ 2 0_0201_5% PD_R_SINK_ARB_SLAVE_IN 55 GPIO20 PD_EE_CS#_R 1 8
<42> PD_R_SLAVE_IN GPIO21 PD_R_DRAIN1 PD_EE_MISO_R /CS VCC PD_HOLD#_R
8 2 7 1
+VCC3V3_TBT_R_LDO DRAIN1_1 15 PD_EE_WP#_R 3 DO(IO1) /HOLD(IO3) 6 PD_EE_CLK_R
DRAIN1_2 19 4 /WP(IO2) CLK 5 PD_EE_MOSI_R CPD11
20 DRAIN1_3 58 GND DI(IO0) 9 0.1U_0201_10V6K
45 GND_1 DRAIN1_4 thermal pad 2
46 GND_4 7 PD_R_DRAIN2 W25Q64FVZPIG_WSON8_6X5
47 GND_5 DRAIN2_1 52 +VCC3V3_TBT_R_LDO
51 GND_6 DRAIN2_2 56
59 GND_2 DRAIN2_3 57 JDB2
GND_3 DRAIN2_4
Right PD Controller SPI FLASH
1
1 2 PD_EE_CLK_R
10K_0201_5% 2 @ 1 RPD184 PD_R_PROCHOT# SA0000C3N00 @ 2 3 PD_EE_MOSI_R
3 4 PD_EE_MISO_R
TPS65987DDHRSHR_VQFN56_7X7
10K_0201_5% 2 1 RPD137 MUX_R_FLIP# 4 5 PD_EE_CS#_R TBT_R_CC1 CPD12 1 2 220P_0201_25V6K
5 6 TBT_R_CC2 CPD13 1 2 220P_0201_25V6K
10K_0201_5% 2 1 RPD168 TCP2_RST# 6 7 I2C1_PD_R_CLK
7 8 I2C1_PD_R_DAT
8 9 I2C2_PD_R_CLK
9 10 I2C2_PD_R_DAT
10
100K_0201_5% 2 1 RPD193 PD_R_USB_MUX1_EN_R
11 I2C1_PD_R_CLK RPD165 1 2 0_0201_5%
PD_R_DDM_MUX1_EN_R GND1 I2C1_PD_R_DAT UPD_SMBCLK_Q <42,50,58>
100K_0201_5% 2 1 RPD192 12 RPD166 1 2 0_0201_5%
GND2 I2C1_PD_R_INT# UPD_SMBDAT_Q <42,50,58>
RPD109 1 2 0_0201_5%
100K_0201_5% 2 1 RPD177 PD_R_SINK_ARB_SLAVE_IN UPD_R_SMBINT# <58>
ACES_50521-01041-P01 I2C2_PD_R_CLK RPD105 1 2 0_0201_5%
TCP2_RST# I2C2_PD_R_DAT SML1_SMBCLK <9,42,46,48>
1M_0201_5% 2 @ 1 RPD167 CONN@ RPD106 1 2 0_0201_5%
I2C2_PD_R_INT# SML1_SMBDATA <9,42,46,48>
RPD113 1 2 0_0201_5%
MUX_R_FLIP# TBT_I2C_INT# <11,42,46,48>
100K_0201_5% 2 @ 1 RPD136
Reserved for debug

PD_R_GPIO18
PD_R_GPIO17
@ RPD205 1
@ RPD144 1
2 0_0201_5%
2 0_0201_5%
PD_R_GPIO19
PD_R_GPIO2
BUSPOWER Config
PD_R_GPIO4 @ RPD147 1 2 0_0201_5% PD_R_GPIO16
BP_NoWait value 0.7~0.78 I2C Address Divider:000b
B B
+VCC3V3_TBT_R_LDO
+VCC3V3_TBT_R_LDO
1
RPD102
R1
1
100K_0201_1%
RPD99
R1 100K_0201_1%
ADCIN1_R_PD 2
2
ADCIN2_R_PD
1
RPD101
R2
1
300K_0201_1%
RPD89
R2 10K_0201_1%
2
2
A A

P044 - TYPE-C Port R_PD
5 4 3 2 1
A
RIGHT Type-C Connector

+TBT_VBUS_R +TBT_VBUS_R
+TBT_VBUS_R +TBT_VBUS_R
JUSBC2
A1 B12
1
2 0.22U_0201_6.3V6M TBT_2_TTX_C_DRX_P1 GND GND
AZ4520-01F.R7G_DFN1610P2E2
CT38 1 CT357
<48> TBT_2_TTX_RD_DRX_P1 TBT_2_TTX_C_DRX_P1 TBT_2_TRX_RD_DTX_P1
A2 B11 10U_0603_25V6M
TBT_2_TRX_RD_DTX_P1 <48>
1
TBT_2_TTX_C_DRX_N1 A3 SSTXP1 SSRXP1 B10 TBT_2_TRX_RD_DTX_N1 EMI@
TBT_2_TRX_RD_DTX_N1 <48>
2
SSTXN1 SSRXN1
CT314 1 2 A4 B9 2 1 CT317
VBUS VBUS
D460 ESD@
0.1U_0201_25V6K 0.1U_0201_25V6K
TBT_R_CC1 A5 B8 TBT_2_SBU2
<44> TBT_R_CC1 CC1 SBU2 TBT_2_SBU2 <48>
<48> TBT_2_TTX_RD_DRX_N1 CT39 1 2 0.22U_0201_6.3V6M TBT_2_TTX_C_DRX_N1
2
SW_USB20_1_P4_R A6 B7 SW_USB20_2_N4_R
SW_USB20_1_N4_R A7 DP1 DN2 B6 SW_USB20_2_P4_R
DN1 DP2
TBT_2_SBU1 A8 B5 TBT_R_CC2
<48> TBT_2_SBU1 SBU1 CC2 TBT_R_CC2 <44>
CT316 1 2 A9 B4 2 1 CT315
CT40 1 2 0.22U_0201_6.3V6M TBT_2_TTX_C_DRX_P2 0.1U_0201_25V6K VBUS VBUS 0.1U_0201_25V6K
<48> TBT_2_TTX_RD_DRX_P2 TBT_2_TRX_RD_DTX_N2 TBT_2_TTX_C_DRX_N2
A10 B3
<48> TBT_2_TRX_RD_DTX_N2 TBT_2_TRX_RD_DTX_P2 SSRXN2 SSTXN2 TBT_2_TTX_C_DRX_P2
A11 B2
<48> TBT_2_TRX_RD_DTX_P2 SSRXP2 SSTXP2
A12 B1
GND GND
<48> TBT_2_TTX_RD_DRX_N2
CT41 1 2 0.22U_0201_6.3V6M TBT_2_TTX_C_DRX_N2 1 4
2 GND GND 5
3 GND GND 6
GND GND
DEREN_560Q10-002H
CONN@
TBT_2_SBU1 TBT_2_SBU2
1
2 2
RT120 @ RT121 @
@ CT306 1M_0201_1% @ CT307 1M_0201_1%
100P_0201_50V8J 100P_0201_50V8J
1 1
2
R6083 1 @ 2 0_0402_5%~D

ML16 EMI@
1 2 SW_USB20_1_N4_R TBT_2_TTX_RD_DRX_P1 1 2 1 2 TBT_2_TTX_RD_DRX_P2 SW_USB20_1_P4_R 1 2 1 2 SW_USB20_1_N4_R
<50> SW_USB20_1_N4
1
4 3 SW_USB20_1_P4_R PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2 AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2
1
<50> SW_USB20_1_P4
HCM1012GH900BP_4P
TBT_2_TTX_RD_DRX_N1 1 2 1 2 TBT_2_TTX_RD_DRX_N2 SW_USB20_2_P4_R 1 2 1 2 SW_USB20_2_N4_R
R6084 1 @ 2 0_0402_5%~D
PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2 AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2

D87 ESD@ D88 ESD@
D420 ESD@ D419 ESD@
R6085 1 @ 2 0_0402_5%~D TBT_2_TRX_RD_DTX_P1 1 2 1 2 TBT_2_TRX_RD_DTX_P2
TBT_R_CC1 1 2 1 2 TBT_2_SBU1
ML17 EMI@ PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2

1 2 SW_USB20_2_N4_R D89 ESD@ D90 ESD@ AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2
<50> SW_USB20_2_N4
TBT_2_TRX_RD_DTX_N1 1 2 1 2 TBT_2_TRX_RD_DTX_N2 D422 ESD@ D421 ESD@
4 3 SW_USB20_2_P4_R
<50> SW_USB20_2_P4 TBT_2_SBU2 TBT_R_CC2
1 2 1 2
HCM1012GH900BP_4P PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
R6086 1 @ 2 0_0402_5%~D AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2

ESD Diodes should be located as
close as possible to USBC.

P045 - TYPE-C Conn R
A
5 4 3 2 1
URT1D @
<6> TBT_0_TTX_DRX_P0 CT1 1 2 0.22U_0201_6.3V6M TBT_0_TTX_C_RD_DRX_P0 J1

TBT PORTS J12
TBT_0_TTX_C_RD_DRX_N0 ASSRXp1 BSSRXp1 TBT_0_TRX_RD_DTX_P1 <43>
<6> TBT_0_TTX_DRX_N0 CT2 1 2 0.22U_0201_6.3V6M J2 J11
ASSRXn1 BSSRXn1 TBT_0_TRX_RD_DTX_N1 <43>
Port B - TypeC Side

Port A - Host Side
CT3 1 2 0.22U_0201_6.3V6M TBT_0_TRX_C_RD_DTX_P0 G1 G12
<6> TBT_0_TRX_DTX_P0 TBT_0_TRX_C_RD_DTX_N0 ASSTXp1 BSSTXp1 TBT_0_TTX_RD_DRX_P1 <43>
CT4 1 2 0.22U_0201_6.3V6M G2 G11
<6> TBT_0_TRX_DTX_N0 ASSTXn1 BSSTXn1 TBT_0_TTX_RD_DRX_N1 <43>
CT5 1 2 0.22U_0201_6.3V6M TBT_0_TTX_C_RD_DRX_P1 C1 C12
<6> TBT_0_TTX_DRX_P1 TBT_0_TTX_C_RD_DRX_N1 ASSRXp2 BSSRXp2 TBT_0_TRX_RD_DTX_P2 <43>
CT6 1 2 0.22U_0201_6.3V6M C2 C11
<6> TBT_0_TTX_DRX_N1 ASSRXn2 BSSRXn2 TBT_0_TRX_RD_DTX_N2 <43>
CT7 1 2 0.22U_0201_6.3V6M TBT_0_TRX_C_RD_DTX_P1 E1 E12
D <6> TBT_0_TRX_DTX_P1 TBT_0_TRX_C_RD_DTX_N1 ASSTXp2 BSSTXp2 TBT_0_TTX_RD_DRX_P2 <43> D
CT8 1 2 0.22U_0201_6.3V6M E2 E11
RT164 1 2 0_0201_5% TBT_0_LSX_TX_R M7 M10
<6> TBT_0_LSX_TX TBT_0_LSX_RX_R PA_LSTX_SBU1 BSBU1 TBT_0_SBU1 <43>
RT165 1 2 0_0201_5% L7 L10
<6> TBT_0_LSX_RX PA_LSRX_SBU2 BSBU2 TBT_0_SBU2 <43>
RT112 1 2 0_0201_5% TBT_0_AUXP_R L8
<6> TBT_0_AUXP TBT_0_AUXN_R PA_AUX_P
RT113 1 2 0_0201_5% M8
<6> TBT_0_AUXN PA_AUX_N
TBT_0_LSX_TX_R BURNSIDE-BRIDGE_BGA105
TBT_0_LSX_RX_R
2
@ RT2 RT1 @
1M_0201_1% 1M_0201_1%
1
URT1A @
+3.3V_TBT_L_FLASH_R +3.3V_TBT_L_LC
TBT_L_ROM_DI C6 C9 I2C_RT_L_SCL
RT176 1 @ 2 0_0201_5% TBT_L_ROM_DO B4 EE_DI I2C_SCL E7 I2C_RT_L_SDA
FLASH
TBT_L_ROM_CS# EE_DO I2C_SDA I2C_RT_L_INT#
B6 A10
+VCC3V3_TBT_L_LDO TBT_L_ROM_CLK C7 EE_CS# I2C_INT B10 RT_FORCE_PWR
EE_CLK FORCE_PWR TBT_L_FLASH_BUSY# RT_FORCE_PWR <13,42,44,48>
A9
MISC &
POC GPIO
RT169 1 @ 2 0_0201_5% FLASH_BUSY# B9 TBT_L_GPIO_5
POC_GPIO_5 A8 TBT_L_GPIO_6
TBT_L_JTAG_TDI POC_GPIO_6 TBT_L_PERST#
C
RT168 1 2 0_0201_5%
+3.3V_TBT_L
Follow CSLP TBT_L_JTAG_TMS
TBT_L_JTAG_TCK
A3
C3
B5
TDI
TMS
DEBUG PERST#
SMBUS_SCL
B8
A7
B7
TBT_L_SMBCLK
TBT_L_SMBDAT
C
JTAG
TBT_L_JTAG_TDO C5 TCK SMBUS_SDA A4 TBT_L_FLASH_SHARE_EN
+3V_PRIM TDO POC_GPIO_10 A5 TBT_L_FLASH_MSTR_SLV
Intel suggest i on POC_GPIO_11
A6 TBT_L_GPIO_12 I2C_RT_L_SCL RT124 1 2 0_0201_5%
POC_GPIO_12 I2C_RT_L_SDA SML1_SMBCLK <9,42,44,48>
RT186 1 @ 2 0_0201_5% L3 POC_GPIO_12 have iPU RT125 1 2 0_0201_5% SML1_SMBDATA <9,42,44,48> PCH
TP6A4 1 TBT_L_THERMDA M11 NC_L3 I2C_RT_L_INT# RT152 1 2 0_0201_5%
THERMDA TBT_I2C_INT# <11,42,44,48>
A12: TP@
PAD~D M12
DB connect to GND. B2
TEST_EDM TBT_L_SMBCLK RT159 1 @ 2 0_0201_5%
FUSE_VQPS_64 SML0_SMBCLK <9,48>
+3.3V_TBT_L_FLASH_R +3.3V_TBT_L_FLASH BB is NC. RESET#
L11 TBT_L_RESET# RT174 1 2 0_0201_5%
TCP0_RST# <42>
TBT_L_SMBDAT RT160 1 @ 2 0_0201_5% SML0_SMBDATA <9,48>
DLB@ A11
DT1 RT101 1 2 0_0201_5% A12 MONDC L9 TBT_L_XTAL_25_IN RT53 1 2 0_0201_5% TBT_L_XTAL_25_IN_R
DEBUG
Main
2 1 L12 NC_A12 XTAL_25_IN M9 TBT_L_XTAL_25_OUT RT54 1 2 0_0201_5% TBT_L_XTAL_25_OUT_R TBT_L_SMBCLK RT193 1 2 100K_0201_5%
RT7 MONDC_SVR XTAL_25_OUT TBT_L_SMBDAT RT194 100K_0201_5%
1 2
1N4148WS-L_SOD323-2 1 2 TBT_L_TEST_PWR_GOOD B3 L5 TBT_L_RSENSE RT19 1 2 4.75K_0402_0.5%
B11 TEST_PWR_GOOD RSENSE L4 TBT_L_RBIAS SMBUS:
100_0201_1%
B3 PD 100 ohm TEST_EN RBIAS No support Vpro
A1 Intel recommended PD 100K
+3.3V_TBT_L_FLASH ATEST_P
A2
A1,A2 SDS,CRB is NC ATEST_N Reserve for TBT RTD3 Support
JDB3
1 BURNSIDE-BRIDGE_BGA105 TBT_L_PERST# RT59 1 2 0_0201_5%
1 TBT_L_ROM_CLK PCH_TBT_PERST# <10,48>
2
2 TBT_L_ROM_DI RT162 1 @
3 2 0_0201_5%
3 TBT_L_ROM_DO PCH_PLTRST#_EC <11,48,52,66,67,70,79>
4 RT ref p.5 XTAL Recommended
7 4 5 TBT_L_ROM_CS#
8 GND1 5 6
FW2500025Z by Pericom
GND2 6 XRCGB25M000F3L12R0 by Murata
JXT_FP241AH-006GAAM
CONN@ Suggest adding GND shield across (L11) DG_P1_RST#:
Crystal and 18pF caps for better
RFI. For PD based systems, DG_P1_RST# should be output from PD.
B YT1 +3.3V_TBT_L For TCPC based systems, DG_P1_RST# should be output from SOC/EC. B
+3.3V_TBT_L_FLASH 4 3 TBT_L_XTAL_25_OUT_R
GND_1 OUT
TBT_L_ROM_CS# RT20 1 2 2.2K_0201_1% TBT_L_XTAL_25_IN_R 1 2 TBT_L_GPIO_5 RT172 1 @ 2 10K_0201_5%
TBT_L_ROM_DO IN GND_2 (B10) FORCE_PWR:Connect to PCH for FW update
RT21 1 2 2.2K_0201_1% 1
TBT_L_ROM_WP# RT22 1 2 3.32K_0201_1% 25MHZ_20PF_FW2500025Z TBT_L_FLASH_SHARE_EN RT13 1 @ 2 10K_0201_5%
TBT_L_ROM_HOLD# 1 '0' - by default
RT23 1 2 3.32K_0201_1% CT43
CT42 27P_0201_25V8 TBT_L_FLASH_MSTR_SLV RT16 1 @ 2 10K_0201_5%
27P_0201_25V8 2 '1' - for debug only
2 TBT_L_GPIO_12 RT18 1 @ 2 10K_0201_5%
+3.3V_TBT_L_FLASH
+3VS
UTS1
TBT_L_ROM_CS# 1 8
TBT_L_ROM_DO /CS VCC TBT_L_ROM_HOLD# TBT_L_GPIO_6 RT12 1 10K_0201_5%
2 7 2 (A9) DG_FLASH_BUSY#:conenction to PU
TBT_L_ROM_WP# 3 DO(IO1) /HOLD(IO3) 6 TBT_L_ROM_CLK
4 /WP(IO2) CLK 5 TBT_L_ROM_DI DVT1 change to 1MB : SA00008DZ00
GND DI(IO0) 9 +3V_PRIM
thermal pad
W25Q64FVZPIG_WSON8_6X5 (A4) DG_FLSH_SHARE_EN (iPU):
TBT_L_JTAG_TDI TP@ 1 TP45 PAD~32 RT_FORCE_PWR RT109 1 @ 2 10K_0201_5%
Debug TBT_L_JTAG_TCK
TBT_L_JTAG_TMS TP@ 1 TP47 PAD~32

TP@ 1 TP46 PAD~32 TBT_L_FLASH_BUSY# RT8 1 2 10K_0201_5%
'0' - Flash isn't shared. 1 Flash per Re-timer. Can be left NC.
'1' - Flash is shared between 2 Re-timers.

+3.3V_TBT_L_FLASH TBT_L_JTAG_TDO TP@ 1 TP48 PAD~32 RT_FORCE_PWR RT6 1 2 10K_0201_5%
UTS3 @ (A5) DG_FLSH_MSTR_SLV (iPU):
TBT_L_ROM_CS# 1 8 +3.3V_TBT_L_LC TBT_L_FLASH_BUSY# RT9 1 @ 2 10K_0201_5%
TBT_L_ROM_DO CS# VCC TBT_L_ROM_HOLD#
2 7
TBT_L_ROM_WP# 3 DO(IO1) HOLD#(IO3) 6 TBT_L_ROM_CLK TBT_L_GPIO_5 RT10 1 2 10K_0201_5% '0' - Set Re-timer to be Slave on shared flash SPI I/F.
4 WP#(IO2) CLK 5 TBT_L_ROM_DI
GND DI(IO0) TBT_L_GPIO_6 RT11 1 @ 2 10K_0201_5% '1' - Set Re-timer to be Master on shared flash SPI I/F.
W25Q64FVSSIG_SO8 TBT_L_JTAG_TDI RT63 1 2 10K_0201_5%
TBT_L_JTAG_TCK RT64 1 2 10K_0201_5% TBT_L_FLASH_SHARE_EN RT14 1 2 10K_0201_5%
TBT_L_JTAG_TMS RT65 1 2 10K_0201_5%
A
TBT_L_JTAG_TDO TBT_L_FLASH_MSTR_SLV
(A8) DG_POC_GPIO6: A
RT97 1 2 10K_0201_5% RT15 1 @ 2 10K_0201_5%
Reserve SO8 footprint for BB debug conn TBT_L_GPIO_12 RT17 1 @ 2 10K_0201_5% '0' -Reserved for debug
For BBR-A0 PLL Issue Workaround reserved '1' -Indication to S0 state for Re-timer
+3.3V_TBT_L
TBT_L_JTAG_TCK RT218 1 @ 2 10K_0201_5%

P046 - TYPE-C TBT_BB L_TCSS
5 4 3 2 1
5 4 3 2 1
+3.3V_TBT_L_LC +3.3V_TBT_L_ANA
CT57 +3.3V_TBT_L_SVR +3.3V_TBT_L_SX

2.2U_0201_6.3V6M
CT58
2.2U_0201_6.3V6M
1 1
CT365
47U_0603_6.3V6M
CT63
1U_0201_6.3V6K
CT62
1U_0201_6.3V6K
CT61
1U_0201_6.3V6K
2 2
D 1 1 1 1 D
J5: +3.3V_TBT_L
+3.3V_TBT_L_ANA URT1B @ DB connect to +3.3V_TBT_L.
BB is NC. 2 2 2 2
Place near Pin E5 Place near Pin L2 +3.3V_TBT_L_LC L2 E6 +3.3V_TBT_L_SX 1 2 0.01_0402_1%
VCC3P3_ANA VCC3P3_SX RT180
+0.9V_TBT_L_LVR +0.9V_TBT_L_LC +0.9V_TBT_L_SVR E5 M4 +3.3V_TBT_L_SVR 1 2 0.01_0402_1%
VCC3P3_LC VCC3P3_SVR_1 M5 RT181 +3.3VA_TBT_L
VCC3P3_SVR_2 +3.3V_TBT_L_DB
F6 J5 1 2
VCC0P9_SVR_ANA_1 VCC3P3_SVR_3
CT59
2.2U_0201_6.3V6M
G6 J7 RT203 DLB@ 0_0201_5% +TBT_L_SVR_IND

VCC0P9_SVR_ANA_2 VCC3P3A Place near Pin M4, M5, J5 Place near Pin E6
CT60
2.2U_0201_6.3V6M
CT200
10U_0402_10V6M
E3 L1 GND share with Pin M2, M3 3.3v @ 80mA
Power
1 VCC0P9_SVR_1 SVR_IND_1
1 1 G3
VCC0P9_SVR_2 SVR_IND_2
M1
connect via inductor to VCC0P9_SVR 3.3v @ 290mA
E9 M2
2 +0.9V_TBT_L_LC G9 VCC0P9_SVR_PB_ANA_1 SVR_VSS_1 M3
2 2 VCC0P9_SVR_PB_ANA_2 SVR_VSS_2
+0.9V_TBT_L_LVR J3 +3.3V_TBT_L +3.3VA_TBT_L
VCC0P9_LC
L6
Place near Pin J3 M6
VCC0P9_LVR
J6 RT122 1 DLB@ 2 0_0201_5% RT79 1 2 0.01_0402_1%
Place near Pin L6,M6 VCC0P9_LVR_SENSE NC_J6
CT303
10U_0402_10V6M
CT302
18P_0201_25V8J
CT64
1U_0201_6.3V6K
J6:
BURNSIDE-BRIDGE_BGA105 DB connect to GND.
BB is NC. 1 1 1
@
C C
2 2 2
+TBT_L_SVR_IND +0.9V_TBT_L_SVR
LT8
1 2
0.68UH_MLV-YT10NR68N-M1L_2.7A_30%
CT49
CT50
CT51
CT52
CT53
CT54
CT55
CT56
1 1 1 1 1 1 1 1 Place near Pin J7
@ @ @ 3.3v @ 50mA
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
18P_0201_25V8J
47U_0603_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
2 2 2 2 2 2 2 2
Place near Pin F6,G6,E3,G3,E9,G9

GND share with Pin M2, M3
0.9v @ 850mA
BB ref sch Rev 1.4 change to CAP Place near Pin F6,E3,E9
G3,G6,G9 CAP change to NC
+3VALW
URT1C
B B1 F12 B
1 VSS_ANA_1 VSS_ANA_12
B12 G7
CT361 +3VALW
3.3v @ 370mA D1
VSS_ANA_2 VSS_ANA_13
H1
1U_0201_6.3V6K UT1 +3.3V_TBT_L VSS_ANA_3 VSS_ANA_14
D2 H2
2 EMI@ VSS_ANA_4 VSS_ANA_15
D11 H11
<42> PD_TCP0_LS_EN
RT83 1 2 0_0201_5%
1
2
VIN_1 VOUT_1
7
8
+3.3V_TBT_L_B
LT3
1 2
BLM18KG331SN1D_2P
D12
F1
VSS_ANA_5
VSS_ANA_6 GND VSS_ANA_16
VSS_ANA_17
H12
J9
VIN_2 VOUT_2 VSS_ANA_7 VSS_ANA_18
F2 K1
RT84 1 @ 2 0_0201_5% 3.3V_TBT_L_EN 3 6 CT362 1 2 470P_0402_50V7K +3.3V_TBT_L F7 VSS_ANA_8 VSS_ANA_19 K2
<11,16,49,58> SIO_SLP_SUS# ON CT VSS_ANA_9 VSS_ANA_20
F9 K11
F11 K12
4 2
+3VALW VBIAS
5 G5
GND_1 9 CT363 VSS_1 F5
GND_2 0.1U_0201_10V6K VSS_2
F3
3.3V_TBT_L_EN RT178 1 2 100K_0201_5% 1 VSS_3
RT179 1 @ 2 10K_0201_5% AOZ1336DI_DFN8_2X2 BURNSIDE-BRIDGE_BGA105
@
BB ref sch p.6 note

DG_P1_PWR_GATE_EN:
For PD based systems, DG_P1_PWR_GATE_EN should be output from PD.
For TCPC based systems, DG_P1_PWR_GATE_EN should be output from SOC/EC.

A A

P047 - TYPE-C TBT_BB L_PWR,GND
5 4 3 2 1
5 4 3 2 1
URT2D @
<6> TBT_2_TTX_DRX_P0 CT9 1 2 0.22U_0201_6.3V6M TBT_2_TTX_C_RD_DRX_P0 J1

TBT PORTS J12
TBT_2_TTX_C_RD_DRX_N0 ASSRXp1 BSSRXp1 TBT_2_TRX_RD_DTX_P1 <45>
CT10 1 2 0.22U_0201_6.3V6M J2 J11
Port B - TypeC Side

Port A - Host Side
CT11 1 2 0.22U_0201_6.3V6M TBT_2_TRX_C_RD_DTX_P0 G1 G12
CT12 1 2 0.22U_0201_6.3V6M G2 G11
CT13 1 2 0.22U_0201_6.3V6M TBT_2_TTX_C_RD_DRX_P1 C1 C12
<6> TBT_2_TTX_DRX_P1 TBT_2_TTX_C_RD_DRX_N1 ASSRXp2 BSSRXp2 TBT_2_TRX_RD_DTX_P2 <45>
CT14 1 2 0.22U_0201_6.3V6M C2 C11
D TBT_2_TRX_C_RD_DTX_P1 D
CT15 1 2 0.22U_0201_6.3V6M E1 E12
CT16 1 2 0.22U_0201_6.3V6M E2 E11
RT167 1 2 0_0201_5% TBT_2_LSX_TX_R M7 M10
<6> TBT_2_LSX_TX TBT_2_LSX_RX_R PA_LSTX_SBU1 BSBU1 TBT_2_SBU1 <45>
RT166 1 2 0_0201_5% L7 L10
<6> TBT_2_LSX_RX PA_LSRX_SBU2 BSBU2 TBT_2_SBU2 <45>
RT116 1 2 0_0201_5% TBT_2_AUXP_R L8
<6> TBT_2_AUXP TBT_2_AUXN_R PA_AUX_P
RT117 1 2 0_0201_5% M8
<6> TBT_2_AUXN PA_AUX_N
BURNSIDE-BRIDGE_BGA105
TBT_2_LSX_TX_R
TBT_2_LSX_RX_R
2
@ RT4 RT3 @
1M_0201_1% 1M_0201_1%
1
+3.3V_TBT_R_FLASH_R +3.3V_TBT_R_LC
RT177 1 @ 2 0_0201_5% URT2A @
+VCC3V3_TBT_R_LDO TBT_R_ROM_DI C6 C9 I2C_RT_R_SCL

TBT_R_ROM_DO EE_DI I2C_SCL I2C_RT_R_SDA
B4 E7
FLASH
RT170 1 @ 2 0_0201_5% TBT_R_ROM_CS# B6 EE_DO I2C_SDA A10 I2C_RT_R_INT#
TBT_R_ROM_CLK C7 EE_CS# I2C_INT B10
EE_CLK FORCE_PWR TBT_R_FLASH_BUSY# RT_FORCE_PWR <13,42,44,46>
+3.3V_TBT_R A9
Follow CSLP
MISC &
POC GPIO
FLASH_BUSY# B9 TBT_R_GPIO_5
RT171 0_0201_5% POC_GPIO_5 TBT_R_GPIO_6
1 2 A8
C TBT_R_JTAG_TDI POC_GPIO_6 TBT_R_PERST# C
+3V_PRIM
Intel suggest i on
TBT_R_JTAG_TMS
TBT_R_JTAG_TCK
A3
C3
B5
TDI
TMS
DEBUG PERST#
SMBUS_SCL
B8
A7
B7
TBT_R_SMBCLK
TBT_R_SMBDAT
JTAG
RT187 1 @ 2 0_0201_5% TBT_R_JTAG_TDO C5 TCK SMBUS_SDA A4 TBT_R_FLASH_SHARE_EN
TDO POC_GPIO_10 TBT_R_FLASH_MSTR_SLV
A5
POC_GPIO_11 A6 TBT_R_GPIO_12 I2C_RT_R_SCL RT197 1 2 0_0201_5%
POC_GPIO_12 I2C_RT_R_SDA SML1_SMBCLK <9,42,44,46>
L3 POC_GPIO_12 have iPU RT198 1 2 0_0201_5% SML1_SMBDATA <9,42,44,46> PCH
TP6A5 1 TBT_R_THERMDA M11 NC_L3 I2C_RT_R_INT# RT199 1 2 0_0201_5%
THERMDA TBT_I2C_INT# <11,42,44,46>
A12: TP@
PAD~D M12
+3.3V_TBT_R_FLASH_R +3.3V_TBT_R_FLASH DB connect to GND. B2 TEST_EDM TBT_R_SMBCLK RT200 1 @ 2 0_0201_5%
FUSE_VQPS_64 SML0_SMBCLK <9,46>
BB is NC. RESET#
L11 TBT_R_RESET# RT175 1 2 0_0201_5%
TCP2_RST# <44>
TBT_R_SMBDAT RT201 1 @ 2 0_0201_5% SML0_SMBDATA <9,46>
DT2 A11
2 1 RT102 1 DLB@ 2 0_0201_5% A12 MONDC L9 TBT_R_XTAL_25_IN RT55 1 2 0_0201_5% TBT_R_XTAL_25_IN_R
DEBUG
Main
NC_A12 XTAL_25_IN TBT_R_XTAL_25_OUT RT56 1 TBT_R_XTAL_25_OUT_R TBT_R_SMBCLK
L12 M9 2 0_0201_5% RT196 1 2 100K_0201_5%
1N4148WS-L_SOD323-2 RT30 MONDC_SVR XTAL_25_OUT TBT_R_SMBDAT RT195 1 2 100K_0201_5%
1 2 TBT_R_TEST_PWR_GOOD B3 L5 TBT_R_RSENSE RT50 1 2 4.75K_0402_0.5%
B11 TEST_PWR_GOOD RSENSE L4 TBT_R_RBIAS SMBUS:
+3.3V_TBT_R_FLASH 100_0201_1%
B3 PD 100 ohm TEST_EN RBIAS No support Vpro
A1 Intel recommended PD 100K
JDB4 A2 ATEST_P
1
A1,A2 SDS,CRB is NC ATEST_N Reserve for TBT RTD3 Support
1 2 TBT_R_ROM_CLK
2 3 TBT_R_ROM_DI BURNSIDE-BRIDGE_BGA105 TBT_R_PERST# RT62 1 2 0_0201_5%
3 TBT_R_ROM_DO PCH_TBT_PERST# <10,46>
4
7 4 5 TBT_R_ROM_CS# RT163 1 @ 2 0_0201_5%
GND1 5 RT ref p.5 XTAL Recommended PCH_PLTRST#_EC <11,46,52,66,67,70,79>
8 6
GND2 6 FW2500025Z by Pericom
JXT_FP241AH-006GAAM XRCGB25M000F3L12R0 by Murata
CONN@
Suggest adding GND shield across (L11) DG_P1_RST#:
Crystal and 18pF caps for better
RFI. For PD based systems, DG_P1_RST# should be output from PD.
+3.3V_TBT_R_FLASH YT2
B 4 3 TBT_R_XTAL_25_OUT_R For TCPC based systems, DG_P1_RST# should be output from SOC/EC. B
TBT_R_ROM_CS# RT42 1 2 2.2K_0201_1% GND_1 OUT +3.3V_TBT_R
TBT_R_ROM_DO RT43 1 2 2.2K_0201_1% TBT_R_XTAL_25_IN_R 1 2
TBT_R_ROM_WP# RT44 1 2 3.32K_0201_1% IN GND_2
TBT_R_ROM_HOLD# 1 TBT_R_GPIO_5
(B10) FORCE_PWR:Connect to PCH for FW update
RT45 1 2 3.32K_0201_1% 1 25MHZ_20PF_FW2500025Z RT173 1 @ 2 10K_0201_5%
CT44
CT45 27P_0201_25V8 TBT_R_FLASH_SHARE_EN RT37 1 @ 2 10K_0201_5% '0' - by default
27P_0201_25V8 2
+3.3V_TBT_R_FLASH 2 TBT_R_FLASH_MSTR_SLV RT38 1 @ 2 10K_0201_5% '1' - for debug only
UTS2
TBT_R_ROM_CS# 1 8 TBT_R_GPIO_12 RT41 1 @ 2 10K_0201_5%
TBT_R_ROM_DO 2 /CS VCC 7 TBT_R_ROM_HOLD#
TBT_R_ROM_WP# 3 DO(IO1) /HOLD(IO3) 6 TBT_R_ROM_CLK +3V_PRIM
4 /WP(IO2) CLK 5 TBT_R_ROM_DI DVT1 change to 1MB : SA00008DZ00
GND DI(IO0)
9 (A9) DG_FLASH_BUSY#:conenction to PU
thermal pad
W25Q64FVZPIG_WSON8_6X5
TBT_R_FLASH_BUSY# RT189 1 2 10K_0201_5%
(A4) DG_FLSH_SHARE_EN (iPU):

+3VS
TBT_R_JTAG_TDI TP@ 1 TP49 PAD~32
'0' - Flash isn't shared. 1 Flash per Re-timer. Can be left NC.
TBT_R_ROM_CS#
TBT_R_ROM_DO
1
2
UTS4
CS#
@
VCC
8
7
+3.3V_TBT_R_FLASH
TBT_R_ROM_HOLD#
Debug TBT_R_JTAG_TCK TP@ 1 TP51 PAD~32
TBT_R_JTAG_TMS TP@ 1 TP50 PAD~32

TBT_R_GPIO_6 RT35 1 2 10K_0201_5%
'1' - Flash is shared between 2 Re-timers.
TBT_R_ROM_WP# 3 DO(IO1) HOLD#(IO3) 6 TBT_R_ROM_CLK TBT_R_JTAG_TDO TP@ 1 TP52 PAD~32

WP#(IO2) CLK TBT_R_ROM_DI TBT_R_FLASH_BUSY#
(A5) DG_FLSH_MSTR_SLV (iPU):
4 5 RT190 1 @ 2 10K_0201_5%
GND DI(IO0) +3.3V_TBT_R_LC
W25Q64FVSSIG_SO8 TBT_R_GPIO_5 RT33 1 2 10K_0201_5% '0' - Set Re-timer to be Slave on shared flash SPI I/F.
TBT_R_GPIO_6 RT34 1 @ 2 10K_0201_5% '1' - Set Re-timer to be Master on shared flash SPI I/F.
TBT_R_JTAG_TDI RT71 1 2 10K_0201_5% TBT_R_FLASH_SHARE_EN RT36 1 2 10K_0201_5%
A Reserve SO8 footprint for BB debug conn TBT_R_JTAG_TCK
TBT_R_JTAG_TMS
RT98 1 2 10K_0201_5%
TBT_R_FLASH_MSTR_SLV
(A8) DG_POC_GPIO6: A
RT72 1 2 10K_0201_5% RT39 1 @ 2 10K_0201_5%
TBT_R_JTAG_TDO RT73 1 2 10K_0201_5%
TBT_R_GPIO_12 RT40 1 @ 2 10K_0201_5% '0' -Reserved for debug
'1' -Indication to S0 state for Re-timer

For BBR-A0 PLL Issue Workaround reserved
+3.3V_TBT_R
TBT_R_JTAG_TCK RT219 1 @ 2 10K_0201_5%

P048 - TYPE-C TBT_BB R_TCSS
5 4 3 2 1
5 4 3 2 1
+3.3V_TBT_R_LC +3.3V_TBT_R_ANA
+3.3V_TBT_R_SVR +3.3V_TBT_R_SX
CT68
2.2U_0201_6.3V6M
CT69
2.2U_0201_6.3V6M
CT366
47U_0603_6.3V6M
CT72
1U_0201_6.3V6K
CT71
1U_0201_6.3V6K
CT70
1U_0201_6.3V6K
1 1
2 2 1 1 1 1
D D
2 2 2 2
J5: +3.3V_TBT_R
Place near Pin E5 Place near Pin L2 +3.3V_TBT_R_ANA URT2B @ DB connect to +3.3V_TBT_R.
BB is NC.
+3.3V_TBT_R_LC L2 E6 +3.3V_TBT_R_SX 1 2 0_0402_5%
VCC3P3_ANA VCC3P3_SX RT184
+0.9V_TBT_R_SVR E5 M4 +3.3V_TBT_R_SVR 1 2 0_0402_5%
Place near Pin M4, M5, J5 Place near Pin E6
+0.9V_TBT_R_LVR +0.9V_TBT_R_LC VCC3P3_LC VCC3P3_SVR_1
M5 RT185 +3.3VA_TBT_R GND share with Pin M2, M3 3.3v @ 80mA
VCC3P3_SVR_2
F6
VCC0P9_SVR_ANA_1 VCC3P3_SVR_3
J5 +3.3V_TBT_R_DB 1 DLB@ 2 3.3v @ 290mA
G6 J7 RT202 0_0201_5% +TBT_R_SVR_IND
VCC0P9_SVR_ANA_2 VCC3P3A
CT82
2.2U_0201_6.3V6M
CT84
2.2U_0201_6.3V6M
CT201
10U_0402_10V6M
E3 L1
Power
G3 VCC0P9_SVR_1 SVR_IND_1 M1 +3.3V_TBT_R +3.3VA_TBT_R
1 VCC0P9_SVR_2 SVR_IND_2 connect via inductor to VCC0P9_SVR
1 1
E9 M2
+0.9V_TBT_R_LC VCC0P9_SVR_PB_ANA_1 SVR_VSS_1 RT88 1 0.01_0402_1%
G9 M3 2
2 VCC0P9_SVR_PB_ANA_2 SVR_VSS_2
2 2
CT304
10U_0402_10V6M
CT305
18P_0201_25V8J
CT81
1U_0201_6.3V6K
+0.9V_TBT_R_LVR J3
VCC0P9_LC
L6
VCC0P9_LVR RT123 1 DLB@
M6 J6 2 0_0201_5%
Place near Pin J3 VCC0P9_LVR_SENSE NC_J6 1 1 1
Place near Pin L6,M6
J6:
BURNSIDE-BRIDGE_BGA105 DB connect to GND. 2 2 2
@
BB is NC.
C C
Place near Pin J7

+TBT_R_SVR_IND +0.9V_TBT_R_SVR 3.3v @ 50mA
LT5
1 2
0.68UH_MLV-YT10NR68N-M1L_2.7A_30%
CT74
CT76
CT77
CT73
CT75
CT78
CT79
CT80
1 1 1 1 1 1 1 1
@ @ @
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
18P_0201_25V8J
47U_0603_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
2 2 2 2 2 2 2 2
Place near Pin F6,G6,E3,G3,E9,G9

GND share with Pin M2, M3
0.9v @ 850mA
BB ref sch Rev 1.4 change to CAP Place near Pin F6,E3,E9
+3VALW G3,G6,G9 CAP change to NC
B B
1
CT211 +3VALW
3.3v @ 370mA
1U_0201_6.3V6K UT2 +3.3V_TBT_R
2 EMI@ URT2C
1 7 +3.3V_TBT_R_B 1 2
RT94 1 2 0_0201_5% 2 VIN_1 VOUT_1 8 LT15 BLM18KG331SN1D_2P B1 F12
<44> PD_TCP2_LS_EN VIN_2 VOUT_2 VSS_ANA_1 VSS_ANA_12
B12 G7
RT95 @ 3.3V_TBT_R_EN +3.3V_TBT_R VSS_ANA_2 VSS_ANA_13
1 2 0_0201_5% 3 6 CT210 1 2 470P_0402_50V7K D1 H1
<11,16,47,58> SIO_SLP_SUS# ON CT VSS_ANA_3 VSS_ANA_14
D2 H2
D11 H11
+3VALW
4
VBIAS
5
2 D12
F1
VSS_ANA_5
VSS_ANA_6 GND VSS_ANA_16
VSS_ANA_17
H12
J9
GND_1 9 CT212 F2 VSS_ANA_7 VSS_ANA_18 K1
GND_2 0.1U_0201_10V6K VSS_ANA_8 VSS_ANA_19
F7 K2
3.3V_TBT_R_EN RT93 1 VSS_ANA_9 VSS_ANA_20
1 2 100K_0201_5% F9 K11
RT158 @ VSS_ANA_10 VSS_ANA_21
1 2 10K_0201_5% AOZ1336DI_DFN8_2X2 F11 K12
G5
VSS_1 F5
VSS_2
F3
VSS_3
BB ref sch p.6 note BURNSIDE-BRIDGE_BGA105
DG_P1_PWR_GATE_EN: @
For PD based systems, DG_P1_PWR_GATE_EN should be output from PD.

A A
For TCPC based systems, DG_P1_PWR_GATE_EN should be output from SOC/EC.

P049 - TYPE-C TBT_BB R_PWR,GND
5 4 3 2 1
5 4 3 2 1
USB2/I2C MUXES_L
+3VALW
D D
2
3.3V/0.1A SPEC p.4
CM1 +3VALW
0.1U_0201_25V6K
1
UM1
13 20
VCC A1_OUTp 19
1 A1_OUTn
<43> SW_USB20_1_P8 A_INp UPD_L_SMBCLK
2 18 RM19 1 2 0_0201_5%
<43> SW_USB20_1_N8 A_INn A0_OUTp UPD_L_SMBDAT UPD_SMBCLK_Q <42,44,50,58>
17 RM20 1 2 0_0201_5%
RM13 1 0_0201_5% MUX_L_SAI A0_OUTn UPD_SMBDAT_Q <42,44,50,58>
<42> MUX_L_FLIP# 2 14
RM2 1 2 0_0201_5% MUX_L_ENA_R 16 SAI 15 1 2
<42> PD_L_DDM_MUX1_EN EN_A SAO RM9 0_0201_5%
3 6
<43> SW_USB20_2_P8 B_INp B1_OUTp
4 7
<43> SW_USB20_2_N8 B_INn B1_OUTn
MUX_L_FLIP# RM14 1 2 0_0201_5% MUX_L_SBI 12 8
MUX_L_ENB_R SBI B0_OUTp USB20_P8 <12>
RM1 1 2 0_0201_5% 10 9
<42> PD_L_USB_MUX1_EN EN_B B0_OUTn USB20_N8 <12>
5 11 1 2
21 GND SBO RM10 0_0201_5%
Thermal pad
TS3DS10224RUKR_WQFN20_3X3
USB2/I2C MUXES_R
C C
+3VALW
CM2 3.3V/0.1A SPEC p.4

0.1U_0201_25V6K +3VALW
1
UM2
13 20
VCC A1_OUTp
19
1 A1_OUTn
<45> SW_USB20_1_P4 A_INp UPD_R_SMBCLK
2 18 RM21 1 2 0_0201_5%
<45> SW_USB20_1_N4 A_INn A0_OUTp UPD_R_SMBDAT UPD_SMBCLK_Q <42,44,50,58>
17 RM22 1 2 0_0201_5%
RM15 1 2 0_0201_5% MUX_R_SAI 14 A0_OUTn UPD_SMBDAT_Q <42,44,50,58>
<44> MUX_R_FLIP# MUX_R_ENA_R SAI
RM18 1 2 0_0201_5% 16 15 1 2
<44> PD_R_DDM_MUX1_EN EN_A SAO RM11 0_0201_5%
3 6
<45> SW_USB20_2_P4 B_INp B1_OUTp
4 7
<45> SW_USB20_2_N4 B_INn B1_OUTn
MUX_R_FLIP# RM16 1 2 0_0201_5% MUX_R_SBI 12 8
MUX_R_ENB_R SBI B0_OUTp USB20_P4 <12>
<44> PD_R_USB_MUX1_EN RM17 1 2 0_0201_5% 10 9
EN_B B0_OUTn USB20_N4 <12>
5 11 1 2
GND SBO RM12 0_0201_5%
21
B Thermal pad B
TS3DS10224RUKR_WQFN20_3X3
Channel INA INB
Signal Name TOP BOT
I2C USB
ENA ENB SAI SBI SAO OUTA0 OUTB0 Mux Functional Mode PD Controller W/DDM
0 1 - 0 - Hi-Z TOP - USB only on TOP
0 1 - 1 - Hi-Z BOT - USB only on BOT
1 1 0 0 0 BOT TOP Crosspoint Switch USB on TOP W/DDM
1 1 1 1 0 TOP BOT Crosspoint Switch USB on BOT W/DDM
A A

P050 - TYPE-C USB/I2C MUX
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P051 - Reserve
5 4 3 2 1
5 4 3 2 1
+3VS_WLAN +3VS_WLAN
Close to JNGFF pin4,5 RF Reserved. Close to JNGFF pin72,73 RF Reserved.

D D
0.1U_0201_10V6K
0.01U_0201_16V7
10U_0402_6.3V6M
15P_0201_50V8J
0.1U_0201_10V6K
0.01U_0201_16V7
10U_0402_6.3V6M
15P_0201_50V8J
1 1 1 1 1 1 1 1
CW1
CW2
CW3
CW4 RF@
CW12
CW10
CW9
CW11 RF@
2 2 2 2 2 2 2 2
+3VS_WLAN
UWL1
4
5 3.3V_1
72 3.3V_2 29
3.3V_3 PEWAKE# PCIE_WAKE# <58,67>
73 30 CLKREQ_PCIE#0 <9>
A48 3.3V_4 CLKREQ# 31
3.3V_5 PERST# PCH_PLTRST#_EC <11,46,48,66,67,70,79>
A49
3.3V_6
27 SUSCLK_R RW8 1 2 0_0201_5% SUSCLK
SUSCLK(32KHZ)(3.3V) SUSCLK <9,67>
1
2 UIM_POWER_SRC/GPIO1 14
3 UIM_POWER_SNK SYSCLK/GNSS0 15
UIM_SWP TX_BLANKING/GNSS1
11 7
12 COEX_TXD RESERVED
+3VALW 13 COEX_RXD
COEX3
<10,71> CNVI_EN# 6
16 GND_1 17
2
18 RESERVED_1 GND_2 20
@ RW46 RW19 19 RESERVED_2 GND_3 23
0_0201_5% 100K_0201_5% 66 RESERVED_3 GND_4 26
1
C RESERVED_7 GND_8 C
<58> CNV_RF_RST 24 41
1
D RESERVED_9 GND_10 68
CNV_RF_RESET# 2 QW1 GND_11 71
G PJQ1900_DFN3L CLK_PCIE_N0_R 33 GND_12 74
CLK_PCIE_P0_R 34 REFCLKN0 GND_13 75
S
3
REFCLKP0 GND_14 76
CH1 1 @ 2 0.1U_0402_10V7K~D PCIE_CRX_C_DTX_N3 36 GND_15 77
<12> PCIE_CRX_DTX_N3 PCIE_CRX_C_DTX_P3 PETN0 GND_16
<12> PCIE_CRX_DTX_P3 CH2 1 @ 2 0.1U_0402_10V7K~D 37 78
PETP0 GND_17 79
CH3 1 @ 2 0.1U_0402_10V7K~D PCIE_CTX_C_DRX_N3 39 GND_18 80
<12> PCIE_CTX_DRX_N3 PCIE_CTX_C_DRX_P3 PERN0 GND_19
CH4 1 @ 2 0.1U_0402_10V7K~D 40 81
<12> PCIE_CTX_DRX_P3 PERP0 GND_20 82
GND_21 83
42 GND_22 84
43 CLINK_CLK GND_23 85
NO support C-Link CLINK_DATA GND_24
CNVi&KILLER BOM opt i on c o-l ay

44 86
CLINK_RESET GND_25 87
GND_26 88
45 GND_27 89
46 SDIO_RESET# GND_28 90
47 SDIO_WAKE# GND_29 91
48 SDIO_DATA3 GND_30 92
49 SDIO_DATA2 GND_31 93
EC Side CNV_BRI_CRX_R_DTX RW35 1 2 0_0201_5% CNV_BRI_CRX_R_DTX_R 50 SDIO_DATA1 GND_32 94
SDIO_DATA0 GND_33
MSCLK:TX CNV_RGI_CTX_R_DRX CNV_RGI_CTX_R_DRX_R
51
SDIO_CMD GND_34
95
RW37 1 2 0_0201_5% 52 96
MSDATA:RX SDIO_CLK GND_35 G1
GND_36
If pop KIEER@ components , 53 GND_37
G2
G3
RE205 need de-pop CNV_BRI_CTX_R_DRX 54 UART WAKE#(3.3V)
LPSS_UART_RTS/BRI_DT
GND_38
GND_39
G4
CNV_BRI_CRX_R_DTX_R 55 G5
+3VALW +1.8V_PRIM CNV_RGI_CTX_R_DRX_R 56 LPSS_UART_RXD/BRI_RSP GND_40 G6
CNV_RGI_CRX_R_DTX 57 LPSS_UART_TXD/RGI_DT GND_41 G7
LPSS_UART_CTS/RGI_RSP GND_42 G8
XTAL SEL M.2 CNVI MODES
2
UW2 GND_43 G9
1 6 RW1 @ CNV_RF_RESET# 58 GND_44 G10
NC1 VCC 10K_0201_1% CLKREQ_CNV#_R 59 PCM_SYNC/I2S_WS GND_45 G11
2 5 60 PCM_OUT/I2S_SD_OUT GND_46 G12
<58,79> MSCLK A NC2 PCM_IN/I2S_SD_IN GND_47
61 A07
GPP_F0/CNV_BRI_DT (Internal 20 K Pull Down) GPP_F2/CNV_RGI_DT
1
3 4 1 @ 2 CNV_RGI_CTX_R_DRX_R PCM_CLK/I2S_SCK GND_48 A26

B 3.3V GND Y RW36 0_0201_5% DZ4
WLAN_WIGIG60GHZ_DIS#_R
GND_49
GND_50
A31 B
74AUP1G07FZ4-7_X2-DFN1410-6 1 2 28 A50 0 = 38.4/19.2MHZ (DEFAULT) 0 = INTEGRATED CNVI ENABLE
@ 1.8V <58> WLAN_WIGIG60GHZ_DIS#
63 W_DISABLE1#
W_DISABLE2#
GND_51
DZ3 A11 1 = 24MHZ (25 MHZ WHEN XTAL FREQ 1 = INTEGRATED CNVI DISABLE
<58> BT_RADIO_DIS#
1 2 BT_RADIO_DIS#_R 65 RESERVED_10 A12 DIVIDER NON ZERO) +1.8V_PRIM +1.8V_PRIM
64 LED1# RESERVED_11 A13
+3VALW +3VALW RB751S40T1G_SOD523-2 LED2# RESERVED_12 A14
RESERVED_13 A16
2
USB20_N10_R 69 RESERVED_14 A17 RW32 1 @ 2 10K_0201_5% RW29 1 2 100K_0201_1%

RW40 RW39 USB20_P10_R 70 USB_D- RESERVED_15 A18
100K_0201_5% 100K_0201_5% USB_D+ RESERVED_16 A27 CNV_BRI_CTX_R_DRX RW33 1 @ 2 20K_0201_5% CNV_RGI_CTX_R_DRX RW30 1 @ 2 4.7K_0201_5%
@ @ +1.8V_PRIM RESERVED_17 A28
3.3V 8 RESERVED_18 A29
1
9 ALERT# RESERVED_19 A30

2
1 @ 2 10 I2C_CLK RESERVED_20 A46

<58,79> MSDATA I2C_DATA RESERVED_21
RW45 0_0201_5% RW43 A47
100K_0201_5% RESERVED_22
6
@ RW13 1 2 0_0201_5% CNV_RF_RESET#_R A42

D1 D2 1.8V <10> CNV_RF_RESET# RF_RESET_B A08
CNVi
1
RW17 1 2 0_0201_5% CLKREQ_CNV#_R A43 A4WP_IRQ# A09

CNV_BRI_CRX_R_DTX_R <10> CLKREQ_CNV# CLKREQ0 A4WP_CLK
2 5 A44 A10
G1 G2 REFCLK0 A4WP_DATA A15
@ LNA_EN A25 SUSCLK_R
@ QW2A S1 S2 QW2B REFCLK0 use by Jefferson Peak A45
NC
C_P32K
PMDXB600UNE_DFN1010B-6 PMDXB600UNE_DFN1010B-6
1
A19 CLK_CNV_CTX_DRX_P <13>

WT_CLKP A20
WT_CLKN CLK_CNV_CTX_DRX_N <13>
A21 CNV_CTX_DRX_P0 <13>
WT_D0P A22
WT_D0N CNV_CTX_DRX_N0 <13>
A23 CNV_CTX_DRX_P1 <13>
WT_D1P A24
WT_D1N CNV_CTX_DRX_N1 <13>
A32 CLK_CNV_CRX_DTX_P <13>
WGR_CLKP A33
WGR_CLKN CLK_CNV_CRX_DTX_N <13>
A34 CNV_CRX_DTX_P0 <13>
WGR_D0P A35
WGR_D0N CNV_CRX_DTX_N0 <13>
A36 CNV_CRX_DTX_P1 <13>
WGR_D1P A37
WGR_D1N CNV_CRX_DTX_N1 <13>
A38 CNV_BRI_CTX_R_DRX
BRI_DT CNV_BRI_CRX_R_DTX CNV_BRI_CTX_R_DRX <13>
A39 RW28 1 2 22_0201_1%
BRI_RSP CNV_RGI_CTX_R_DRX CNV_BRI_CRX_DTX <13>
A A40 CNV_RGI_CTX_R_DRX <13> A
RGI_DT A41 CNV_RGI_CRX_R_DTX RW31 1 2 22_0201_1%
RGI_RSP CNV_RGI_CRX_DTX <13>
RW6 1 2 0_0402_5%
RW4 1 @ 2 0_0402_5%
9560.D2WGE2_152P
@
ML1 EMI@ L26 @EMI@
4 3 USB20_P10_R 4 3 CLK_PCIE_P0_R
<12> USB20_P10 <9> CLK_PCIE_P0
1 2 USB20_N10_R 1 2 CLK_PCIE_N0_R
<12> USB20_N10 <9> CLK_PCIE_N0
HCM1012GH900BP_4P HCM1012GH900BP_4P Security Classification Compal Secret Data Compal Electronics, Inc.
RW5 1 @ 2 0_0402_5% RW7 1 2 0_0402_5%
P052 - WLAN/BT (w/ CNVi)
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P053 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P054 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P055 - Reserve
5 4 3 2 1
5 4 3 2 1
Beep sound RA22 1 2 0_0402_5%
RC filter for PWM square to sine-wave

CA78 1
@EMI@
2 0.1U_0402_10V7K
TOP Codec AVDD ( Placement near Audio Codec)
1
RA8
2 1
RA27
2 1
RA28
2
CA14
1 2 MONO_IN
Close +AVDD1 ANALOG DIGITAL +5VS_AUDIO
<58> BEEP
0_0201_5% 0_0201_5% 0.1U_0201_10V6K
RA23 1 2 0_0402_5% Audio jack
1K_0201_5%
BOT
0.22U_0201_6.3V6M
0.22U_0201_6.3V6M
0.22U_0201_6.3V6M
@EMI@ LA1 1 2 HCB2012KF-600T30
1 @ 1 @ 1 @ CA79 1 2 0.1U_0402_10V7K
1
1
CA46
CA47
CA48
DA11
CA19 AZ5125-01H.R7G_SOD523-2
2 2 2 RA25 1 2 0_0402_5% Close Codec 2
10U_0402_10V6M
EMI@
@EMI@
CA80 1 2 0.1U_0402_10V7K AGND
Moat
Place on
2
RA9
D 1 2 @EMI@ D
<10> SPKR
CA81 1 2 0.1U_0402_10V7K Codec to
1
1
In order to prevent the built-in LDO damaged from
1K_0201_5% RA30
1K_0201_5%
@
CA13 CA83 1
@EMI@
2 0.1U_0402_10V7K
Audio Jack over-voltage on +5VD or Standby power line, we
suggested using this Voltage suppressing device.
Close to UA1 Pin32 2
100P_0201_25V7K
@EMI@
Path
2
CA82 1 2 0.1U_0402_10V7K
LINE2-L <57>
Moat
GND AGND
Da
on
nd
'
ts
so
hu
ol
rd
t
te
h
if
sa
p
aa
dw
ty
o
Ur
So
Bm
da
in
gy
i
t
ap
lo
ge
rr
o
ut
n
dr
,a
LINE2-R <57>
+AVDD1
a
f
c
e
s
.
AGND SLEEVE <57>
RING2 <57>
10U_0402_10V6M
10K_0201_5%
MIC2-VREFO-R <57>
Place near UA1 pin26/27
MIC2-VREFO-L <57>
1 2
10 mA HPOUT-L
HPOUT-L <57>
HPOUT-R HPOUT-L
+1.8VS_AUDIO +DVDD
2
RA36 0_0402_5% 2 HPOUT-R
HPOUT-R <57>
10U_0402_6.3V6M
0.1U_0201_10V6K
1
200 mA 1 1
1
MONO_IN
CA39
CA33
330P_0201_50V7K
330P_0201_50V7K
@ @
0603 type
+AVDD1 1
CA9
CA11
2
RA64 1
2 CPVEE CA18 1 2 2.2U_0603_10V7K 2 2
AGND
CA15
Powered by AVDD1
Place next to CODEC
AGND AGND
36
35
34
33
32
31
30
29
28
27
26
25
UA1
10U_0402_10V6M
0.1U_0201_10V6K
CA23
Powered by CPVDD/AVDD2
1 1
CA22
CA17 1 2
LINE2-L
PCBEEP
AUX MODE
MIC_CAP
MIC2-R/SLEEVE
MIC2-L/RING2
MIC2-VREFO-L
HP-OUT-L
CPVEE
LINE2-R
MIC2-VREFO-R
HP-OUT-R
AGND
CA39, CA33 close 2.2U_0201_10V6K

2 2 0603 type
with UA1 Pin3
C
1 RA10 2
AGND
37
AVSS1 AGND CBN
24 CBN 1.8V power rail should be supplied by linear regulator,
not switching regulator. if switching regulator is C
unavoidable, Please make sure that switching
100K_0201_5% 38
VREF
DGND CBP
23 CBP CA21 1 2 2.2U_0603_10V7K frequency operates at out- band(over 20KHz).
5 mA CA20 1 2 39 22 +1.8VS_AUDIO
+1.8VS_AUDIO
RA41
1 2
0_0402_5%
+DVDDIO
AGND
AGND
4.7U_0402_10V6M 40
LDO1_CAP AVSS2
21 LDO2_CAP CA51 1 2 10U_0402_10V6M
AGND
50 mA
AVDD1 LDO2_CAP AGND
10U_0402_6.3V6M
0.1U_0201_10V6K
ALC3281-CG
1
1
CA38
CA36
RA81 1 2 0_0402_5% +PVDD Powered by PVDD 41 20 Near Codec

+5VS_AUDIO PVDD1 CPVDD/AVDD2 Near Codec
LDO3_CAP CA32 1
0.1U_0201_10V6K
42 19 2 10U_0402_10V6M
2
2 SPK-L+ LDO3_CAP
0.1U_0201_10V6K
CA52
0.1U_0201_10V6K
CA26
CA24
10U_0402_10V6M
1 1 Powered by DVDD-IO 1 1
43 18
SPK-L-
QFN48(6*6) DVDD_IO +DVDDIO
CA29
44 17 HDA_SDOUT_R <10>
2 2 SPK-R- SDATA_OUT 2 2
HDA_SDIN0_R 1
45
SPK-R+ Thermal pad=DGND SDATA_IN
16
RA17
2
0_0201_5%
HDA_SDIN0 <10>
OE
GPIO0/DMIC-DATA-12
+PVDD 46 15
PVDD2 SYNC HDA_SYNC_R <10>
CA26 close to UA1 pin41
GPIO1/DMIC-CLK
DMIC-DATA-34/I2S
CA38,CA36close 47 14 AGND
JD2 BCLK HDA_BIT_CLK_R <10>
GPIO2/SPDIFO
@
with UA1 Pin18 JACK_PLUG# 48 13 CA37 1 2 22P_0201_25V8
I2S_LRCLK
JD1 DC_DET/EAPD
I2S_DOUT
I2S_MCLK
I2S_SCLK
I2C_SDA
I2C_SCL
I2S_DIN
0.1U_0201_10V6K
CA30
1 49
GND
DVDD
EAPD reserve 0 ohm
PDB
EAPD
EAPD <57,58>
2
10
11
12
JACK DETECTION NETWORK
+DVDD CA30 close to UA1 pin46 Powered by DVDD AMP_I2S_LRCK 1 2 AMP_I2S_LRCK_R
1 2 RA75 33_0201_5% AMP_I2S_LRCK_R
+DVDD AMP_I2S_BCLK AMP_I2S_BCLK_R <57> AMP_I2S_LRCK_R AMP_I2S_BCLK_R
RA63 100K_0201_5% 1 2
<57> AMP_I2S_BCLK_R
2
RA76 33_0201_5% AMP_I2S_OUT_R

+DVDD AMP_I2S_OUT AMP_I2S_OUT_R <57> AMP_I2S_OUT_R AMP_I2S_IN_R
0.1U_0201_10V6K
RA13 1 2
1 <57> AMP_I2S_IN_R
CA54
100K_0201_1% 100K Necessary RA77 33_0201_5%
AMP_I2S_IN 1 2 AMP_I2S_IN_R
RA57 1 2 1 RA78 33_0201_5%
1
0_0201_5% 2 CA116 1 1 1 AMP_I2C_CLK

CA113 CA114 CA115
<57> AMP_I2C_CLK AMP_I2C_DAT
33P_0201_50V8J
B <57> AMP_I2C_DAT B
DMIC_DATA12_R
JACK_PLUG# 2
33P_0201_50V8J
33P_0201_50V8J
33P_0201_50V8J
DMIC_CLK12_R
2 2 2
1
1
RA14 CA40 @
200K _0201_1% 0.1U_0201_10V6K
2
2
RA58 1 2 0_0201_5%
<57> HP_PLUG# <39> DMIC_DATA12 AMP_I2C_CLK
RA62 1 2 22_0201_5%
<39> DMIC_CLK12 AMP_I2C_DAT
1 1
CA57 CA64
10P_0201_50V8J 33P_0201_50V8J
EMI@ 2 2 EMI@
Near Codec pin5
A A

P056 - Audio ALC3281
5 4 3 2 1
5 4 3 2 1
+1.8VS_AUDIO
+UA2_VBAT
RA73
B+ Int. Speaker Conn.
1 2
1 1 1 1 2 2 0_0603_5%
1
CA105 CA94 CA86 CA93 CA92 JSPK1
CA101 CA117 SPK_L+ 1 5
1U_0603_25V6K 0.1U_0402_25V6 2.2U_0603_10V7K 0.1U_0402_25V6 UA2 0.1U_0402_25V6 10U_0603_25V6M 10U_0603_25V6M SPK_L- 2 1 GND
2
2 2 2 2 1 1 SPK1_DET# 3 2
<10> SPK1_DET# 3
9 25 4 6
8 AVDD VBAT CA88 4 GND
IOVDD 4 1 2 Close to SPK ACES_50208-0040C-P03
BST_P 0.1U_0402_25V6 CONN@
3 SPK_L+_R RA67 1 2 SPK_L+
OUT_P 0_0805_5%
1 17 5
PAD~D TP@ TP153 PDMCK VSNS_P
1 18
PAD~D TP@ TP154 PDMD JSPK2
D D
AMP_I2S_LRCK_R SPK_R+ 1 5
<56> AMP_I2S_LRCK_R AMP_I2S_BCLK_R SPK_R- 1 GND
6 2
<56> AMP_I2S_BCLK_R AMP_I2S_OUT_R AMP_I2S_OUT_R VSNS_N SPK_L-_R SPK_L- SPK2_DET# 2
11 26 RA68 1 2 3
<56> AMP_I2S_OUT_R SDIN OUT_N <10> SPK2_DET# 3
AMP_I2S_IN_R AMP_I2S_IN_R 12 0_0805_5% 4 6
<56> AMP_I2S_IN_R AMP_I2S_BCLK_R SDOUT 1 1 4 GND
13 CA89 CA110 CA109
AMP_I2S_LRCK_R 14 SBCLK 1 1 2 @ @ ACES_50208-0040C-P03
FSYNC BST_N
100P_0201_25V7K
100P_0201_25V7K
0.1U_0402_25V6 CONN@
2 2
AMP_I2C_CLK 23 7
AMP_I2C_DAT 22 SCL DREG 24
SDA AREG
1 1
1
+1.8VS_AUDIO CA90 CA103 CA91 CA104
EAPD 21
SD SPK_L+
0.1U_0402_25V6
1U_0603_25V6K
0.1U_0402_25V6
1U_0603_25V6K
RA79 1 2 20 16
2
4.7K_0201_5% IRQ GND 15 2 2 SPK_L-
GND 10 SPK_R+
19 GND 2 SPK_R-
AMP_I2C_CLK MODE PGND
<56> AMP_I2C_CLK AMP_I2C_DAT
AZ4A24-01F.R7G_DFN0603P2Y2
<56> AMP_I2C_DAT
DA14
DA15
DA8
DA9
EC_AMP_I2C_DAT TAS2770RJQR_VQFN-HR26_4X3P5
<58> EC_AMP_I2C_DAT
2
EC_AMP_I2C_CLK
<58> EC_AMP_I2C_CLK
+1.8VS_AUDIO
Address 0x82 (Left)
RA83 +1.8VS_AUDIO B+
1 2 EAPD RA74 SPK L+ L- R+ R- trace width
@EMI@
@EMI@
@EMI@
@EMI@
1
1
+UA3_VBAT
4.7K_0201_5%
RA71
1
0_0603_5%
2 Speaker 4 ohm ==> 40 mils
1 2 AMP_I2C_CLK CA108
1
CA100
1
CA87
1
CA99
1 1
CA1
2 2
Speaker 8 ohm ==> 20 mils
2.2K_0201_5% CA102 CA118
RA72 1U_0603_25V6K 0.1U_0402_25V6 2.2U_0603_10V7K 0.1U_0402_25V6 UA3 0.1U_0402_25V6 10U_0603_25V6M 10U_0603_25V6M
2
1 2 AMP_I2C_DAT 2 2 2 2 1 1
2.2K_0201_5% 9 25
8 AVDD VBAT CA95
IOVDD 4 1 2 Close to SPK
BST_P 0.1U_0402_25V6
C Follow TI request PAD~D TP@ TP156

1 17
PDMCK
OUT_P
VSNS_P
3
5
SPK_R+_R RA69 1
0_0805_5%
2 SPK_R+
Need up to 15+V, check with EMC C
1 18
PAD~D TP@ TP157 PDMD
+1.8VS_AUDIO
6
AMP_I2S_OUT_R 11 VSNS_N 26 SPK_R-_R RA70 1 2 SPK_R-
AMP_I2S_IN_R 12 SDIN OUT_N 0_0805_5%
AMP_I2S_BCLK_R SDOUT 1 1
13 CA96 CA111 CA112
AMP_I2S_LRCK_R 14 SBCLK 1 1 2 @ @
FSYNC BST_N
2
100P_0201_25V7K
100P_0201_25V7K
0.1U_0402_25V6
2 2
G1
@ Q352A
AMP_I2C_CLK 23 7
EC_AMP_I2C_CLK 6 1 AMP_I2C_CLK AMP_I2C_DAT 22 SCL DREG 24
SDA AREG <56,58> EAPD
D1
S1
1 1
1
+1.8VS_AUDIO CA97 CA106 CA98 CA107
PMDXB600UNE_DFN1010B-6 EAPD 21 @ DA10
SD
0.1U_0402_25V6
1U_0603_25V6K
0.1U_0402_25V6
1U_0603_25V6K
RA80 1 2 20 16 1 2 EAPD
<58> NB_MUTE#
2
IRQ GND
5
4.7K_0201_5% 15 2 2
GND
G2
@ Q352B 10 RB751S40T1G_SOD523-2
GND
1
19 2 1
EC_AMP_I2C_DAT 3 4 AMP_I2C_DAT 2 MODE PGND @
D2
S2
RA21 @ CA55
RA82 1K_0201_5% 1U_0201_6.3V6M
PMDXB600UNE_DFN1010B-6 TAS2770RJQR_VQFN-HR26_4X3P5 2
2
470_0201_1%
Address 0x84 (Right)

1
PCB trace width of MIC2-R(SLEEVE)/MIC2-L(RING2) are

required at least 40 mil for HP crosstalk consideration
and, its length should be as short as possible. Universal Audio Jack CONN
LA19/L15 should choose DC resistance (Rdc) < 30m-ohm
to get the best audio performance for HP crosstalk.
B
Universal Audio Jack B
change RA6/RA3 to 5.6 ohm to meet Dell Grade A

heapdhone output power > 25 mW setting
EMI@
RA6 1 2 20_0201_1% HPOUT-L_L LA19 1 2 BLM15AX700SN1D_2P HPOL_CONN
<56> HPOUT-L
RA3 1 2 20_0201_1% HPOUT-R_L LA18 1 2 BLM15AX700SN1D_2P HPOR_CONN
<56> HPOUT-R
EMI@ ESD207-B1-02EL_TSLP-2-19-2
ESD207-B1-02EL_TSLP-2-19-2
CA12 1 2 10U_0603_6.3V6M
<56> LINE2-L
1
1
330P_0201_50V7K
330P_0201_50V7K
1 1
CA85
CA84
CA10 1 2 10U_0603_6.3V6M
<56> LINE2-R
DA4 EMI@
use X5R for better performance DA5 EMI@

2 2
2
<56> MIC2-VREFO-L
RA2 1 2 2.2K_0201_5%
AGND AGND
Contact with PC BEAN
RA1 1 2 2.2K_0201_5% HP_PLUG#
<56> MIC2-VREFO-R <56> HP_PLUG#
HP_PLUG#
EMI@
40mil L12 1 2 BLM15PX330SN1D_2P SLEEVE_CONN JHP1
<56> SLEEVE
1 2 HPOL_CONN
L15 1 2 BLM15PX330SN1D_2P RING2_CONN HP_PLUG# 3 1 2 4 HPOR_CONN
<56> RING2 3 4
1
EMI@ SLEEVE_CONN 5 6 RING2_CONN
5 6
ESD207-B1-02EL_TSLP-2-19-2
ESD207-B1-02EL_TSLP-2-19-2
DA13 EMI@
40mil ESD207-B1-02EL_TSLP-2-19-2
1
1
330P_0201_50V7K
330P_0201_50V7K
UNIMI_FCECBE015
A 1 1 A
CA59
CA58
AGND CONN@
DA3
DA1
2
2 2
EMI@
EMI@
2
AGND AGND
P057 - Audio Jack/Amp/Speaker
Date: Tuesday, March 05, 2019 Sheet 57 of 100
5 4 3 2 1
5 4 3 2 1
+1.8V_PRIM
SSD_SCP#
RE522 1 @ 2 100K_0201_5%
+RTCVCC_R
BATBTN# RE137 1 2 100K_0201_5%
+3.3V_ALW_UE1 LID_POWER_ON# RE142 1 2 100K_0201_5%

+RTCVCC_R
VCI_IN3#
RE244 1 2 100K_0201_5%
0.1U_0201_10V6K
0.1U_0201_10V6K
RE106 1 2 0_0201_5%
+RTC_CELL_VBAT +3VALW
1 1 <52,67> PCIE_WAKE#
CE50
CE51
+3VALW +3.3V_ALW_UE1
0.1U_0201_10V6K
1 TAP_SMBDAT
CE42
RE49 RE484 1 @ 2 2.2K_0201_5%
2 2 PCIE_WAKE#_R PCH_PCIE_WAKE#
1 2 RE185 1 2 0_0201_5% RE186 1 @ 2 0_0201_5%
PCH_PCIE_WAKE# <11> TAP_SMBCLK
10U_0402_6.3V6M
1 RE483 1 @ 2 2.2K_0201_5%
2
0.1U_0201_10V6K
1U_0201_6.3V6M
0.1U_0201_10V6K
0.01_0603_1%
Stuff RE185 and no stuff RE186 keep E5 design UPD_L_SMBINT#
CE46
close to pin G8/M9 RE108 1 2 100K_0201_5%
1 1 1 Stuff RE186 and no stuff RE185 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
CE43
CE44
CE45
RF Request 2 UPD_R_SMBINT# RE109 1 2 100K_0201_5%
+3VALW
D 2 2 2 +3VALW PBAT_CHARGER_SMBDAT RE111 D
1 2 2.2K_0201_5%
UE1 PBAT_CHARGER_SMBCLK
RE112 1 2 2.2K_0201_5%
EC_AMP_I2C_DAT
F2 GPIO033 RE486 1 @ 2 0_0201_5% RE526 1 @ 2 2.2K_0201_5%
RE113 1 2 100_0201_5% A2 GPIO033/RC_ID0 J10 RE124 1 2 10K_0201_1%
+3.3V_ALW_UE1 GPIO034 THERMTRIP1#
VBAT GPIO034/RC_ID1/SPI0_CLK BOARD_ID EC_AMP_I2C_CLK RE527 @
J13 1 2 2.2K_0201_5%
GPIO036/RC_ID2/SPI0_MISO TAP_SMBDAT SSD_SCP#
22U_0603_6.3V6M
0.1U_0201_10V6K
B7 E7 RE426 1 @ 2 100K_0201_5%
1 1 VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# TAP_SMBCLK
12P_0402_50V8J
RF@
68P_0402_50V8J
RF@
@ CE47
1 1 D7
GPIO004/SMB00_CLK/SPI0_MOSI IMVP_SMBDAT
CE48
K2 RE459 1 2 2.2K_0201_5%
VREF_ADC G3 RE448 1 2 0_0201_5%
RUNPWROK ALLSYS_PWRGD <79>
2 2 +3.3V_EC_PLL GPIO057/VCC_PWRGD SSD_SCP# IMVP_SMBCLK
CE52
CE53
F1 H5 System crash protection RE458 1 2 2.2K_0201_5%

2 2 VTR_PLL GPIO060/KBRST/48MHZ_OUT SSD_SCP# <67>
G11
GPIO104/UART0_TX HOST_DEBUG_TX <79> UPD_SMBDAT
H1 G12 RE446 1 2 2.2K_0201_5%
+VSS_PLL VTR_REG GPIO105/UART0_RX EAPD_R ME_FWP <10>
B13 RE529 1 @ 2 0_0402_5%
G8 GPIO127/A20M/UART0_CTS# F10
UPD_L_SMBINT# EAPD <56,57> Amp. UPD_SMBCLK RE445 1 2 2.2K_0201_5%
+3.3V_ALW_UE1 VTR1 GPIO225/UART0_RTS# UPD_L_SMBINT# <42>
M9
+3.3V_ALW_UE1 VTR2 PCIE_WAKE#_R TP_WAKE_KBC#
0.1U_0201_10V6K
1 N5 N13 RE449 1 2 100K_0201_5%
+1.8V_3.3V_ALW_VTR3 VTR3 GPIO025/TIN0/nEM_INT/UART_CLK N12
PCH_DPWROK_EC GPIO026/TIN1 SIO_SLP_S4# <11,78,79> FPR_DET#
CE49
<11> PCH_DPWROK RE248 1 2 0_0201_5% F8 M11 RE470 1 2 10K_0201_5%
RUN_ON_EC GPIO020 GPIO027/TIN2 TAP_RESET# <63>
E8 H9 TP_EN <63>
2 <78> RUN_ON_EC SIO_EXT_WAKE#_EC GPIO045 GPIO030/TIN3 FPR_SCAN_INT#
RE482 1 2 0_0201_5% M12 RE469 1 2 10K_0201_5%
<10> SIO_EXT_WAKE# BT_RADIO_DIS# GPIO120
C2 L9 1
<52> BT_RADIO_DIS# PBAT_PRES# GPIO166 GPIO017/GPTP-IN5 PAD~D TP@ TP146 PCIE_WAKE#_R
F9 M10 RE481 1 2 10K_0201_5%
SIO_SLP_SUS#_EC GPIO175 GPIO151/ICT4 TAP_FW_RDY# <63>
1 2 N4 N9
<11,16,47,49> SIO_SLP_SUS# GPIO230 GPIO152/GPTP-OUT3 TAP_FW_RDY#
Close to pin H1 RE115 43K_0402_1% M8 RE493 1 2 10K_0201_5%
<38> PANEL_MONITOR GPIO231 BREATH_LED#
K8 C11
<11> AC_PRESENT GPIO233 GPIO156/LED0 BAT1_LED# BREATH_LED# <63>
D10 @
E11 GPIO157/LED1 D11
BAT2_LED# BAT1_LED# <63>
RE492 1 2 0_0201_5%
Amber VCCDSW_EN CE108 1 2 0.1U_0201_10V6K
<10> SML0B_SMBDATA
D8 GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 E1
BAT2_W_LED# <63> White
Connect to PCH <10> SML0B_SMBCLK BATT_LED#_LV5 GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <38> I_BATT_R
CE106
<63> BATT_LED#_LV5 M13 1 2 2200P_0402_50V7K
GPIO110/PS2_CLK2 EC_AMP_I2C_DAT
K12 E5 Amp.
WLAN_WIGIG60GHZ_DIS# GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 EC_AMP_I2C_CLK EC_AMP_I2C_DAT <57> I_SYS_R
L13 B3 CE107 1 2 2200P_0402_50V7K
<52> WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 VCCDSW_EN EC_AMP_I2C_CLK <57>
+3VALW K11 M7
<11,79> SIO_PWRBTN# SLP_WLAN#_GATE_R GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 VCCDSW_EN <16> I_SYS_R
RE476 1 2 0_0201_5% K10 M4 1 RE159 1 @ 2 10K_0201_5%
<71> SLP_WLAN#_GATE LID_CL_SIO# GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 PBAT_CHARGER_SMBDAT PAD~D TP@ TP147
N11 M3
BT_RADIO_DIS# CLK_TP_SIO_I2C_DAT GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <82,83> SSD_SCP#
RE133 1 2 10K_0201_5% RE467 1 2 0_0201_5% E10 N2 RE48 1 @ 2 100K_0201_5%
RE208 1 2 10K_0201_5%
WLAN_WIGIG60GHZ_DIS# <63> PS2_CLK1B_TP
RE468 0_0201_5% DAT_TP_SIO_I2C_CLK
1 2 C12 GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 N10
PBAT_CHARGER_SMBCLK <82,83> Charger and Battery
RE130 1 2 100K_0201_5% BC_DAT_ECE1117 Touch Pad PS2 <63> PS2_DAT1B_TP GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA A12
BAT1_LED# GPIO140/SMB06_CLK/ICT5 IMVP_SMBDAT
RE102 1 2 100K_0201_5% E9 B6
BAT2_LED# <79> JTAG_TDI GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# IMVP_SMBCLK IMVP_SMBDAT <91>
RE101 1 2 100K_0201_5% F6 F7
RE100 100K_0201_5%
BATT_LED#_LV1 <79> JTAG_TDO GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# UPD_SMBDAT IMVP_SMBCLK <91> VCCIN VR
1 2 C8 B4
RE99
RE98
RE97
1
1
1
2
2
2
100K_0201_5%
100K_0201_5%
100K_0201_5%
BATT_LED#_LV2
BATT_LED#_LV3
BATT_LED#_LV4
<79>
<79>
JTAG_CLK
JTAG_TMS JTAG_RST#
C5
G13
GPIO147/SMB08_DATA/JTAG_CLK
GPIO150/SMB08_CLK/JTAG_TMS
JTAG_RST#
GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR#
GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI#
C3
J4
UPD_SMBCLK
I_BATT_R RE125 1
PD
2 300_0402_5% I_BATT <83>
S5 LID OPEN POWER ON +3V_NB_LID
RE96 100K_0201_5% BATT_LED#_LV5 GPIO200/ADC00 I_SYS_R RE126

1 2 E3 J5 1 2 300_0402_5% I_SYS <83,91>
RESET_IN# <77> TACH_FAN1 GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01
RE247 1 2 100K_0201_5% D1 J6
<77> TACH_FAN2 LCD_TST GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 TP_WAKE_KBC#
M2 G2 1 2
<38> LCD_TST GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 TP_WAKE_KBC# <63>
1
L10 H2 RE411 0.01_0402_1%
+3V_NB_LID_R
<77> PWM_FAN1 GPIO053/PWM0/GPWM0 GPIO204/ADC04 BATT_LED#_LV4
1
+3VALW L11 J2 RE479
<77> PWM_FAN2 PCH_RSMRST# GPIO054/PWM1/GPWM1 GPIO205/ADC05 BATT_LED#_LV4 <63>
M5 J3 UE6 390K_0402_1%
<78> PCH_RSMRST# GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06
J8 K3 100K_0201_1% SN74LVC1G123DCUR_VSSOP8
IRCAM_EN GPIO056/PWM3/SHD_CLK GPIO207/ADC07 SOLC <38>
RE528 1 2 100K_0201_5% N1 D3 RE478 1 8
<38> BIA_PWM_EC AUX_EN_WOWL <71>
2
FPR_SCAN_INT# GPIO001/PWM4 GPIO210/ADC08 SUS_ON_EC A# VCC LID_POWER_ON#
1
L8 D2
<77> FPR_SCAN_INT# SUS_ON_EC <78> LID_POWER_ON# <94>
2
SSD_SCP_PWR_EN GPIO002/PWM5 GPIO211/ADC09 NB_LID#
RE525 1 2 100K_0201_5% N6 E2 2 7
100K_0201_5% <67> SSD_SCP_PWR_EN GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 BC_INT#_ECE1117 <63> B R/CEXT
J9 G5
RE521
<38> PANEL_BKEN_EC
H11 GPIO015/PWM7 GPIO213/ADC11 F5
UPD_R_SMBINT# IRCAM_EN <39> IR CAM. 3 6
PCH_RSMRST# <56> BEEP FPR_DET# GPIO035/PWM8/CTOUT1 GPIO214/ADC12 UPD_R_SMBINT# <44> CLR# CEXT
1
RE472 1 2 100K_0201_5% D9 K4 D
<77> FPR_DET#
2
+3.3V_BAT_LDO PBAT_PRES# GPIO133/PWM9 GPIO215/ADC13 PCH_PCIE_WAKE#

H12 L1 4 5 2
C SUS_ON_EC <83> AC_DIS GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 GND Q C
RE95 1 2 100K_0201_5% G10 L3 G QE19
<63> BATT_LED#_LV2 GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <11>
1
D H10 L2N7002WT1G_SC-70-3
<52,79> MSCLK S
3
LCD_TST GPIO170/TFDP_CLK/UART1_TX
10U_0402_10V6M
RE160 1 2 100K_0201_5% 2 G9 H8
<52,79> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ
G QE23 J7
1M_0201_1%
GPIO223/SHD_IO0 3.3V_TS_EN <71> 1
1
S L2N7002WT1G_SC-70-3 <57> NB_MUTE# A4 L6
CE109
RE480
3
GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 PRIM_PWRGD

1
B2 L7
SYS_PWROK <38> EN_INVPWR RESET_IN# GPIO023/GPTP-IN1 GPIO227/SHD_IO2
RE157 1 2 100K_0201_5% C1 M6
IMVP_VR_ON_EC GPIO024/nRESETI GPIO016/GPTP-IN7/SHD_IO3/ICT3 2
10M_0201_1% N7
IMVP_VR_ON_EC <78> IMVP_VR_ON_EC GPIO031/GPTP-OUT1
RE473 1 2 100K_0201_5% RE520 K9 D6 BGPO0 1
PAD~D TP@ TP58
2
N8 GPIO032/GPTP-OUT0 BGPO0 C7
<63> M_BIST ACAV_IN <63,83>
2
RUN_ON_EC GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN

RE475 1 2 100K_0201_5% A5 ALWON
VCI_OUT POWER_SW_IN#
F13 D5 POWER_SW_IN# <63>
E13 GPIO121/PVT_IO0 GPIO163/VCI_IN0# B5 BATBTN# BATBTN# <63,94>
<82> AC_DISC# GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# LID_POWER_ON#
C13 D4
<6,38> EDP_HPD GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# VCI_IN3#
E12 E4
GPIO126/PVT_IO3 GPIO000/VCI_IN3# VSET_5105
ALWON 1 2
F11 ALWON_3VALW <84,94>
<63> RTCRST_ON BATT_LED#_LV1 GPIO122/BCM0_DAT/PVT_IO1 BATT_LED#_LV3
F12 C6 0_0402_5%
1M_0201_5%
<63> BATT_LED#_LV1 BC_DAT_ECE1117 GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 BATT_LED#_LV3 <63>
0.1U_0402_25V6
D12 RE305
RE312
@ CE312
<63> BC_DAT_ECE1117 GPIO046/BCM1_DAT 32KHZ_OUT
1
D13 F3 @ CE105 1 2 10P_0402_50V8J
+3.3V_ALW2 <63> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT
RE147 close to UE1 at least 250mils
1
0.1U_0201_10V6K
1.58K_0402_1%
F4 2
<63> PTP_DIS#
2
SYSPWR_PRES GPIO041/SYS_SHDN# +PECI_VREF
RE152 1 @ 2 1K_0201_5% B1 J11 RE147 1 2 0_0201_5%
+1.05V_VCCST
2
SYSPWR_PRES GPIO044/VREF_VTT PECI_EC_R
CE79
RE199
1 GPIO011 K7 K13 1 2
PAD~D TP@ TP84 GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT PECI_EC <11>
2
RE153 43_0402_5%
0.1U_0201_10V6K
N3 J12 GPIO043 1 RE405
RE154 K6 GPIO021/LPCPD# GPIO043/SB-TSI_CLK A8
REM_DIODE1_N PAD~D TP@ TP112 1 0_0402_5%
CE76 1 2 2200P_0402_50V7K
POWER SW <9,79> ESPI_RESET#
2
ESPI_ALERT# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_P
CE56
100K_0201_5% 1 H7 A7 1 2
PAD~D TP@ TP74 GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N ALWON_5VALW <85>
1 K1 A10 CE93 1 2 2200P_0402_50V7K
PAD~D TP@ TP148 ESPI_CLK_5105 GPIO064/LRESET# DN2_DP2A REM_DIODE2_P
G7 A9
1
2
<9,79> ESPI_CLK_5105 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A REM_DIODE3_N
0.1U_0402_25V6
H6 B9 CE39 1 2 2200P_0402_50V7K
@ CE413
<9,79> ESPI_CS# GPIO066/LFRAME#/ESPI_CS# DN3_DP3A REM_DIODE3_P
1
K5 B8
<9,79> ESPI_IO0 GPIO070/LAD0/ESPI_IO0 DP3_DN3A REM_DIODE4_N
L4 A11 CE86 1 2 2200P_0201_25V7K
<9,79> ESPI_IO1 GPIO071/LAD1/ESPI_IO1 DN4_DP4A REM_DIODE4_P
G6 B10
<9,79> ESPI_IO2
Rest=1.58K , Tp=96 degree
2
GPIO072/LAD2/ESPI_IO2 DP4_DN4A +VR_CAP
L5 C10
<9,79> ESPI_IO3 GPIO073/LAD3/ESPI_IO3 VIN VSET_5105
GPIO167 L2 C9
2 @ 1 RE487 GPIO100 M1 GPIO067/CLKRUN# VSET B11 RE417
Reserved for debug 0_0201_5% I_ADP <83>
SYS_PWROK GPIO100/nEC_SCI VCP
G4 H3 THERMTRIP2# 0_0402_5%
VSS_ANALOG
<11,79> SYS_PWROK CNV_DET#_EC GPIO106/PWROK GPIO103/THERMTRIP2#
RE471 1 2 0_0201_5% L12 B12 THERMTRIP1# 1 2
<52> CNV_RF_RST
Setting for Thermal Design

GPIO107/nSMI THERMTRIP1# PROCHOT#_R1 RE158 1 ALWON_5VALWB <85>
H13 2 100_0402_1%
VSS_ADC
VSS_PLL
+RTCVCC_R MEC_XTAL1 GPIO160/PWM11/PROCHOT# H_PROCHOT# <11,16,86,91>
VR_CAP
A1
MEC_XTAL2_R XTAL1
0.1U_0402_25V6
A3
VSS1
VSS2
VSS3
Thermal diode mapping
@ CE429
XTAL2
1
1
MEC5105_WFBGA169_11X11
A6
A13
E6
H4
J1
C4
G1
2
RE215
CE64 1U_0201_6.3V6M
@ RE184 @
1U_0201_10V6M 1 2 CE68 100K_0201_5%
+3VALW
1 2 THERMTRIP2# MEC5105 pins thermal diode Locat i on
+VR_CAP
+VCCIO_OUT
SIO_SLP_S3# <11,78,79>
+VSS_PLL
DP1/DN1 QE4 Top Skin Temp
2
8.2K_0201_1%
1
MMST3904-7-F_SOT323-3
0.1U_0402_25V6
POWER_SW_IN#
2
RE187 1 2 1K_0201_5%
G
<63,77,79,94> PWRBTN# 1
CE61
C
DN1a/DP1a QE14 HP Temp
2
QE16
1 1 3 1 2 2
RE219 2.2K_0201_5% B
S
CE104 2 +1.05V_VCCST @ E
DP2/DN2 QE17 SSD Temp
3
2.2U_0201_6.3V6M L2N7002WT1G_SC-70-3 QE15
2
RE477 1 2 0_0201_5%
B
<11> H_THERMTRIP# DN2a/DP2a QE8 OTP Sensor B
+3VS
+3VALW +3VALW DP3/DN3 QE10 VR Temp
ESPI only support 1.8V
DN3a/DP3a QE3 AMB Temp
2
2
RH565
RE156 1 2 RE488 RE1
100K_0201_5% +1.8V_PRIM 0_0402_5%
+1.8V_3.3V_ALW_VTR3
100K_0201_5% 10K_0201_5%
DP4/DN4 --- ---
1
1
CE88 D438
1 1
0.1U_0201_10V6K RE461 1 2 0_0201_5%
ALLSYS_PWRGD
2 1
ALW_PWRGD_3V_5V <16,78>
DN4a/DP4a --- ---
JTAG_RST# CE54
VCCIN_AUX_VR_PG <58,89>
PRIM_PWRGD
0.1U_0201_10V6K RE245 1 @ 2 0_0201_5% RB751S40T1G_SOD523-2
2 2 1.8V_PRIM_PG <58,88,89> RE457 @
REM_DIODE1_P
Close to pin N5 1 2 0_0201_5%
MEM_PG <25>
GPIO024 use for PRIM_PWRGD(eSPI) 1.8V_PRIM_PWRGD
1
1U_0201_6.3V6M
D474
1
1 2 1
1
VCCIN_AUX_VR_PG <58,89>
@SHORT PADS~D
JTAG2
CE63
100_0201_1%
@
RE164
RB751S40T1G_SOD523-2 1 PMBT3904MB_SOT883B 1
1
100P_0201_50V8J
100P_0201_50V8J
E QE14 C
2 @ D475 @
B
2 @ 2
2
@JUMP@
CE58
CE57
2 1 B
1.8V_PRIM_PG <58,88,89> 2 2
+3VALW E QE4
C
3
2
RB751S40T1G_SOD523-2 PMBT3904MB_SOT883B
2
+3VS
2
@ Q30A
REM_DIODE1_N
G1
2
+3VALW
UPD_SMBCLK
6 1 @ RE93
<42,44,50> UPD_SMBCLK_Q
DDR CPU
D1
S1
10K_0201_5%
32 KHz Clock +3VALW 0_0201_5% 2 1 RE462
1
ALLSYS_PWRGD_R REM_DIODE2_P
2
RE464 1 2 0_0201_5%
MEC_XTAL2_R RE87
R C REV +3VALW
For EMI request 100K_0201_5%
5
@ Q30B
240K 4700p X00 ESPI_CLK_5105
G2
1
1
PMBT3904MB_SOT883B
130K 4700p X01 UPD_SMBDAT 1 1
1
2N7002KDW_SOT363-6
QE18A
100P_0201_50V8J
100P_0201_50V8J
RE178 RE194 3 4 QE8 C
E
R <42,44,50> UPD_SMBDAT_Q D
RUN_ON#
1
D2
S2
33_0201_5%
240K_0201_1% 2 @
B
2 @ 2
0_0402_5%
62K 4700p X02
@EMC@
CE55
CE69
G B
2 2
RE172
C E QE17
33K 4700p BOARD_ID
2
3
0_0201_5% 2 1 RE463 S PMBT3904MB_SOT883B
YE2
1
MEC_XTAL1 MEC_XTAL2 8.2K 4700p 1
2
1 2
3
33P_0201_50V8J
2N7002KDW_SOT363-6
QE18B
C4240 D
4.3K 4700p C REM_DIODE2_N
10P_0402_50V8J
10P_0402_50V8J
@EMC@
4700P_0201_10V6K 5
2 1 RUN_ON_P <67,71,78>
32.768KHZ_9PF_X1A000141000200 G
2K 4700p WLAN SSD
1
CE65
CE66
CE89
S
1K 4700p
4
2
2
REM_DIODE3_P
A
BOARD_ID rise t i me i s meas ur ed fr o m5 %~68 %. NB LID A
+3VALW +3VS 1 PMBT3904MB_SOT883B 1
1
100P_0201_50V8J
100P_0201_50V8J
QE3 C
E
@ 2 @ 2
B
LID_CL_SIO# LID_CL_TS_FP#
CE60
CE67
RE122 1 2 100K_0201_5% RE237 1 2 100K_0201_5% B
2 C 2 E QE10
3
PMBT3904MB_SOT883B
TAP_SMBDAT
0_0201_5%
2 1
RE523
TAP_SMBDAT_R <63>
Connect to EC
LID_CL_SIO#
2
DE1
1
follow Centenario add board ID in EVT1.1 REM_DIODE3_N
RB520SM-30T2R_EMD2-2
NB_LID# <63>
DVT1.2 _09 Ambient Charger
DE3
TAP_SMBCLK Connect to TS/FPR LID_CL_TS_FP#
2 1 2 1
TAP_SMBCLK_R <63> <11,77> LID_CL_TS_FP#
0_0201_5% RE524

P058 - EC_MEC5105/5106
Date : Tuesday, March 05, 2019 Sheet 58 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P059 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P060 - Reserve
5 4 3 2 1
5 4 3 2 1
0-ohm
+3VALW +3VALW
I2C/ISH_I2C/SML +3VS_TS G
NC
SMBus
UPD_L_SMBDAT 0-ohm UPD_SMBDAT_Q
USB/I2C B_IN UPD_L_SMBCLK UPD_SMBCLK_Q D S 2.2K-ohm 2.2K-ohm
MUX_L
0-ohm 0-ohm
2.2K-ohm 2.2K-ohm UPD_SMBDAT B4
UPD_R_SMBDAT 0-ohm UPD_SMBDAT_Q
USB/I2C B_IN +3VALW UPD_SMBCLK C3 SMB04
DT24 I2C_0_SDA 0-ohm I2C_0_SDA_R UPD_R_SMBCLK UPD_SMBCLK_Q
MUX_R
I2C0 DT23 I2C_0_SCL I2C_0_SCL_R Touch screen [ 0x0A ] 0-ohm G
0-ohm NC
D S
D D
0-ohm NC
0-ohm NC
0-ohm NC
I2C3_PD_L_INT# 23
I2C3_PD_L_DAT 22
I2C3_PD_L_CLK
+3VALW
PD I2C3 for TGL use
21
100K-ohm
I2C3_INT#
I2C3
[ 0x40 ] [ 0X44 ](7bit: 0x22)
SML1_SMBDATA 0-ohm I2C_RT_L_SDA E7 UPD_SMBDAT_Q 0-ohm I2C1_PD_L_DAT 28
29 I2C1_PD_L_INT# 0-ohm UPD_L_SMBINT# F10
SML1_SMBCLK I2C_RT_L_SCL C9 I2C UPD_SMBCLK_Q I2C1_PD_L_CLK 27 GPIO225

I2C1 I2C1_INT#
0-ohm 0-ohm
+3V_PRIM
0-ohm TBT_L_SMBDAT B7
BB_L SML1_SMBDATA 0-ohm I2C2_PD_L_DAT 33 PD_L
NC A1 0 I2C_RT_L_INT# 0-ohm 34 I2C2_PD_L_INT# 0-ohm
TBT_L_SMBCLK A7 SMB I2C_INT# SML1_SMBCLK I2C2_PD_L_CLK 32 +3VALW
I2C2 I2C2_INT# +3VALW
NC 0-ohm 0-ohm [ 0X12 ]
1K-ohm 1K-ohm [ 0X44 ](7bit: 0x22) 0-ohm CHG_DAT
100K-ohm
[ 0x42 ] CHG_CLK Charger
DL22 0-ohm I2C_RT_R_SDA E7 2.2K-ohm 2.2K-ohm
[ 0X40 ](7bit: 0x20)
UPD_SMBDAT_Q 0-ohm I2C1_PD_R_DAT 28 0-ohm
SML1 DN22 I2C_RT_R_SCL C9 I2C 29 I2C1_PD_R_INT# 0-ohm UPD_R_SMBINT# F5
M3 PBAT_CHARGER_SMBDAT 100-ohm DAT_SMB
UPD_SMBCLK_Q I2C1_PD_R_CLK 27 I2C1 I2C1_INT# GPIO214
0-ohm SMB10
+3V_PRIM
0-ohm TBT_R_SMBDAT B7
BB_R 0-ohm
PD_R
N2 PBAT_CHARGER_SMBCLK CLK_SMB Bat t er y Connect or
NC 100-ohm
A1 0 I2C_RT_R_INT# 0-ohm SML1_SMBDATA 0-ohm I2C2_PD_R_DAT 33
SMB [ 0X16 ]
I2C3_INT#
TBT_R_SMBCLK A7 34 I2C2_PD_R_INT# 0-ohm
I2C_INT# +3VALW +3VALW
SML1_SMBCLK I2C2_PD_R_CLK 32 I2C2 I2C2_INT#
NC 0-ohm
I2C3
499-ohm 499-ohm 0-ohm
[ 0X40 ](7bit: 0x20)
EC
100K-ohm
100K-ohm
100K-ohm
100K-ohm
DJ24 SML0_SMBDATA NC NC
23
22
21
PD I2C3 for TGL use 2.2K-ohm 2.2K-ohm 10K-ohm 10K-ohm
PCH SML0
I2C3_PD_R_INT#
I2C3_PD_R_DAT
I2C3_PD_R_CLK
DK24 SML0_SMBCLK
B6 IMVP_SMBDAT 0-ohm IMVP_SMBDAT_VR
VCCIN Controller
NC
SMB05 F7 IMVP_SMBCLK IMVP_SMBCLK_VR MP2940AGRT
NC 0-ohm
+3V_PRIM
100K PD for non-Vpro use
0-ohm NC
C C
0-ohm NC
0-ohm NC
10K-ohm
CL39 TBT_I2C_INT#
GPP_B11
+3V_PRIM
1K-ohm
1K-ohm
DV33 SML0B_SMBDATA SML0B_SMBDATA E11

GPP_D13
DW33 SML0B_SMBCLK SML0B_SMBCLK D8 SMB03
GPP_D14
+3VS_TP
+3VS
+3VALW
10K-ohm
G 10K-ohm
100K-ohm
CR38 PCH_TOUCHPAD_INTR# PCH_TOUCHPAD_INTR# G
GPP_B3
D S TP_WAKE_KBC# G2
GPIO203
S D
+3VS_TP
+3V_PRIM
4.7K-ohm 4.7K-ohm
1K-ohm 1K-ohm
MIPI60@ MIPI60@
DP24 SMB_DATA 0-ohm SMB_DATA_MIPI60
MIPI60@
SMB DK27 SMB_CLK SMB_CLK_MIPI60 MIPI60 Debug
PS2_CLK1B_TP 0-ohm CLK_TP_SIO_I2C_DAT E10
MIPI60@ 0-ohm
PS2_DAT1B_TP DAT_TP_SIO_I2C_CLK C12 PS2_1B
0-ohm
B TOUCHPAD_INTR# B
TouchPad +3VALW +RTCVCC_R

+3VS_TP [ 0x2c ] +3VALW
2.2K-ohm
2.2K-ohm
100K-ohm
+3VALW
2.2K-ohm 2.2K-ohm S D
TAP_SMBDAT_R G TAP_SMBDAT E7
DW23 I2C_1_SDA 0-ohm I2C_1_SDA_R
TAP_SMBCLK_R NC 0-ohm TAP_SMBCLK D7 SMB00
I2C1 DU23 I2C_1_SCL I2C_1_SCL_R
S D
0-ohm
NC 0-ohm BATBTN# B5
VCI_IN1#
+3VALW
CN43 KB Transfer Board 100K-ohm

NC
ISH_I2C0 CN42
NC Keyboard Controller BC_DAT_ECE1117 D12
BC_CLK_ECE1117 D13 BCM1

Accelerometer Bat t er y Gauge 2nd ECE1117
LNG2DMTR [ 0x28 ] [ 0x3A ] MC3451 BC_INT#_ECE1117 E2
GPIO212
CL41
NC
ISH_I2C2 CJ39
NC
Bat t er y Gauge 1st
MC3451
DW41
I2C3
NC Double TAP FPC AMP_I2C_DAT
DT41 Codec
[ 0x5A ]
NC AMP_I2C_CLK
ALC3281
DT40
NC
I2C4 DW40 EAPD
NC
DMIC FPC
G
+1.8VS EC_AMP_I2C_DAT E5
P-Sensor [ 0x52/53 ] Lef t c hannel A mp
A A
[ 0x82 ] TAS2770 S D EC_AMP_I2C_CLK B3 SMB01
1K-ohm 1K-ohm G
UFCAM module [ 0x84 ]

Right channel Amp
CN41 ISH_I2C_1_SDA 0-ohm ISH_I2C_1_SDA_R TAS2770
S D
ISH_I2C1 CL43 ISH_I2C_1_SCL ISH_I2C_1_SCL_R ALS [ 0x29 ]
0-ohm Checking

P061 - SMB/I2C Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siz e Document Number Re v
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H811P 0.1 (X00)
Date : Monday, January 28, 2019 Sheet 61 of 78

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P062 - Reserve
5 4 3 2 1
5 4 3 2 1
+3VS_TP
KB Controller & TP transfer Conn Touch PAD +3VS_TP
2
+3VS_TP
R6214
10K_0201_1%
15P_0402_50V8J
1U_0201_6.3V6M
C4237
1
PU at PCH side 1 1
C4238
PCH_TOUCHPAD_INTR# 6 1 TOUCHPAD_INTR#
<11> PCH_TOUCHPAD_INTR#
+5VALWB +5VALWB EMI@
5
JIO1
1 2 Q351A 2 2
+3VALW 3 1 2 4 +3VALW 2N7002KDW 2N SOT-363-6
3 4 PU at EC side TP_WAKE_KBC#
5 6 +1.8VS <58> TP_WAKE_KBC# 3 4
+3V_NB_LID 7 5 6 8
9 7 8 10
11 9 10 12 Q351B
NB_LID# 11 12 PWRBTN# <58,77,79,94>
13 14 2N7002KDW 2N SOT-363-6
D <58> NB_LID# 13 14 KB_DET# <6> D
<58> TAP_FW_RDY# 15 16 BC_DAT_ECE1117 <58>
17 15 16 18
<58> BC_CLK_ECE1117 17 18 TAP_RESET# <58>
19 20
<58> BC_INT#_ECE1117 19 20 +3VS_TP
21 22
ISH_I2C_1_SDA 23 21 22 24 ISH_I2C_1_SCL +3VALW
<10,39> ISH_I2C_1_SDA ACC1_INT2# 23 24 ISH_I2C_1_SCL <10,39>
25 26
<10> ACC1_INT2# 25 26
1U_0201_6.3V6M
27 28 BAT1_LED# <58>
+3VS_TP 29 27 28 30
BATBTN# BATT_LED#_LV1 <58> 1
C4233
TOUCHPAD_INTR# 31 29 30 32 I2C_1_SDA_R R6216 2 1 2.2K_0201_1%
31 32 BATT_LED#_LV2 <58> I2C_1_SCL_R
33 34 R6215 2 1 2.2K_0201_1%
33 34 BATT_LED#_LV3 <58>
35 36 +3VALW +3VALW +3VS_TP
<58> BREATH_LED# 35 36 BATT_LED#_LV4 <58> 2 PS2_DAT1B_TP
<58> BAT2_W_LED# 37 38 BATT_LED#_LV5 <58> U713 R6218 2 1 4.7K_0201_1%
39 37 38 40 PS2_CLK1B_TP R6217 2 1 4.7K_0201_1%
41 39 40 42 1 7 +3VS_TP_R
41 42 TAP_SMBCLK_R <58> VIN_1VOUT_1
0.1U_0201_16V6K
B+_FLAG
10U_0402_10V6M
43 44 2 8 R6213 1 2 0.01_0603_1% +3VS_TP
43 44 TAP_SMBDAT_R <58> VIN_2VOUT_2
45
45 R6211 1 2 TP_EN_R 3 6 C4236 1 2 2200P_0402_25V7K
1 1 <58> TP_EN
C622
C628
ON CT
0_0201_5% 1
2
ACES_51688-0450M-P01 4 C4239
2 2 VBIAS 5 +3VS_TP
2 0.1U_0201_10V6K
R6212 GND_1 9 2
100K_0201_5% C4232 GND_2
0.1U_0201_10V6K
1
1 AOZ1336DI_DFN8_2X2
TAP_SMBDAT_R JTP1
1
R6222 1 2 B+_FLAG TAP_SMBCLK_R I2C_1_SDA R6220 2 1 0_0201_5% I2C_1_SDA_R 2 1
<94> B+_FLAG_R <10> I2C_1_SDA I2C_1_SCL I2C_1_SCL_R 2
0_0201_5% R6219 2 1 0_0201_5% 3
<10> I2C_1_SCL 3
BATBTN# +5VALWB 4
<58,94> BATBTN# TOUCHPAD_INTR# 4
+1.8VS 5
5
D476
D477
<58> PTP_DIS# 6
2
PS2_DAT1B_TP PS2_DAT1B_TP 7 6
<58> PS2_DAT1B_TP 7
0.1U_0201_16V6K
PS2_CLK1B_TP
10U_0402_10V6M
<58> PS2_CLK1B_TP 8
8
15P_0201_25V8J
PS2_CLK1B_TP
1U_0201_6.3V6M
1 1 EMI@ 1 1 9
C4180
C4221
C4222
C640
GND1
680P_0402_50V7K~D
@ C4235
680P_0402_50V7K~D
@ C4234
1 1 10
GND2
2
ACES_50506-00841-P01
2 2 2 2 CONN@
2 2 @EMI@ D482
1
@EMI@
@EMI@
TVNST52302AB0_SOT523-3 @EMI@
C C
D483
TVNST52302AB0_SOT523-3
1
+3VALW For manufacturer process use only
M-BIST RTC
1
R283
1M_0201_5% +3VS
BAT1_LED#
D481@ +VCC3V3_TBT_R_LDO +VCC3V3_TBT_L_LDO +3.3V_BAT_LDO +3VALW +RTCBATT
+RTCBATT
2
2
RB751V40_SC76-2
3
BAT54HT1G_SOD323-2
BAT54HT1G_SOD323-2
BAT54HT1G_SOD323-2
1 2 R1=10K;R2=10K RTCR2 @
<58,83> ACAV_IN
QZ20 JRTC1 100K_0201_5%
BAT54HT1G_SOD323-2
R2
1
M_BITS_R
LMUN5111T1G_SC70-3 W=20mils W=20mils W=20mils W=20mils W=20mils
2
R273 1 2 0_0201_5% BAT1_LED#_Q 2 2 1
<58> M_BIST +RTCBATT
1
2
2
RTCR1 2
2
R1
RTCD5 RTCD4 RTCD2 RTCD3 1.3K_0402_5% RTC_DET#_R <6>
R272 1 @ 2 330K_0201_1% @ RTCD6 3
<11,78> PCH_RSMRST#_AND G1
4
1
1
G2
1
C D
1
1
2 1 2 ACES_50278-00201-001 2
1
C92 2.2U_0201_6.3V6M B CONN@ G QRTC1 @
2
E 1 2 S L2N7002WT1G_SC-70-3
3
3
QE25 R789 150_0201_1% @ RTCR3
LMBT3904WT1G_SC70-3 100K_0201_5%
<58> POWER_SW_IN# +RTCVCC_R
1
W=20mils
1
C112
1U_0201_6.3V6M
2
B B
+RTCVCC
Gen 8 reserved +RTCVCC_R
@ R2751
0_0402_5%
1 2
Gen 9 X9&X8 RTC discharge schematic

Q349
PJ2301_SOT23-3
1 3
S
1 <9,79> PCH_RTCRST# R2711 @ 2 0_0402_5%~D
1U_0201_6.3V6M
G
2
1
C1040
D116
R5768 RB751S40T1G_SOD523-2
1
2 10K_0402_5% 2 1 D
@ Q3 2 RTCRST_ON
2
L2N7002WT1G_SC-70-3 G
S
3
R5779
1
D R5769 0_0402_5%
2 RTCRST_ON_R 1 2 1 2 RTCRST_ON
RTCRST_ON <58>
G
Q348 S
3
1M_0402_5%~D
0.1U_0402_25V6K~D
L2N7002WT1G_SC-70-3
1
22P_0402_50V8J
100K_0201_1%
1 @
1
R2745
C1131
C1132
2
A 2 A
2
P063 - KB/TP/RTC
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P064 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P065 - Reserve
5 4 3 2 1
5 4 3 2 1
D
For follow
ST/Nuvoton TPM
Centenario reserve +3V_PRIM in EVT1.1
D
DVT1.2_08
+3V_PRIM R5717 1 ST@ 2 0.01_0603_1%
+3VALW
R687 1 750@ 2 0_0402_5% +3.3V_VPS_TPM
1 2 TPM_PIRQ#_R
R656 10K_0201_5% R200 1 750@ 2 0_0402_5% +3VS_TPM
+3VS
R688 1 750@ 2 0_0402_5% +3VALW_TPM

+3VALW
U712
17 22 +3.3V_VPS_TPM
<11,46,48,52,67,70,79> PCH_PLTRST#_EC RST# VPS
14
TPM_PIRQ#_R NC11
C 18 750@ C
<10> TPM_PIRQ#_R PIRQ# +3VALW_TPM
0.1U_0201_10V6K
10U_0402_6.3V6M
0.1U_0201_10V6K
1 1 1 1
SPI_0_CLK_TPM NC1
C96
C1387
C97
R703 1 EMI@ 2 49.9_0201_1% 19
<9> SOC_SPI_0_CLK_R SCLK +3VS_TPM
10U_0402_6.3V6M
0.1U_0201_10V6K
8 750@ 750@
R702 SPI_0_CS#2_TPM NC5
<9> SOC_SPI_0_CS#2 1 2 0_0201_5% 20 1 1
CS# 2 2 2
10U_0402_6.3V6M
0.1U_0201_10V6K
C421
C422
3 750@ 750@
R700 1 2 49.9_0201_1% SPI_0_D0_TPM 21 NC2 4
<9> SOC_SPI_0_D0_R MOSI NC3 1 1
C94
C95
5
R701 SPI_0_D1_TPM NC4 2 2
<9> SOC_SPI_0_D1_R 1 2 49.9_0201_1% 24 10
MISO NC7 11
+3VS NC8 2 2
6 12
GPIO NC9
29 13 place C96,C97,C1387 as close as U712.22
1 @ 2 7 NC19 NC10 15
R649 10K_0201_5% PP NC12
9 25 place C421, C422 as close as U712.1
16 NC6 NC15 26
TPM_GPIO0 NC13 NC16
1 @ST@ 2 23 27 place C94, C95 as close as U712.8
<11,79> SIO_SLP_S0# NC14 NC17
R747 0_0201_5% 32 28
1 @750@ 2 TPM_GPIO0_NU 2 NC22 NC18 30
R54 0_0201_5% GND NC20
33 31
PAD NC21
For NPTC750
ST33HTPH2032AHC1_VQFN32_5X5
Depop R747,R5717
@
Pop C94,C95,C97,C421,C422,R54,R687,R200,R688
Close to U712
B B
SPI_0_CLK_TPM
RF Request
+3VALW
2
33_0201_5%
R648 @EMI@ C453 @EMI@
1
0.1U_0201_10V6K
1 1 1
12P_0201_50V8J
C454 RF@
68P_0201_50V8J
C455 RF@
2 2 2
A A

P066 - TPM
5 4 3 2 1
5 4 3 2 1
+3VALW
1
+3VS_SSD
RZ2 1 2 0_0402_5% CS94
1U_0201_6.3V6M
2
+3VALW
1
US1 +3VS_SSD
C4230
1 7 +3VS_SSD_R 0.1U_0201_10V6K
UZ6 +3VALW VIN_1 VOUT_1
5
2 8 RS200 1 2 0.01_0603_1% 2
RUN_ON_P 1 VIN_2 VOUT_2
P
<58,71,78> RUN_ON_P INB
D 4 RUN_ON_P_R 3 6 CS95 1 2 0.01U_0201_16V7 D
SSD_SCP_PWR_EN 2 O ON CT
<58> SSD_SCP_PWR_EN INA
G
@
MC74VHC1G32DFT2G_SC70-5~D 4 +3VS_SSD
+5VALWB
3
VBIAS
5
GND_1
9
GND_2
33P_0201_25V8J
CS89
4.7U_0402_6.3V6M
CS90
0.1U_0201_10V6K
CS91
0.01U_0201_16V7
CS92
47P_0201_25V8J
CS93
.1U_0402_16V7K~D
C42
1 1 1 1 1 1
AOZ1336DI_DFN8_2X2
SSD_PWR_EN 1 @ 2 0_0402_5%
<10> SSD_PWR_EN
R81 @
2 2 2 2 2 2
+3VS_SSD
JNGFF1
1 2
GND 3.3V
3 4
GND 3.3V
C
<12> PCIE_CRX_DTX_N9 5 6 C
PERn3 NC
<12> PCIE_CRX_DTX_P9 7 8 1 2 0_0402_5%
PERp3 NC SSD_SCP# <58>
9 10 RS379
CS26 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N9 11 GND DAS/DSS#/LED# 12
<12> PCIE_CTX_DRX_N9 PETn3 3.3V
CS27 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_P9 13 14
<12> PCIE_CTX_DRX_P9 PETp3 3.3V
15 16
17 GND 3.3V 18
<12> PCIE_CRX_DTX_N10 PERn2 3.3V
<12> PCIE_CRX_DTX_P10 19 20
PERp2 NC
21 22
CS25 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N10 23 GND NC 24
<12> PCIE_CTX_DRX_N10 PETn2 NC
<12> PCIE_CTX_DRX_P10 PETp2 NC
27 28
29 GND NC 30
PCIe SSD <12> PCIE_CRX_DTX_N11
31
PERn1 NC
32
<12> PCIE_CRX_DTX_P11 PERp1 NC
33 34 1 2
PCIE_CTX_C_DRX_N11 GND NC +3VS_SSD
CS98 1 2 0.22U_0201_6.3V6M 35 36 RS380 10K_0201_5%
<12> PCIE_CTX_DRX_N11 PETn1 NC
<12> PCIE_CTX_DRX_P11 PETp1 DEVSLP SSD_DEVSLP <12>
39 40
GND NC
<12> PCIE_CRX_DTX_P12 41 42
43 PERn0/SATA-B+ NC 44
<12> PCIE_CRX_DTX_N12 PERp0/SATA-B- NC
45 46
SATA SSD CS96 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N12 47
GND NC
48
<12> PCIE_CTX_DRX_N12 PETn0/SATA-A- NC
<12> PCIE_CTX_DRX_P12 PETp0/SATA-A+ PERST#/NC PCH_PLTRST#_EC <11,46,48,52,66,70,79>
51 52
CLK_PCIE_N1_R GND CLKREQ#/NC CLKREQ_PCIE#1 <9>
RS207 1 2 0_0201_5% 53 54 1 2
<9> CLK_PCIE_N1 REFCLKn PEWAKE#/NC +3VS_SSD
RS208 1 2 0_0201_5% CLK_PCIE_P1_R 55 56 RS377 10K_0201_5%
<9> CLK_PCIE_P1 REFCLKp NC
57 58
GND NC
1 @ 2 0_0402_5% PCIE_WAKE# <52,58>
+1.8V_PRIM RS381
B Solt M & Key M B
1 2
RS383 10K_0201_5%
Platform Pin-out
67 68 RS382 1 @ 2 0_0402_5%
NC SUSCLK SUSCLK <9,52>
RS384 1 2 0_0201_5% 69 70
<12> SSD_IFDET PEDET (NC-PCIe/GND-SATA) 3.3V
71 72
GND 3.3V
73 74
GND 3.3V
75
GND
77 76
GND GND
LOTES_APCI0146-P004A
CONN@
A A

P067 - M.2 SSD CONN
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P068 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P069 - Reserve
5 4 3 2 1
5 4 3 2 1
Card Reader
D 1)Placing the RTS5242 chip and flash card socket locate to suit trace routing for SI / EMI / ESD. D
2)Keep bulk and de-coupling capacitors as close as possible to the RTS5242 chip and flash card socket.
■ Bulk capacitor for Card_3V3 place closed to flash card socket.
■ Bulk capacitor for 3V3_IN / 3V3aux / DV12S place closed to RTS5242 chip.
3)Keep damping resistor (ex, for SD CLK / MS CLK) as close as possible to the RTS5242 chip.
4)Keep these capacitors for SD card / MS card signals as close as possible to flash card socket.
+3VS_CR +3VS_CR
0.1U_0201_10V6K
4.7U_0402_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
1 1 1
1
1 2
CR20
CR23
CR7
CR8
R6090 0_0402_5%~D
2
2 2 2
L70 @EMI@
4 3 CLK_PCIE_N4_R
<9> CLK_PCIE_N4
27
11
1 2 CLK_PCIE_P4_R UCR1
<9> CLK_PCIE_P4
+SD_VDD1
3V3aux
3V3_IN
HCM1012GH900BP_4P
1 12
<11,46,48,52,66,67,79> PCH_PLTRST#_EC PERST# CARD_3V3 DV33_18
1 2 2 18 1U_0201_6.3V6M 1 2 CR15
<9> CLKREQ_PCIE#4 CLK_REQ# DV33_18
R6089 0_0402_5%~D EMC@
CLK_PCIE_P4_R 5
CLK_PCIE_N4_R 6 REFCLKP 15 SD_RCLK_M_L RR2 1 2 0_0201_5% SD_RCLK_M
REFCLKN SP1 SD_RCLK_P_L RR3 0_0201_5% SD_RCLK_P
16 1 2
C CR1 1 2 0.1U_0201_10V6K PCIE_CTX_C_DRX_P16 3 RTS5242 SP2 17 SD_CLK_L RR4 1 2 0_0201_5% SD_CLK C
<12> PCIE_CTX_DRX_P16 PCIE_CTX_C_DRX_N16 HSIP SP3 SD_CMD_L SD_CMD
<12> PCIE_CTX_DRX_N16 CR2 1 2 0.1U_0201_10V6K 4 19 RR6 1 2 0_0201_5%
CR3 1 2 0.1U_0201_10V6K PCIE_CRX_C_DTX_P16 7 HSIN SP4 20 SD_D3_L RR8 1 2 0_0201_5% SD_D3
<12> PCIE_CRX_DTX_P16 PCIE_CRX_C_DTX_N16 HSOP SP5 SD_D2_L SD_D2
CR4 1 2 0.1U_0201_10V6K 8 21 RR9 1 2 0_0201_5%
<12> PCIE_CRX_DTX_N16 HSON SP6 SP7_SDWP
29
RR12 1 2 0_0201_5% SP7
<10> MEDIACARD_IRQ#_R CD_WAKE#
+3VS_CR 1 2 32 1 1 1 1 1 1
WAKE#
2.2P_0201_25V
CR18 @EMC@
2.2P_0201_25V
CR17 @EMC@
2.2P_0201_25V
CR16 @EMC@
2.2P_0201_25V
CR13 EMC@
2.2P_0201_25V
CR11 @EMC@
2.2P_0201_25V
CR10 @EMC@
RR11 10K_0201_1% 31
SD_CD# 30 MS_INS#
Close to UR1 SD_CD#
22 SD_LN1_P 2 2 2 2 2 2
SD_LN1_P 23 SD_LN1_M
CR9 1 2 0.1U_0201_10V6K 10 SD_LN1_M
DV12S
14 AV12 26 SD_LN0_P
DV12S SD_LN0_P SD_LN0_M
25
SD_LN0_M
0.1U_0201_10V6K
4.7U_0402_6.3V6M
+SD_VDD2 13
SD_VDD2 24 SD_REG2
1 1
E-PAD
SDREG2
CR5
1 2 RREF 9 28 2 1
RREF GPIO +3VS_CR
CR6
RR1 6.2K_0402_1% 10K_0201_1% RR10 1

2 2 Close to UR1 RTS5242-GR_QFN32_4X4 CR19 EMC@
33
1U_0201_6.3V6M
2
If GPIO not use for LED function,

must be pull-high (Layout guide)
B B
JCR1
+SD_VDD1 Close to JCR1 SD_D2 1

SD_D3 DAT2
2
SD_CMD 3 CD/DAT3
4 CMD
SD_CLK 5 VDD1
CLK
10U_0402_6.3V6M
0.1U_0402_10V7K
6
SD_RCLK_P VSS_1
2 7
1
+SD_VDD2 SD_RCLK_M DAT0/RCLK+
CR21
8
SD_CD# DAT1/RCLK-
CR25
9
10 CD
2
1 11 VDD2
SWIO
4.7U_0402_6.3V6M
0.1U_0402_10V7K
For GPIO control SD_WP 12
QR1 SD_LN0_P 13 VSS_2
1 1 SD_LN0_M D0+
CR24
PJQ1900_DFN3L 14
D0-
CR22
15 19
SP7_SDWP 1 3 SD_LN1_M 16 VSS_3 GND_1 20
D
2 2 SD_LN1_P D1- GND_2

17 21
18 D1+ GND_3 22
VSS_4 GND_4
G
2
T-SOL_158-9090302600
<10> HOST_SD_WP#
A A

P070 - Card reader uSD RTS5242
5 4 3 2 1
A B C D E
+3VS +3VS_TS
TS&WLAN TS_EN_R
100K_0201_5% 2
100K_0201_5% 2
@ 1
1
R220
R6194
+3VS_TS 1
1.8VS +1.8V_PRIM
U34 C223
+3VS_TS_R 1
1 14 F4 1A_65V_T0603FF1000TM 0.1U_0201_10V6K
+3VALW +3VALW VIN1_1 VOUT1_1 2
+3VALW 2 13 1 2 C252
VIN1_2 VOUT1_2 1U_0201_6.3V6M +1.8V_PRIM +1.8VS +1.8VS
TS_EN_R 2
R6168 1 @ 2 0_0201_5% 3 12 C224 1 2 2200P_0402_25V7K UC24
<58> 3.3V_TS_EN ON1 CT1
R672 1 2 0_0201_5%
1 1 <10> PCH_3.3V_TS_EN +3VS_WLAN +1.8VS_R
4 11 1 7 1
+5VALWB VBIAS GND +3VS_WLAN VIN_1 VOUT_1
C240 C235 2 8 R441 1 2 0.01_0603_1%
WLAN_PWR_EN VIN_2 VOUT_2
1U_0201_6.3V6M 1U_0201_6.3V6M 5 10 C237 1 2 2200P_0402_25V7K C248
2 2 ON2 CT2 RUN_ON_P R6170 0_0201_5%
RUN_ON_P_1P8VS
C4189 1 2200P_0402_25V7K
<58,67,71,78> RUN_ON_P 1 2 3 6 2 0.1U_0201_10V6K
+3VS_WLAN_R ON CT 2
6 9
+3VALW VIN2_1 VOUT2_1 1
7 8 R222 1 2 0.01_0603_1%
VIN2-2 VOUT2_2 C233 4
+5VALW VBIAS
15 0.1U_0201_10V6K 5
GPAD 2 GND_1 9
AOZ1331DI_DFN_14 GND_2
AOZ1336DI_DFN8_2X2
+3VALW +3V_PRIM +3VALW
EC PCH
1
1
1
R322
100K_0201_5%
@ R616
100K_0201_5%
R617
20K_0201_5%
R532
75K_0201_5%
1.8VS_AUDIO 1
2
RE321 1 @ 2 0_0201_1%
<58> SLP_WLAN#_GATE WLAN_PWR_EN_PCH WLAN_PWR_EN
1 2
2
R534 @ 0_0201_5%
G
1
D23 D +1.8V_PRIM
SLP_WLAN#_M
1 3 2 2 Q350 @
<11,71> SIO_SLP_WLAN# <10,52> CNVI_EN#
G PJQ1900_DFN3L
D
WLAN_PWR_EN_EC WLAN_PWR_EN
1 1 2 S 1
3
1
Q124 R533 0_0201_5%
2
PJQ1900_DFN3L 3 R529 C256
<58> AUX_EN_WOWL
R6137 75K_0201_5% 1U_0201_6.3V6M
2 +1.8V_PRIM +1.8VS_AUDIO +1.8VS_AUDIO
100K_0201_5%
BAT54CW_SOT323-3 UC25
2
1 @ 2
+1.8VS_AUDIO_R
1
RE322 0_0201_1% 1 7
VIN_1 VOUT_1 1
2 8 R211 1 2 0.01_0603_1%
<11,71> SIO_SLP_WLAN# VIN_2 VOUT_2 C276
<10,71> AUD_PWR_EN 3 6 C234 1 2 4700P_0402_25V7K 0.1U_0201_10V6K
ON CT 2
EC request to reserve OR gate for WLAN power enable
+5VALW
4
VBIAS 5
GND_1 9
GND_2
AOZ1336DI_DFN8_2X2
5VS_AUDIO
+5VS_AUDIO
+5VALWB +5VS_AUDIO
+5VALWB U36
1
+5VS_AUDIO_R
1 7 C278
1 VIN_1 VOUT_1
2 8 R716 1 2 0.01_0805_1% 0.1U_0201_10V6K
C246 VIN_2 VOUT_2 2
AUD_PWR_EN
1U_0201_10V6M 3 6 C245 1 2 3300P_0402_25V7K
<10,71> AUD_PWR_EN ON CT
2
4
+5VALWB VBIAS 5
GND_1 9
GND_2
AOZ1336DI_DFN8_2X2
+3VS
2 2
R232 1 2 10K_0201_5%
AUD_PWR_EN
R600 1 @ 2 10K_0201_5%
5VBS
+5VBS
U60
+5VBS_R
+5VALWB
1 7 +5VBS
+5VALWB 2 VIN_1 VOUT_1 8 R670 1 2 0.01_0603_1%
VIN_2 VOUT_2
RUN_ON_P RUN_ON_P_5VBS
<58,67,71,78> RUN_ON_P
R6199 1 2 0_0201_5% 3 6 C4213 1 2 220P_0402_50V8K
ON CT 1
1
C801
C4212 4 0.1U_0201_10V6K
+5VALWB VBIAS 2
1U_0201_10V6M 5
2 GND_1 9
GND_2
AOZ1336DI_DFN8_2X2
5VS
+5VALW
3 3
1
C4204
1U_0201_10V6M
2
+5VALW +5VS +5VS
UC28
+5VS_R
1 7
VIN_1 VOUT_1 1
2 8 R6182 1 2 0.01_0603_1%
VIN_2 VOUT_2 C4207
RUN_ON_P RUN_ON_P_5VS
R6181 1 2 0_0201_5% 3 6 C4205 1 2 2200P_0402_25V7K 0.1U_0201_10V6K
<58,67,71,78> RUN_ON_P ON CT 2
4
VBIAS 5
GND_1 9
GND_2
AOZ1336DI_DFN8_2X2
CAMERA +3VALW
3VS
1
C4199 +3VALW
1U_0201_6.3V6M
2 +3VALW
+CAM_PWR +CAM_PWR UC30 +3VS
1
+3VS
+3VS_R
C229 1 7
1U_0201_6.3V6M 2 VIN_1 VOUT_1 8 R216 1 2
1 1 0.01_0603_1% 1
2 VIN_2 VOUT_2
C4197 C4198
RUN_ON_P R6169
RUN_ON_P_3VS
C227 1000P_0402_25V8J C230
<58,67,71,78> RUN_ON_P 1 2 0_0201_5% 3 6 1 2
10U_0402_10V6M ON CT 0.1U_0201_10V6K
0.1U_0201_10V6K
2 2 2
+3VS 4
VBIAS 5
GND_1 9
R704 2 @ 1 10K_0201_5% +CAM_PWR GND_2
3.3V_CAM_EN_R
R6162 2 1 10K_0201_5% +3VALW
AOZ1336DI_DFN8_2X2
U55
+CAM_PWR_R
5 1 R6161 1 2 0.01_0603_1%
IN OUT
2
GND
3.3V_CAM_EN 3.3V_CAM_EN_R
R6163 1 2 0_0201_5% 4 3
<6> 3.3V_CAM_EN EN OC
SY6288C20AAC_SOT23-5
4 4
Card Reader
+3VALW
1
+3VS
C4216 +3VALW
R666 1 2 100K_0201_5% 1U_0201_6.3V6M +3VS_CR +3VS_CR +3VS_CR
SD_PWR_EN_R 2
R667 1 @ 2 100K_0201_5%
UC31
+3VS_CR_R
5 1 1 2 1 1
IN OUT R669 0.01_0603_1%
2 C4217 C800
GND 10U_0402_10V6M 0.1U_0201_10V6K
SD_PWR_EN_R 2 2
R6171 1 @ 2 0_0201_5% 4 3
<12> SD_PWR_EN EN OC Security Classification Compal Secret Data Compal Electronics, Inc.
SY6288C20AAC_SOT23-5 2020/10/01 2018/10/01 Title
Issued Date Deciphered Date
P071 - DC/DC
Date: Sheet of
A B C D E
5 4 3 2 1
D
eDP DMIC module D
TS Middle board UFCAM module
FPC FPC
LF-H812P LF-H813P Audio Jack FPC
LF-H811P
C C
JEDP1 JUFC1
p.38 p.39
JHP1
p.57
M/B JFP1
p.57
FPC 8pin
FP Module
LA-H811P LF-H816P
JIO1
p.63
FPC 45 pin
B
LF-H814P B
32pin FPC 20pin Battery Gauge LED

Keyboard
KB Transfer Board LF-H815P
6pin LS-H811P
KBBL
A A

P072 - Board Map
5 4 3 2 1
A
SW_TBT_L_USB20_P1 1 0-ohm
8 USB20_P8
SW_TBT_L_USB20_N1 2 A_IN +3VALW
B0_OUT 9 USB20_N8 To PCH & PD_L +3VALW
USB/I2C +3VALW
To LEFT Type-C Connector MUX_L G
NC
SW_TBT_L_USB20_P2 3 17 UPD_L_SMBDAT 0-ohm
B_IN A0_OUT 100K-ohm 100K-ohm

SW_TBT_L_USB20_N2 4 18 UPD_L_SMBCLK D S
0-ohm 2.2K-ohm 2.2K-ohm F10 UPD_L_SMBINT#

GPIO225
UPD_SMBDAT B4
SW_TBT_R_USB20_P1 1 8 USB20_P9
0-ohm
UPD_SMBCLK C3 SMB04 EC
SW_TBT_R_USB20_N1 2 A_IN B0_OUT 9 USB20_N9 To PCH & PD_R F5 UPD_R_SMBINT#
USB/I2C +3VALW
GPIO214
To RIGHT Type-C Connector MUX_R
SW_TBT_R_USB20_P2 4 17 UPD_R_SMBDAT 0-ohm G
SW_TBT_R_USB20_N2 3 B_IN A0_OUT 18 UPD_R_SMBCLK NC

0-ohm D S
0-ohm NC
0-ohm NC
0-ohm NC
I2C3_PD_L_INT# 23
I2C3_PD_L_DAT 22
I2C3_PD_L_CLK
PD I2C3 for TGL use
21
I2C3_INT#
I2C3
SML1_SMBDATA 0-ohm I2C_RT_L_SDA E7 UPD_SMBDAT_Q 0-ohm I2C1_PD_L_DAT 28
29 I2C1_PD_L_INT# 0-ohm
SML1_SMBCLK I2C_RT_L_SCL C9 I2C UPD_SMBCLK_Q I2C1_PD_L_CLK 27 I2C1 I2C1_INT#
1 1
0-ohm 0-ohm
+3V_PRIM
0-ohm TBT_L_SMBDAT B7
BB_L SML1_SMBDATA 0-ohm I2C2_PD_L_DAT 33
PD_L
NC A10 I2C_RT_L_INT# 0-ohm 34 I2C2_PD_L_INT# 0-ohm
TBT_L_SMBCLK A7 SMB I2C_INT# SML1_SMBCLK I2C2_PD_L_CLK 32 I2C2 I2C2_INT#
NC 0-ohm 0-ohm
1K-ohm 1K-ohm
DL22 0-ohm I2C_RT_R_SDA E7

UPD_SMBDAT_Q 0-ohm I2C1_PD_R_DAT 28
SML1 DN22 I2C_RT_R_SCL C9 I2C 29 I2C1_PD_R_INT# 0-ohm
UPD_SMBCLK_Q I2C1_PD_R_CLK 27 I2C1 I2C1_INT#
0-ohm
+3V_PRIM
0-ohm TBT_R_SMBDAT B7
BB_R 0-ohm
PD_R
NC
PCH SMB A10 I2C_RT_R_INT# 0-ohm SML1_SMBDATA 0-ohm I2C2_PD_R_DAT 33
I2C3_INT#
TBT_R_SMBCLK A7 34 I2C2_PD_R_INT# 0-ohm
I2C_INT#
SML1_SMBCLK I2C2_PD_R_CLK 32 I2C2 I2C2_INT#
NC 0-ohm
I2C3
499-ohm 499-ohm 0-ohm
100K-ohm
100K-ohm
100K-ohm
100K-ohm
DJ24 SML0_SMBDATA
23
22
21
SML0
PD I2C3 for TGL use
I2C3_PD_R_INT#
I2C3_PD_R_DAT
I2C3_PD_R_CLK
DK24 SML0_SMBCLK
100K PD for non-Vpro use

+3V_PRIM 0-ohm NC
0-ohm NC
0-ohm NC
10K-ohm
CL39 GPP_B11 TBT_I2C_INT#

GPP_B11

P073 -TBT I2C/SML block diagram
0.1 (X00)
A
A
UFCAM module
PCH
P-sensor
ALS
ALS_ALERT#
ISH_GP7
1 1
ESPI
EC
+3V_NB_LID
NB_LID#
GPIO115 NB LID
GPIO161
(VCI_IN2#)

P074 - Sensor block diagram
A
5 4 3 2 1
(8) +3VALW
(5) B+ (8) +3VALW

100k-ohm
(8) 3VALW_PG 0-ohm (8) ALW_PWRGD_3V_5V

VIN
PG (8) 3VALW_PG VIN
(5) B+ 0-ohm
VOUT (8) 5VALW_PG
(4) +CHG_VIN_20V +3VALW_DSW
VIN CHARGER (8) 5VALWB_PG 0-ohm +3VALW
(6) ACAV_IN (7) ALWON (8) +3VALW (8)VCCDSW_EN_GPIO (9)+3VALW_DSW
ACOK EN VOUT EN VOUT
(8) +3VALW
(5) B+
D D
(1) +TBT_VBUS_L_PD
VIN
PG (8) 5VALW_PG VIN
+5VALW
+3V_PRIM
Type-C Port-L (8) +3VALW
(7) ALWON (8) +5VALW (8)VCCDSW_EN_GPIO (9) +3V_PRIM
EN VOUT EN VOUT
(4) +CHG_VIN_20V VIN (3) +RTCVCC_R (5) B+

LDO_3V3 (5) B+
PD_L 100k -ohm
(0) +3.3V_BAT_LDO
VIN_3V3 VIN
(8) +3VALW VIN (8) 5VALWB_PG (14) 1.8V_PRIM_PG
PG PG
(2) +TBT_VBUS_R_PD (8) +3VALW
+1.8V_PRIM (8) +3VALW
(2)+VCC3V3_TBT_L_LDO
+5VALWB (12) SIO_SLP_SUS# (13) +1.8V_PRIM
100K-ohm
(7) ALWON (8) +5VALWB EN VOUT
Type-C Port-R EN VOUT
(2)+VCC3V3_TBT_R_LDO
(5) B+
(4) +CHG_VIN_20V VIN (7) ALWON 100k -ohm
LDO_3V3
VBAT GPIO_024 GPIO_164
(8) +3VALW
VCI_OUT
PD_R nRESETI VCI_OVRD_IN VIN
PG (17) VCCIN_AUX_VR_PG
VIN_3V3
(10) RESET_IN# +VCCIN_AUX
10ms Delay
100K-ohm (14) 1.8V_PRIM_PG (16) +VCCIN_AUX
EN VOUT
(9) +3VALW_DSW VCC_DSW 3P3 0-ohm

(11) PCH_DPWROK (8)VCCDSW_EN
DSW_PWROK GPIO_020 GPIO_012
(5) B+ (13) +1.8V_PRIM
(8)VCCDSW_EN_GPIO
(12) SIO_SLP_SUS#
SLP_SUS# GPIO_230
(9) +3V_PRIM
VIN VIN
VCC_PRIM3P3
(19) PCH_RSMRST#_AND 0-ohm
C
(18) PCH_RSMRST# (17) PRIM_PWRGD C
RSMRST# GPIO_227 +1.1V_MEM +1.8V_MEM
RSMRST#
(8) ALW_PWRGD_3V_5V (26) SIO_SLP_S4# VOUT
(31) +1.1V_MEM (26) SIO_SLP_S4# VOUT
(31) +1.8V_MEM
EN EN
(20) ESPI_RESET# (5) B+

ESPI_RESET# GPIO_061
ESPI_RESET#
(21) ESPI_IO
ROM SP I
ESPI_IO ESPI_IO LPDDR4x POP0-ohm VIN
(22) AC_PRESENT
+0.6V_VDDQ
ACPRESENT GPIO_233
(31) +0.6V_VDDQ
(23) POWER_SW_IN# EN VOUT
(13) +1.8V_PRIM GPIO_163/VCI_IN0# Power Button
VCCPRIM_1P8
(14) +VCC1.05_OUT_PCH (24) SIO_PWRBTN# (14) +VCC1.05_OUT_FET

VCCPRIM_1P05 PWRBTN# GPIO_113
(14) +VCC1.05_OUT_FET
VCC1P05
SLP_S5#
(25) SIO_SLP_S5#
(26) SIO_SLP_S4#
GPI0_040
EC 5105 (15) CORE_VID0
(15) CORE_VID1
(16)VCCIN_AUX_CORE_VID
VIN
+VCCST_CPU
SLP_S4# GPIO_026
(17) VCCST_EN (18) +VCCST_CPU
(27) SIO_SLP_S0# EN VOUT
SLP_S0#
SLP_S3# (27) SIO_SLP_S3# (27) SIO_SLP_S3#
GPIO_032
(8) +3VALW (27) CPU_C10_GATE# VCCST_OVERRIDE_R
CPU_C10_GATE# SLP_VCCST_OVRD
10k-ohm (15) CORE_VID0 (15) CORE_VID0

CORE_VID0
ICL U PCH (35) VCCST_PWRGD
GPIO_045
(MIPI60 debug use only)
(28) RUN_ON_EC
VIN
(27) +1.1V_MEM
VIN
Level
10k-ohm
VCCST_PW RGD
Shifter
(29) RUN_ON_P
(15) CORE_VID1 (15) CORE_VID1 (34) IMVP_VR_ON_EC
CORE_VID1 GPIO_031 (27) SIO_SLP_S3# +VCCSTG_CPU +VCC_SFR_OC
VCCST_OVERRIDE_R (30) VCCSTG_EN
VCCST_OVERRIDE EN (32) +VCCSTG_CPU (30) VCCSTG_EN (32) +VCC_SFR_OC
(27) CPU_C10_GATE# VOUT EN VOUT
B B
(35) IMVP_VR_ON_P
(13) +1.8V_PRIM (13) +1.8V_PRIM
(26) +3VS
(38) CPUPWRGD
VIN VIN
100k-ohm +VCC1P8A +1.8VS

(27) CPU_C10_GATE# VOUT
(32) +VCC1P8A (29) RUN_ON_P VOUT
(32) +1.8VS
EN EN
(37) PCH_PWROK_P (40) PCH_PLTRST# (41) PCH_PLTRST#_EC

PCH_PWROK PLTRST# GPIO_064/LRESET#
(7) +3VALW (7) +5VALW

(39) SYS_PWROK
SYS_PW ROK
VIN VIN
(32) +3VS
+3VS +5VS/+5VBS
MOS (29) RUN_ON_P VOUT
(32) +3VS (29) RUN_ON_P VOUT
(32) +5VS/+5VBS
EN EN
(39) SYS_PWROK 10K-ohm
GPIO_106/PWROK
(33) RUNPWROK (5) B+ (5) B+

(ALL_SYS_PWRGD)
GPIO_057/VCC_PW RGD MOS
VIN VIN
+SSD_PWR2 +SSD_PWR3
(29) RUN_ON_P VOUT
(32) +SSD_PWR2 (29) RUN_ON_P VOUT
(32) +SSD_PWR3
EN EN
(5) B+
A A
VIN
PG (37) PCH_PWROK_P
+VCCIN
(35) IMVP_VR_ON_P VOUT
(36) +VCCIN
EN

P075 - AC_Power up Sequence
5 4 3 2 1
5 4 3 2 1
(5) +3VALW
(2) B+ (5) +3VALW

100k-ohm
(5) 3VALW_PG 0-ohm (5) ALW_PWRGD_3V_5V

VIN
PG (5) 3VALW_PG VIN
(5) 5VALW_PG 0-ohm

+3VALW_DSW
(5) 5VALWB_PG 0-ohm +3VALW
(4) ALWON (5) +3VALW (5) VCCDSW_EN_GPIO (6) +3VALW_DSW
EN VOUT EN VOUT
(2) B+ (5) +3VALW

D D
(2) B+
VOUT
VIN
PG (5) 5VALW_PG VIN
CHARGER
+5VALW
+3V_PRIM
(5) +3VALW
(4) ALWON (5) +5VALW (5) VCCDSW_EN_GPIO (6) +3V_PRIM
EN VOUT EN VOUT
(1) +RTCVCC_R (2) B+

(2) B+
(0) +3.3V_BAT_LDO 100k -ohm
VIN
(5) +3VALW VIN (5) 5VALWB_PG (11) 1.8V_PRIM_PG
PG PG
(5) +3VALW
+1.8V_PRIM (5) +3VALW
+5VALWB (9) SIO_SLP_SUS# (10) +1.8V_PRIM
100K-ohm
(4) ALWON (5) +5VALWB EN VOUT
EN VOUT
(2) B+
(4) ALWON 100k -ohm
VBAT GPIO_024
(5) +3VALW
VCI_OUT
nRESETI VIN
PG (14) VCCIN_AUX_VR_PG
(7) RESET_IN# +VCCIN_AUX

10ms Delay
100K-ohm (11) 1.8V_PRIM_PG (13) +VCCIN_AUX
EN VOUT
(6) +3VALW_DSW VCC_DSW 3P3 0-ohm

(8) PCH_DPWROK (5) VCCDSW_EN
DSW_PWROK GPIO_020 GPIO_012
(2) B+ (11) 1.8V_PRIM_PG
(5)VCCDSW_EN_GPIO
(9) SIO_SLP_SUS#
SLP_SUS# GPIO_230
(6) +3V_PRIM
VIN VIN
VCC_PRIM3P3
(16) PCH_RSMRST#_AND 0-ohm
C
(15) PCH_RSMRST# (14) PRIM_PWRGD C
RSMRST# GPIO_227 +1.1V_MEM +1.8V_MEM
RSMRST#
(5) ALW_PWRGD_3V_5V (21) SIO_SLP_S4# VOUT
(26) +1.1V_MEM (21) SIO_SLP_S4# VOUT
(26) +1.8V_MEM
EN EN
(17) ESPI_RESET# (2) B+

ESPI_RESET# GPIO_061
ESPI_RESET#
(18) ESPI_IO
ROM SP I
ESPI_IO ESPI_IO LPDDR4x POP0-ohm VIN
+0.6V_VDDQ
(26) +0.6V_VDDQ
(3) POWER_SW_IN# EN VOUT
(10) +1.8V_PRIM GPIO_163/VCI_IN0# Power Button
VCCPRIM_1P8
(11) +VCC1.05_OUT_PCH (19) SIO_PWRBTN# (11) +VCC1.05_OUT_FET

VCCPRIM_1P05 PWRBTN# GPIO_113
VCC1P05
SLP_S5#
(20) SIO_SLP_S5#
(21) SIO_SLP_S4#
GPI0_040
EC 5105 (12) CORE_VID0
(12) CORE_VID1
(13)VCCIN_AUX_CORE_VID
VIN
+VCCST_CPU
SLP_S4# GPIO_026
(14) VCCST_EN (15) +VCCST_CPU
(22) SIO_SLP_S0# EN VOUT
SLP_S0#
SLP_S3# (22) SIO_SLP_S3# (22) SIO_SLP_S3#
GPIO_032
(5) +3VALW (22) CPU_C10_GATE# VCCST_OVERRIDE_R
CPU_C10_GATE# SLP_VCCST_OVRD
10k-ohm (12) CORE_VID0 (12) CORE_VID0

CORE_VID0
ICL U PCH (30) VCCST_PWRGD
GPIO_045
(MIPI60 debug use only)
(23) RUN_ON_EC
VIN
(22) +1.1V_MEM
VIN
Level
10k-ohm
VCCST_PW RGD
Shifter
(24) RUN_ON_P
(12) CORE_VID1 (12) CORE_VID1 (29) IMVP_VR_ON_EC
CORE_VID1 GPIO_031 (22) SIO_SLP_S3# +VCCSTG_CPU +VCC_SFR_OC
VCCST_OVERRIDE_R (25) VCCSTG_EN
VCCST_OVERRIDE EN (27) +VCCSTG_CPU (25) VCCSTG_EN (27) +VCC_SFR_OC
(22) CPU_C10_GATE# VOUT EN VOUT
B B
(30) IMVP_VR_ON_P
(10) +1.8V_PRIM (10) +1.8V_PRIM
(26) +3VS
(33) CPUPWRGD
VIN VIN
100k-ohm +VCC1P8A +1.8VS

(22) CPU_C10_GATE# VOUT
(27) +VCC1P8A (24) RUN_ON_P VOUT
(27) +1.8VS
EN EN
(32) PCH_PWROK_P (35) PCH_PLTRST# (36) PCH_PLTRST#_EC

PCH_PWROK PLTRST# GPIO_064/LRESET#
(7) +3VALW (5) +5VALW

(34) SYS_PWROK
SYS_PW ROK
VIN VIN
(27) +3VS
+3VS +5VS/+5VBS
MOS (24) RUN_ON_P VOUT
(27) +3VS (24) RUN_ON_P VOUT
(27) +5VS/+5VBS
EN EN
(34) SYS_PWROK 10K-ohm
GPIO_106/PWROK
(28) RUNPWROK (2) B+ (2) B+

(ALL_SYS_PWRGD)
GPIO_057/VCC_PW RGD MOS
VIN VIN
+SSD_PWR2 +SSD_PWR3
(24) RUN_ON_P VOUT
(27) +SSD_PWR2 (24) RUN_ON_P VOUT
(27) +SSD_PWR3
EN EN
(2) B+
A A
VIN
PG (32) PCH_PWROK_P
+VCCIN
(30) IMVP_VR_ON_P VOUT
(31) +VCCIN
EN

P076 - DC_Power up Sequence
5 4 3 2 1
5 4 3 2 1
Screw Hole
Fiducial Mark
FD1 FD2 FD3 FD4
1 @ @ @ @
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
D
ME Spring for 1.13mm cable D
CLIP1 CLIP2 CLIP3 CLIP4 CLIP5 CLIP6 CLIP7 CLIP8

1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
EMIST_SU-15AG EMIST_SU-15AG EMIST_SU-15AG EMIST_SU-15AG EMIST_SU-15AG EMIST_SU-15AG EMIST_SU-15AG EMIST_SU-15AG

CONN@ CONN@ CONN@ CONN@ CONN@ CONN@ CONN@ CONN@
PCB X 12(PTH) CPU X 5 SSD stand-off

H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H17 HCPU1 HCPU2 HCPU3 HCPU4 HSSD1
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
H_1P6 H_3P6 H_2P0 H_2P6 H_3P6 H_2P6 H_2P6 H_3P6 H_2P6 H_3P6 H_2P0 H_2P0 H_2P0 H_3P3 H_3P3 H_3P3 H_3P3 H_3P3
1
1
PCB X 2(NPTH) PAD X 6 (SMT Screw) TBT Shielding PCB suppoert bracket
H21 H14 H15 H16 H18 H19 H20
@ @ @ @ @ @ @
H_1P9X0P9 H_1P3N PAD_C6 PAD_C4 PAD_C4 PAD_C4 PAD_C4
1
S1 S2 S3 S4
C C
Power button & Finger print 0_0201_5% 2
+3V_NB_LID
1 R208
FAN1 +3VS +5VS
10U_0603_25V6M
0.1U_0402_25V6K~D
2
G
B B
2
C1124
2
1 3 PWRBTN#_FPR
10K_0201_1%
10K_0201_1%
10K_0201_1%
C4181
<58,63,79,94> PWRBTN#
2
D
+3VS_FP JFP1 @
Modena Conn, Check pin define
R36
R37
R38
1
RW10 1 @ 2 0_0402_5% @ QF1 10 1
PJQ1900_DFN3L GND_2 9
8 GND_1
1
ML18 PWRBTN#_FPR 7 8 LT9
EMI@ JFAN1
EMI@
1 2 USB20_P5_R USB20_N5_R 6 7 1 2 +5VS_FAN1 1
<12> USB20_P5 USB20_P5_R 6 1
5 D132 HCB2012KF-800T50_2P 2
5 <58> PWM_FAN1 2
4 2 1 3
USB20_N5_R NB_LID#_FPR 4 <58> TACH_FAN1 3
<12> USB20_N5 4 3 <11,58> LID_CL_TS_FP# 0_0201_5% 2 1 R808 3 4
0_0201_5% 2 1 R801 FPR_SCAN#_R 2 3 5 4
<58> FPR_SCAN_INT# FPR_DET#_R 2 RB751V40_SC76-2 G1
HCM1012GH900BP_4P 0_0201_5% 2 1 R800 1 6

<58> FPR_DET# 1
1
G2
+3VS RW11 1 @ 2 0_0402_5% TWVM_FPC0510-08RC-TAGHA D469 ACES_50224-00401-001
1
D14 D13 CONN@ BZT52C6V2LP-7_X1-DFN1006-2-2 CONN@

FPR_SCAN#_R
+3V_NB_LID 2 1 +3VS_FP_R FPR_DET#_R
2
R638 0_0402_5% +3VS_FP +3VS_FP
F2
2
R390 2 @ 1 0_0402_5% 1 2
100P_0201_50V8J
1 EMI@ EMI@
0.1U_0201_10V6K
0438.500WR 0.5A 32V UL/CSA D16 EMI@

1
2
2
C2990
1U_0201_6.3V6M
C4183 @EMI@
TVNST52302AB0_SOT523-3
1 +3VS
C4186
+5VBS
FAN2
2
10U_0603_25V6M
0.1U_0402_25V6K~D
1
2
2
C1125
2
10K_0201_1%
10K_0201_1%
10K_0201_1%
C4182
2
2
@
Modena Conn, Check pin define
R39
R40
R41
1
1
1
LT10
EMI@ JFAN2
1 2 +5VBS_FAN2 1
HCB2012KF-800T50_2P 2 1
<58> PWM_FAN2 D12
2 1 3 2
<58> TACH_FAN2 3
4
A 5 4 A
RB751V40_SC76-2 G1
6
1
G2
D470 ACES_50224-00401-001
BZT52C6V2LP-7_X1-DFN1006-2-2 CONN@
2
P077 - PWRBTN&FPR/SCREW/FAN
5 4 3 2 1
5 4 3 2 1
+3VALW_DSW&+3V_PRIM RSMRST# +3VALW

PROM_BIOS_R <9>
FOLLOW CSLP
1
R6204
100K_0201_5% R466
1K_0201_5%
2
1 @ 2 +3VALW
1 2 ALW_PWRGD_3V_5V RC644 0_0201_5%
<84> 3VALW_PG
RC702 0_0201_5% 1
1 2 +3VALW
<85> 5VALW_PG
RC703 0_0201_5% CC1
+3VALW_DSW 1 2
<85> 5VALWB_PG 0.1U_0201_10V6K
RC704 0_0201_5% UC2 MC74VHC1G08DFT2G_SC70-5 2
5
U31 +3VALW_DSW
+3VALW_DSW_R 1
+3VALW 1 14 1
P
+3VALW VIN1_1 VOUT1_1 <58> PCH_RSMRST# B
2 13 R204 1 2 0.01_0603_1% C218 4
VIN1_2 VOUT1_2 ALW_PWRGD_3V_5V O PCH_RSMRST#_AND <11,63>
0.1U_0201_10V6K 2
<16,58> ALW_PWRGD_3V_5V
G
VCCDSW_EN_GPIO 1 2 3VALW_DSW_EN 3 12 C217 1 2 2200P_0402_25V7K 2 A
1 <16> VCCDSW_EN_GPIO ON1 CT1
RC651 0_0201_5%
3
C216 4 11
+5VALWB VBIAS GND
1U_0201_6.3V6M
D 2 1 2 3V_PRIM_EN 5 10 C1467 1 2 2200P_0402_25V7K D
RC657 0_0201_5% ON2 CT2 +3V_PRIM
6 9 +3V_PRIM_R
+3VALW
SUS_ON(DDR EN)
7 VIN2_1 VOUT2_1 8 R6048 1 2 0.01_0603_1% +3V_PRIM +3VALW
VIN2-2 VOUT2_2 RC695 1 2 0_0201_5%
15 1 1
+3VALW GPAD +3VALW
+3VALW AOZ1331DI_DFN_14 C1468 C4201
0.1U_0201_10V6K 0.1U_0201_10V6K
2 UC5 MC74VHC1G08DFT2G_SC70-5 2
1
5
R375 1 2 100K_0201_5% @
VCCDSW_EN_GPIO RC736
C1469 R374 1 @ 2 100K_0201_5% 1 0_0402_5%
P
<11,58,79> SIO_SLP_S4# B SUS_ON_P
1U_0201_6.3V6M 4 1 2
2 O 1.1V_MEM_EN <25,86>
2
<58> SUS_ON_EC
G
A
0.1U_0402_10V7K
1M_0201_5%
1
1
3
1
@ RC737
@ CC707
RE21 @
100K_0201_5%
2
2
2
1 2
@ RE22 0_0201_5%
+3VALW
VCC_SFR_OC(VCCPLL_OC) RUN_ON(VS EN) 1

RE460
+3VALW
@ 2
0_0201_5% 1
C4202
0.1U_0201_10V6K
2
UC4
5
1
P
<11,58,78,79> SIO_SLP_S3# B RUN_ON_P
4
O RUN_ON_P <58,67,71>
2
<58> RUN_ON_EC
G
+1.1V_MEM +VCC_SFR_OC A
2
3
1 MC74VHC1G08DFT2G_SC70-5 RE14
1 100K_0201_5%
CC395
1U_0201_6.3V6M CC721
1
2 0.1U_0201_10V6K 1 2
2 @ RE15 0_0201_5%
+1.1V_MEM
UC27 +VCC_SFR_OC
1
C 2 VIN1 C
VIN2
+5VALW 7 6 +VCC_SFR_OC_R RC643 1 2 0.01_0603_1%
VIN thermal VOUT
3
IMVP_VR_ON&VCCST_PWRGD
VBIAS
VCCSTG_EN 1 2 VCC_SFR_OC_EN 4 5
RC640 0_0201_5% ON GND
AOZ1334DI-01_DFN8-7_3X3 +3VALW
1
+3VALW
C4203
0.1U_0201_10V6K +3VALW
U15 MC74VHC1G08DFT2G_SC70-5 2 UE8
5
1 5
SIO_SLP_S3# 1 NC VCC
P
B 4 IMVP_VR_ON_P 2
+3V_PRIM 2 O A 4
<58> IMVP_VR_ON_EC VCCST_PWRGD <11>
VCCSTG
G
+3VS A 3 Y
GND
1
3
+3V_PRIM 74AUP1G07SE-7_SOT353-5
1
CC632
0.1U_0201_10V6K
100K_0201_5% 2 RE489
RC631 IMVP_VR_ON_P 1 2
IMVP_VR_ON_P <11> IMVP_VR_ON_EN <91>
UC10 1 2
2
1
MC74VHC1G08DFT2G_SC70-5 @ RE10 0_0201_5% 0_0402_5%
1
P
<11> CPU_C10_GATE#
1
B 4 VCCSTG_EN_R 1 2 100K_0201_5%
1 @ 2 RUN_ON_R 2 O RC636 NMIPI60@ 0_0201_5% RE29 CE430
<11,58,78,79> SIO_SLP_S3#
G
RC730 0_0201_5% A 0.1U_0402_25V6
2
3
RUN_ON_P 1 2
RC731 0_0201_5%
VCC1P8A shape from VR to VCC1P8A pins should have:

+VCC1.05_OUT_FET
+VCC1P8A a. total length L of < 22mm between VR and BGA.
1
UC12
+VCCSTG_CPU
b. Average width W of 1.8mm.
UC11 MIPI60@ 2 VIN1 RC351 1 @ 2 0_0201_5%
VCCSTG_EN_R VCCSTG_EN_MIPI
VIN2
+VCCSTG_R 1
RC639 PDG p.615 +1.8V_PRIM
3 4 1 MIPI60@ 2 +5VALW 7 6 2 UC22
A Y RC634 0_0201_5% VIN thermal VOUT TCSS and AGSH 1 +VCC1P8A
1
2 5 3 0.01_0603_1% 2 VIN1
B
@ RC701
100K_0201_5% 1
GND Vcc
6
+3V_PRIM
VCCSTG_EN 4
VBIAS
5
Type C Sub system and +5VALWB 7
VIN2
6 +VCC1P8A_R 1
RC718
2 +VCC1P8A B
+3V_PRIM B C MIPI60_OVERRIDE# <78,79>
+VCC1.05_OUT_FET ON GND +VCCSTG_CPU processor analog supply. 3
VIN thermal VOUT
0.01_0603_1%
2
+3V_PRIM SN74AUP1G97DRLR_SOT6 AOZ1334DI-01_DFN8-7_3X3 +1.8V_PRIM RC226 VBIAS

CPU_C10_GATE# 1 VCC1P8A_EN 1
1 1 2 4 5
ON GND CC668
1
CC638 CC667 1 0.1U_0201_10V6K
1U_0201_6.3V6M 0_0201_5% 2
CC633 0.1U_0201_10V6K AOZ1334DI-01_DFN8-7_3X3
0.1U_0201_10V6K 2 2 CC386
2 1U_0201_6.3V6M
2
VCCST
+3V_PRIM
+3V_PRIM
+3V_PRIM
1
+3V_PRIM
+3V_PRIM
1
+1.8_MEM
CC620 CC625
1
+3V_PRIM 0.1U_0201_10V6K 0.1U_0201_10V6K

RC617 2 2
5
100K_0201_5% UC9
1
1 2 SLP_VCCST_MIPI60_OVRD 1 +1.8V_PRIM +1.8V_MEM

P
5
RC616 UC7 RC619 NMIPI60@ 0_0201_5% INB 4 1 2 VCCST_EN

2
100K_0201_5% 1 VCCIN_AUX_CORE_VID 2 O RC627 0_0201_5%

P
<11,58,78,79> SIO_SLP_S3#
G
INB 4 SLP_VCCST_OVRD INA

3.3_VCCST_OVERRIDE O 2
2 MC74VHC1G32DFT2G_SC70-5 1
2
3
G
INA C3011 CC394

MC74VHC1G32DFT2G_SC70-5 1U_0201_6.3V6M
3
6
D 1 0.1U_0201_10V6K
2 QM1A 2
QM1B G 2N7002KDW_SOT363-6 +1.8V_PRIM
3
2N7002KDW_SOT363-6 D UC23 +1.8V_MEM

5 S 1
<11> VCCST_OVERRIDE_R
1
G +VCC1.05_OUT_FET +VCC1.05_OUT_FET 2 VIN1

1
UC13 VIN2
RC615 S 1 +VCCST_CPU 7 6 +1.8V_MEM_R RC139 1 2 0.01_0603_1%
4
100K_0201_5% 2 VIN1 VIN thermal VOUT

1 VIN2 3
+VCCST_R +5VALWB VBIAS
CC629 +5VALW 7 6 1 2
2
1U_0201_6.3V6M VIN thermal VOUT RC630 0.01_0603_1% SUS_ON_P 4 5

2 3 ON GND
UC8 MIPI60@ VBIAS
VCCST_EN 4 5 +VCCST_CPU AOZ1334DI-01_DFN8-7_3X3
SLP_VCCST_OVRD 3 4 1 2 SLP_VCCST_MIPI60_OVRD ON GND
A Y MIPI60@ RC623 0_0201_5% +3V_PRIM
1
A 2 5 AOZ1334DI-01_DFN8-7_3X3 A
GND Vcc +3V_PRIM 1
@ RC700 RC626 @ 1
100K_0201_5% 1 6 100K_0201_5% CC666
+3V_PRIM B C MIPI60_OVERRIDE# <78,79>
CC621 0.1U_0201_10V6K
0.1U_0201_10V6K
SN74AUP1G97DRLR truth table 2
2
SN74AUP1G97DRLR_SOT6 2
+3V_PRIM
+3V_PRIM
1
CC622
0.1U_0201_10V6K
2
5
UC6
1
P
<16,89> CORE_VID0 INB VCCIN_AUX_CORE_VID

4 1 2
2 O RC624 0_0201_5%
<16,89> CORE_VID1 Security Classification Compal Secret Data Compal Electronics, Inc.
G
INA
MC74VHC1G32DFT2G_SC70-5 RC735 @ 2020/10/01 2018/10/01 Title
3
100K_0201_5%
P078 - DC/DC & Sequence Logic
2
5 4 3 2 1
5 4 3 2 1
MIPI 60
PLACE WITHIN 1.1INCH OF MERGED MIPI60 CONNECTOR
R191 2 1 0_0201_5% MIPI60_TDI +VCC1.05_OUT_FET +V1.05A_MIPI60
<11>
<11>
MIPI60_CPU_JTAG_TDI
MIPI60_PCH_JTAG_TDI
R312 2 1 0_0201_5% DFXTESTMODE(ITP_PMODE)
+V1.05A_MIPI60 +3VS
R201 2 1 0_0201_5% MIPI60_TDO R123 1 2 0.01_0402_1%
<11> MIPI60_CPU_JTAG_TDO
R156 2 1 0_0201_5% MIPI60@
<11> MIPI60_PCH_JTAG_TDO DBG_PMODE (Internal 20 K Pull UP) MIPI60_DBRESET#_R 1K_0201_5% 2 1 R176
R300 2 1 0_0201_5% MIPI60_TMS MIPI60@
<11> MIPI60_CPU_JTAG_TMS
<11> MIPI60_PCH_JTAG_TMS
R247 2 1 0_0201_5% 0 = DFXTESTMODE ENABLED 0.1U_0201_16V6K 2 1 C200
+VCCIO_OUT
R190 2 1 0_0201_5% MIPI60_TCLK MIPI60@
CFG TERMINATIONS(CRB p.69/SDS p.110 reserved )
<11> MIPI60_CPU_JTAG_TCLK
R244 2 1 0_0201_5% 1 = DFXTESTMODE DISABLED(DEFAULT)
<11> MIPI60_PCH_JTAGX
R192 2 1 0_0201_5% MIPI60_TRST# +V1.05A_MIPI60
<11> MIPI60_CPU_JTAG_TRST#
R213 2 1 0_0201_5%
<11> MIPI60_PCH_JTAG_TRST#
R270 1 MIPI60@ 2 1K_0201_5%
1 UNSTUFF RC AND STUFF RD FOR MIPI60 TO XDP60 ADAPTOR COMPATIBILITY
@ R160 2 1 10K_0201_5% MIPI60_CFG0# C1544MIPI60@ DBG_PMODE R6143 1 @ 2 1K_0201_5% +1.05V_VCCSTG
MIPI60_CFG1# +V1.05A_MIPI60
@ R161 2 1 10K_0201_5% 0.1U_0201_10V6K +VCCIO_OUT
@ R162 2 1 10K_0201_5% MIPI60_CFG2# 2
@ R163 2 1 10K_0201_5% MIPI60_CFG3#
@ R164 2 1 10K_0201_5% MIPI60_CFG4#
RC RD
1
D @ R165 2 1 10K_0201_5% MIPI60_CFG5# D
MIPI60_CFG6#
@ R166 2 1 10K_0201_5% JMIPI60 CONN@ R113 R114 @
@ R167 2 1 10K_0201_5% MIPI60_CFG7# +V3.3A_1.8A_PCH_SPI +V1.05A_VREF_DEBUG 1 2 MIPI60_TMS R112 @ 0_0201_5% 0_0201_5%
@ R168 2 1 10K_0201_5% MIPI60_CFG8# MIPI60_TCLK 3 VREF_DEBUG TMS 4 MIPI60_TDO 51_0201_5% MIPI60@
PLACE WITHIN 1.1INCH OF MERGED MIPI60 CONNECTOR
@ R169 2 1 10K_0201_5% MIPI60_CFG9# R544 2 @ 1 0_0201_5% MIPI60_TDI 5 TCK0 TDO 6 MIPI60_DBRESET# R236 2 MIPI60@ 1 0_0201_5% MIPI60_DBRESET#_R
<11,46,48,52,66,67,70,79> PCH_PLTRST#_EC MIPI60_DBRESET#_R <11>
2
1
@ R170 2 1 10K_0201_5% MIPI60_CFG10# R545 2 MIPI60@ 1 0_0201_5% DBG_PMODE_MIPI60_RST# 7 TDI HOOK7 8 MERGED_TRST_PD
CRB P.73 <11> DBG_PMODE
@ R171 2 1 10K_0201_5% MIPI60_CFG11# R261 @ MIPI60_TRST# 9 HOOK6 TRST_PD 10
MIPI60_CFG12# TRST_N PREQ_N MIPI60_PREQ# <11>
@ R172 2 1 10K_0201_5% 1.5K_0201_5% 11 12
MIPI60_CFG13# <11> MIPI60_PRDY# PRDY_N VREF_TRACE
@ R173 2 1 10K_0201_5% 13 14 Pin 16 PDG no define,CRB tie GND P.71
MIPI60_CFG14# <18> MIPI60_CFG_STB0_DP MIPI60_SPI0_IO2
@ R174 2 1 10K_0201_5% <9> MIPI60_SPI0_IO2 R188 1 MIPI60@ 2 0_0201_5% MIPI60_PRESENT1# 15 PTI_0_CLK PTI_1_CLK 16 +VCCIO_OUT
2
@ R175 2 1 10K_0201_5% MIPI60_CFG15# MIPI60_OVERRIDE# R335 1 MIPI60@ 2 0_0201_5% MIPI60_PRESENT2# 17 POD_PRESENT1_N GND1 18
SPI0_MOSI_SYS_PWROK_MIPI60 <78> MIPI60_OVERRIDE# POD_PRESENT2_N PTI_1_DATA0 1
0_0201_5% 1 MIPI60@ 2 R260 19 20
<9> MIPI60_SPI0_MOSI <18> MIPI60_CFG0# PTI_0_DATA0 PTI_1_DATA1
<11,58> SYS_PWROK 0_0201_5% 1 @ 2 R644 1 21 22 C100 MIPI60@
<18> MIPI60_CFG1#
1
23 PTI_0_DATA1 PTI_1_DATA2 24 0.1U_0201_10V6K
<18> MIPI60_CFG2# PTI_0_DATA2 PTI_1_DATA3 2
C220 @ 25 26 R246 @
<18> MIPI60_CFG3# PTI_0_DATA3 PTI_1_DATA4
0.1U_0201_16V6K 27 28 150_0201_1%
2 <18> MIPI60_CFG4# PTI_0_DATA4 PTI_1_DATA5
CRB p.74,75/SDS p.31,32 reserved
Except CFG 4
<18>
<18>
MIPI60_CFG5#
MIPI60_CFG6#
29
31 PTI_0_DATA5 PTI_1_DATA6
30
32 RA PLACE STRAPPING RESISTOR RB WITHIN 0.25" OF MAIN_NOA0_N_ROUT
2
PTI_0_DATA6 PTI_1_DATA7
@ R140 1 2 1K_0201_5% MIPI60_CFG0#
MIPI60_CFG1#
<18>
<18>
MIPI60_CFG7#
MIPI60_CFG8#
33
35 PTI_0_DATA7
PTI_0_DATA8
RSVD1
HOOK3
34
36 SPI0_MOSI_SYS_PWROK_MIPI60
MIPI60_HOOK2_CPU_BOOT_STALL
RB MIPI60_CFG0#
@ R141 1 2 1K_0201_5% +3VALW_DSW 37 38 1 2 connect to MIPI60_CFG0_N PDG no define
MIPI60_CFG2# <18> MIPI60_CFG9# PTI_0_DATA9 HOOK2 SMC_ONOFF_MIPI60_N
@ R142 1 2 1K_0201_5% 39 40 R230 MIPI60@ 1K_0201_5%
MIPI60_CFG3# <18> MIPI60_CFG10# PTI_0_DATA10 HOOK1
@ R143 1 2 1K_0201_5% 41 42
MIPI60_CFG4# <18> MIPI60_CFG11# PTI_0_DATA11 HOOK0 PM_RSMRST_PWRGD_MIPI60 <11>
R144 1 2 1K_0201_5% 43 44
<18> MIPI60_CFG12# RA SHOULD BE STUFFED ONLY FOR MIPI60 TO XDP60 ADAPTOR COMPATIBILITY
2
@ R145 1 2 1K_0201_5% MIPI60_CFG5# 45 PTI_0_DATA12 RSVD2 46
MIPI60_CFG6# <18> MIPI60_CFG13# PTI_0_DATA13 RSVD3 SMB_CLK_MIPI60
@ R146 1 2 1K_0201_5% R267 @ 47 48 R725 1 MIPI60@ 2 0_0201_5%
MIPI60_CFG7# <18> MIPI60_CFG14# PTI_0_DATA14 I2C_SCL SMB_DATA_MIPI60 SMB_CLK <9>
@ R147 1 2 1K_0201_5% 1K_0201_5% 49 50 R726 1 MIPI60@ 2 0_0201_5%
MIPI60_CFG8# <18> MIPI60_CFG15# MIPI60_TCLK1 PTI_0_DATA15 I2C_SDA V3.3A_CPU_NOA_LA_VAL SMB_DATA <9>
@ R148 1 2 1K_0201_5% R193 2 MIPI60@ 1 0_0201_5% 51 52
MIPI60_CFG9# <11> MIPI60_PCH_JTAG_TCLK MIPI60_MBP1#_R TCK1 RSVD4 UART_2_CTXD_R_DRXD
@ R149 1 2 1K_0201_5% R194 2 MIPI60@ 1 0_0201_5% 53 54 R249 1 @ 2 0_0201_5%
<18> MIPI60_MBP1# UART_2_CTXD_DRXD <10>
1
@ R150 1 2 1K_0201_5% MIPI60_CFG10# 0_0201_5% 1 2 R257 SMC_ONOFF_MIPI60_N R195 2 MIPI60@ 1 0_0201_5% MIPI60_MBP0#_R 55 HOOK9 DBG_UART_TX 56 UART_2_CRXD_R_DTXD R157 1 @ 2 0_0201_5%
MIPI60_CFG11# <11,58> SIO_PWRBTN# <18> MIPI60_MBP0# HOOK8 DBG_UART_RX UART_2_CRXD_DTXD <10>
@ R151 1 2 1K_0201_5% MIPI60@ 1 57 58
@ R152 1 2 1K_0201_5% MIPI60_CFG12# 59 GND2 GND3 60
MIPI60_CFG13# <18> MIPI60_CFG_STB1_DP PTI_3_CLK PTI_2_CLK
@ R153 1 2 1K_0201_5% C285 MIPI60@ 61 62
@ R154 1 2 1K_0201_5% MIPI60_CFG14# 0.1U_0201_16V6K 63 GND_4 GND_5 64 +3V_PRIM NEED SINGLE ENDED 50OHM ROUTING , FOR STB0, STB1 SIGNALS
@ R155 1 2 1K_0201_5% MIPI60_CFG15# 2 65 GND_6 GND_7 66 R614 1 MIPI60@ 2 51_0201_5%
GND_8 GND_9 MIPI60_CFG_STB0_DN <18>
+VCCIO_OUT
SMB_CLK_MIPI60
SAMTE_QSH-030-01-L-D-A MIPI60@ R210 1 2 1K_0201_5% R660 1 MIPI60@ 2 51_0201_5%
SMB_DATA_MIPI60 MIPI60_CFG_STB1_DN <18>
MIPI60@ R311 1 2 1K_0201_5%
R274 1 @ 2 10K_0201_5% MIPI60_MBP0# MIPI60@ R410 1 2 100K_0201_5% MIPI60_OVERRIDE# R137 1 MIPI60@ 2 10K_0201_5% MERGED_TRST_PD
R178 1 @ 2 10K_0201_5% MIPI60_MBP1# MIPI60@ R138 1 2 0_0402_5% V3.3A_CPU_NOA_LA_VAL
C
JESPI APS BIOS UART Debug C
JUART1
UART_2_CRTS_DCTS 1
+3VALW +3V_PRIM <10> UART_2_CRTS_DCTS UART_2_CTXD_DRXD 1
2
UART_2_CRXD_DTXD 3 2
UART_2_CCTS_DRTS 4 3
<10> UART_2_CCTS_DRTS 4
5
6 GND_1
JAPS1 GND_2
1 CVILU_CI1804M1VRA-NH
1
2 CONN@
<11,58,78> SIO_SLP_S3# 2
3
4 3
<11> SIO_SLP_S5# 4
5
<11,58,78> SIO_SLP_S4# 5
Power Button Debug

6
<11> SIO_SLP_A# 6
7
+3V_PRIM 7
8
LPC 80Port +3VS 9 8
Debug <9,63> PCH_RTCRST# 9
LPC ESPI JDEBUG2 10
1
1
<58,63,77,79,94> PWRBTN#
11 10
11
BOT
1 +3VS +3VS 2 12
2 3 13 12
3 ESPI_IO0 <9,58> <11> SYS_RESET# 13
2 +3VS +3VS 4 ESPI_IO1 <9,58> 14
4 5 15 14 SW1
5 ESPI_IO2 <9,58> <11,66> SIO_SLP_S0# 15
3 LPC_LAD0 ESPI_IO0 6 16 3 4
6 ESPI_IO3 <9,58> 16 <58,63,77,79,94> PWRBTN#
7 17
4 LPC_LAD1 ESPI_IO1 7 ESPI_CS# <9,58> 17
8 RE193 2 @ 1 0_0201_5% 18
8 PCH_PLTRST#_EC <11,46,48,52,66,67,70,79> 18
9 RE428 2 1 0_0201_5% 19
5 LPC_LAD2 ESPI_IO2 9 ESPI_RESET# <9,58> GND_1
10 20
10 ESPI_CLK_5105 <9,58> GND_2 1 2
6 LPC_LAD3 ESPI_IO3 ACES_50506-01841-P01
SKRBAAE010_4P
11 CONN@
7 LPC_FRAME# ESPI_CS# GND1 12 DB@
GND2
8 PCH_PLTRST# NA
ACES_50521-01041-P01
Debug LED
9 GND GND CONN@
10 LPC_CLK ESPI_CLK
+3VS +3VS
1
DB@ DB@
R530 R531
200_0201_1% 200_0201_1%
B B
2
2
2
DB@ DB@
DCI Debug
LED1 LED2
HT-F196BP5_WHITE HT-F196BP5_WHITE
1
<58> ALLSYS_PWRGD
<11,46,48,52,66,67,70,79> PCH_PLTRST#_EC
<12> USB3_CTX_DRX_P2
CH44
1 2 USB3_CTX_C_DRX_P2
0.1U_0201_10V6K +5VALWB
JDEBUG1
JDEG1
<12> USB3_CTX_DRX_N2
CH45
1 2 USB3_CTX_C_DRX_N2
0.1U_0201_10V6K
<12>
<12>
USB20_P1
USB20_N1
USB3_CTX_C_DRX_P2
USB3_CTX_C_DRX_N2
1
2
3
4
5
6
1
2
3
4
5
6
EC UART Debug/80 port
7
8 7
9 8 +3VALW
<12> USB3_CRX_DTX_P2 9
10
<12> USB3_CRX_DTX_N2 10
2
2
11
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
12 GND1 RE200
RE210
RE211
RE212
RE213
GND2 10_0201_1%
1
10K_0201_5%
10K_0201_5%
10K_0201_5%
100K_0201_5%
RE204
ACES_50521-01041-P01
1
1
RE201
RE202
RE203
CONN@ JDEG1
1 +EC_DEBUG_VCC
1 2 JTAG_TDI @
JTAG_TMS JTAG_TDI <58>
2
2 3
3 JTAG_CLK JTAG_TMS <58>
4
4 JTAG_TDO JTAG_CLK <58>
5 RE205
5 JTAG_TDO <58>
11 6 MSCLK 10K_0201_5%
G1 6
12 7 MSDATA 1 2
G2 7 8 HOST_DEBUG_TX
8 9 DEBUG_TX
9 10
A 10 1 @ 2 A
<10> SBIOS_TX
ACES_50521-01041-P01_10P
RE206
CONN@
0_0201_5%
HOST_DEBUG_TX <58>
MSDATA <52,58>
MSCLK <52,58>
1 2
RE209
0_0201_5%

2020/10/01 2018/10/01 Title
P079 - Debug APS,DEG,eSPI,LED
5 4 3 2 1
A B C D E
1 1
2 2
3 3
4 4

P080 - Reserved
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H811P 0.1 (X00)

A B C D E
5 4 3 2 1
Modena POWER BLOCK DIAGRAM

D D
Power Rail
2S2P Battery
51W +3.3VALW
Power Trace ALWON_3VALW TDC: 7.3A
B+
Peak Current 10.5A
(NB502)
Page:84
PD1
Type-C Port-L Controller
TPS65987DH
+5VALW
ALWON_5VALW TDC 5.1A
Buck-boost B+ Peak Current 7.3A
Charger (NB502)
C
EC ISL9538C Page:85 C
MEC5105 (NVDC)
Page:83
+5VALWB
ALWON_5VALWB TDC 3.5A
PD2 B+ Peak Current 5A
Type-C Port-R Controller (NB502)
TPS65987DH Page:85
B+ B+ B+
B B
Phase1
VCCIN PWM1 Dr.MOS +1.1V_MEM +1.8VPRIM
TDC 36A MP86902 TDC 4.2A TDC 1.9A
IMVP_VR_ON_EN 1.1V_MEM_EN PCH_PRIM_EN
Peak Current 62A Peak Current 6A Peak Current 2.8A
(MP2940A) PWM2
Phase2 (NB685) (NB691)
Page:91,92,93 Dr.MOS Page:86 Page:88
MP86902
VCCIN_AUX +0.6V_VDDQ (LPDDR4X only)

1.8V_PRIM_PG TDC 10A 0.6V_VDDQ_EN_P TDC 0.5A
Peak Current 26A Peak Current 0.72A
(MP2941) (NB691)
Page:89,90 Page:87
A A

PWR_POWER BLOCK DIAGRAM
0.4 (X02)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G172P
5 4 3 2 1
5 4 3 2 1
DCIN(37.1)
EMC@ PL102
HCB2012KF-800T50_2P
1 2
+VBATT
EMC@ PL103
HCB2012KF-800T50_2P +BATT
Battery
D 1 2 (2S2P) D
EMC@ PL104
HCB2012KF-800T50_2P
1 2 PBAT_CHARGER_SMBCLK <58,83>
1000P_0201_50V7K
100P_0201_50V8J
100P_0201_50V8J
PC133
0.01UF_0402_25V7K
PC132
1M_0402_1%
PC134
PC135
1
2 EMC@ PD104
PR185
1
1
1 TVNST52302AB0_SOT523-3
3
2
EMC@
EMC@
EMC@
EMC@
2
PBAT_CHARGER_SMBDAT <58,83>
2 EMC@ PD105
1TVNST52302AB0_SOT523-3
JBATT1 3
DEREN_40-42507-01001RHF_10P
1
1.BATT+ 1 2
2.BATT+ 2 3
3.BATT+ 3 4 +3.3V_BAT_LDO
CLK_SMB PR195 1 2 100_0402_1%
4.CLK_SMB 4 5 DAT_SMB PR196 1 2 100_0402_1%
5.DAT_SMB 5 6 +3.3V_BAT_LDO_R PR197 1 2 0_0402_5%
6.+3.3V_BAT_LDO 6 7
7.SYS_PRES* 7
8
C
8.GND 8 9 C
9.GND 9 10 SYS_PRES# <94>
10.GND 10 11
11.GND GND_1 12
12.GND GND_2 13
13.GND GND_3 14
14.GND GND_4
CONN@
+3VALW
200K_0201_5%
PR102
1
0_0402_5%
PR101
1 2 CHG_PROCHOT# <83>
+3VALW
2N7002KDW_SOT363-6
200K_0201_5%
1
6
B D B
PR103
PQ100A
G
PR100 S
2
1
0_0402_5%
2N7002KDW_SOT363-6
1 2 AC_DISC# <58>
@ PR104
0_0402_5% 3 D
<42,44> PD_L_R_PROCHOT# 1 2 5
G PQ100B
S
4
@ PR105
0_0402_5%
1 2
A A

PWR DCIN
5 4 3 2 1
A B C D
Charger controller(40.1), Support component(40.2)
@ PT200
+CHG_VIN_20V PAD~D H=1.2mm
+CHG_SRC_20V Low noise MLCC SE00000X210
1
EMC@ PL200 PR200
1 1
1UH_1277AS-H-1R0N-P2_3.3A_30% 0.01_1206_1%
1 2 CHG_VIN_20V 1 4
0.1U_0402_25V6
4.5V 2 3
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
442K_0402_1%
@ PC200
1
@EMC@PC202
@EMC@PC201
0.1U_0402_25V6
PR201
PD200
@ PC203
PC204
PC205
PC206
PC207
PC208
PC209
1
1
SMF4L22A_SOD123FL2
1_0402_1%
1_0402_1%
1
1
PR202
PR203
2
2
CHG_ACIN
2
PC210
4.7U_0402_16V6M
0.1U_0402_25V6
1U_0402_25V6K
1U_0402_25V6K
100K_0402_1%
1 2
1
H=1.2mm
PC211
PR204
B+
1
PC212
PC213
Low noise MLCC SE00000X210
2
2
33U_B3_16VM_R45M
33U_B3_16VM_R45M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
@EMC@ PC224
1 1
@EMC@ PC223
PC214
PC215
PC216
PC217
@ PC221
@ PC222
PC218
PC219
1
1
+ +
0.22U_0603_25V7K
2.2_0603_5%
1
2
1
2 2
PC225
normal
normal
PR205
+CHG_VIN_20V PR206
2
2_1206_5%
2
1 2
1U_0402_25V6K
CHG_BST1
CHG_CSIN
CHG_CSIP
CHG_ADP
PC226
CHG_UG1
1
CHG_LG1
CHG_LX1
PR207 VDD
2 2
4.7_0402_5%
+CHG_VIN_20V PD201 PC227 1 2
Main: ML, 2nd: CLSN
CHG_UG1
CHG_UG2
2
RB520SM-30T2R_EMD2-2 1U_0402_25V6K
2 1 1 2 PC246 Package: 11.5 x 10.3 x 2
1U_0201_6.3V6M Idc=10A, Isat=11A
16
15
14
13
12
11
10
33
B+
9
PD202 PR208 1 2 Rdc=14mohm (Typ.)
RB520SM-30T2R_EMD2-2 5V
2_1206_5%
063T
ADP
CSIP
ASGATE
BOOT1
UGATE1
PHASE1
LGATE1
CSIN
PAD
AON6962_DFN5X6D-8-7
AON6962_DFN5X6D-8-7
2 1 1 2 PC228
2
PC229 VDD CHG_DCIN 17 8 CHG_VDDP
1U_0201_6.3V6M
1 2 PL250
+VBATT
D1
G1
G1
D1
2.2U_0402_6.3V6M DCIN VDDP PR211 PQ202
2.2UH_MHCB06030-2R2M-C1L_10A_20%
1 2 18 7 CHG_LG2 0.005_1206_1% AON7405_DFN8-5
VDD 5V LGATE2
PR210 7 CHG_LX1 1 2 CHG_LX2 7 1 4 +8.4V_BATT+ 1
PQ201
PQ203
CHG_ACIN 19 6 CHG_LX2 1 2 D2/S1 D2/S1 2
ACIN PHASE2 2 3 3 5
S2_1
S2_2
S2_3
S2_3
S2_2
S2_1
2.2_0603_5%
@EMC@PR215
@EMC@PR216
4.7_1206_5%
1
1
4.7_1206_5%
CHG_CMIN CHG_UG2
10U_0603_25V6M
10U_0603_25V6M
PR212 1 2 0_0201_5% 20 5
G2
G2
CMIN UGATE2 PC230
1
PR213 1 2 0_0402_5% CHG_DAT 21 ISL9538BHRTZ-T_TQFN32_4X4 4 CHG_BST2 1 2
<58,82> PBAT_CHARGER_SMBDAT
PC231
PC232
2200P_0402_50V7K
3
4
SDA BOOT2
4700P_0402_25V7K
PR214 1 2 0_0402_5% CHG_CLK 22 3 0.22U_0603_25V7K
<58,82> PBAT_CHARGER_SMBCLK
2
SCL VSYS
1
CHG_LG1
PC234
CHG_BGATE
B+
CHG_LG2
1
CHG_CSOP
PC233
PR217 1 2 75_0402_5% 23 2 PR218
1 SNUB_CHG1
AMON/BMON
<16> VRALERT#_R PROCHOT# CSOP
1 SNUB_CHG2
0_0402_5%
2
BATGONE
24 1 1 2
2
<82> CHG_PROCHOT# ACOK CSON
CMOUT
BGATE
COMP
680P_0402_50V7K
680P_0402_50V7K
PROG
CHG_CSON
PSYS
VBAT
VDD PR220
@EMC@ PC236
@EMC@ PC237
0.1U_0402_25V6
0_0402_5%
1 2 1 2
1_0402_1%
1_0402_1%
@ PC235
1
1
PR219 PU200
PR221
PR222
25
26
27
28
29
30
31
32
3V 100K_0402_5%
<58,63> ACAV_IN
2
0_0201_5% CHG_VBAT1
CHG_PSYS
CHG_BGATE
PR224
L2N7002WT1G_SC70-3
CHG_AMON
93.1K_0402_1%
1M_0402_5%
154K_0402_1%
2
1
PR223 1 2
1
D
PR226
PR225
0_0402_5%
PQ205
1 2 2
<58> AC_DIS
1M_0402_5%
G
1
PR229 1
S @ PC238 PC239 @ PC240

PR227
1U_0402_25V6K 1U_0402_25V6K 1U_0402_25V6K

1 2 1 2 1 2
2-CELL
2
3 CHG_COMP 3
1K_0402_1%
1
PR230
0.01U_0402_16V7K 499_0402_1%
1
10K_0201_5%
For Battery 60% RSOC stop charging in Factory

PR231
1
@ PR232
560P_0402_50V7K
2
@ PC241
1
2
2
0.1U_0402_25V6
2
1
0_0402_5%
0_0402_5%
PR233
PR234
1
1
PC243
PC244
PR236
+VBATT
100_0402_1%
2
1 2
I_SYS
<58,91>
2
@ PC245
0.1U_0402_25V6
I_BATT
I_ADP
2
<58>
<58>
4 4

PWR_Charger
Size Document Number Rev
0.4 (X02)
A B C D
5 4 3 2 1
Controller(35.1), Support component(35.2)
D D
CLM Resistor to GND

Reserved for Placement 7A 0
2018/02/21 VCC MODE2 Set 10A 90K

INT VCC 0 13A 150K
EXT VCC Connect to VIN 16.5A >230K or float
@EMC@ PL309
1
HCB2012KF-800T50_2P 2018/12/26 modify
1 2 PR300 PR1301
B+ H=1.2mm 3.77A/6V 0_0402_5% 150K_0201_1%
EMC@ PL310 Low noise MLCC SE00000X210
+3VALW
HCB2012KF-800T50_2P PR1303 PC300 TDC 7.4A
2
1 2 0_0603_5% 0.22U_0402_16V7K 2018/12/26 modify
BST_3V 1 2 1 2
Main: Cyntec, 2nd:
Peak Current 10.5A
33U_B3_16VM_R45M
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K Package: 6.5 x 6.9 x 30 Min. CL :13(A)
0.1U_0402_25V6
EMC@ PC340
SE00000X210
SE00000X210
EMC@ PC337
1
DVT1_05 Idc=9A, Isat=18A Fsw 700KHz
PC345
PC349
@ PC350
1
1
+
DCR=14mohm (Typ.)
16
11
10
PU300 H=1.2mm
PL308 Low noise MLCC SE00000M020 +3VALWP
MODE2
CLM
BST
2
2
2 1.5UH_PCMC063T-1R5MN_9A_20%
1 9 LX_3V 1 2
VIN SW
2200P_0402_50V7K
2200P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
SE00000M020
SE00000M020
SE00000M020
SE00000M020
SE00000M020
SE00000M020
@EMC@ PC336
@EMC@ PC339
R4 PR1302
PC1335
PC346
PC338
PC344
PC347
PC348
1
1
PR1304 PC305 R1 26.1K_0402_1%
2019/1/07 add 33u*1pcs 768K_0402_1% 220P_0201_25V7K
EN_3V 15 1 2 1 2
2
EN FB_3V
C 13 @ @ C
FB
1
12 NB502GQ-Z_QFN16_3X3 PR307
<78> 3VALW_PG PG
1
499_0402_1%
1
PR309
@ PR308 3 4 R2 30.1K_0402_1% Reserved for EMC
2
150K_0201_5% 3V3 3.6V GND_1 5
+3.3V_ALW2 GND_2 2018/02/21
6
MODE1
2
GND_3
2 7
2
PGND GND_4
NC
1
14
8
PC313
LX_3V
2.2U_0402_6.3V6M
2
1 @ PJP301
@ PR310 1 2
@EMC@ PR301
+3VALWP +3VALW
1
4.7_0805_5%
0_0402_5%
MODE VREF JUMP_43X118
Vo<3V 0.6V
2
Vo>3V 1.8V
State VOUT Fs Resistor to GND
2
M1 Vo<3V 700kHz 0 1
M2 Vo<3V 1000kHz 90K R1= X R2
SN_3V
1000kHz 150K VREF - R2
M3 Vo>=3V
700kHz >230K or float VOUT-VREF R4
M4 Vo>=3V
680P_0603_50V7K
@EMC@ PC341
1
B B
2
PR302
0_0402_5%
1 2 EN_3V
<58,94> ALWON_3VALW
A A

PWR_+3VALW
5 4 3 2 1
5 4 3 2 1
Controller(35.1), Support component(35.2) 2018/12/26 modify

CLM Resistor to GND
7A 0 5VALW
VCC MODE2 Set
0
10A
13A
90K
150K
TDC 5.1A
INT VCC
EXT VCC Connect to VIN 16.5A >230K or float Peak Current 7.3A
EMC@ PL404 OCP 10A
1
HCB2012KF-800T50_2P
1 2 PR400 700kHz
B+ H=1.2mm 0_0402_5% PR401
EMC@ PL400 Low noise MLCC SE00000X210 90.9K_0201_1% PR403 PC400
HCB2012KF-800T50_2P 0_0603_5% 0.22U_0402_16V7K 053T 2018/12/26 modify
2
1 2 BST_5V 1 2 1 2
Main: ML, 2nd: CLSN
D Package: 5.49 x 5.18 x 3 D
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
Idc=7.2A, Isat=11A
33U_B3_16VM_R45M
@EMC@ PC401
@EMC@ PC402
0.1U_0402_25V6
DCR=19.7mohm (Typ.)
16
11
10
1 H=1.2mm +5VALWP
PC403
PC404
1
1
PU400
@ PC432
+ PL401 Low noise MLCC SE00000M020
CLM
BST
MODE2
1.5UH_MMD-05CZN1R5M-V1L_7.2A_20%
2
1 9 LX_5V 1 2
2 VIN SW
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
R4 PR404
PR406 PC405 R1 19.1K_0402_1%
PC406
PC407
PC408
PC409
PC410
PC412
1
1
274K_0402_1% 220P_0201_25V7K
15 1 2 1 2
<58> ALWON_5VALW
2
EN 13 FB_5V
2
FB
1
12 NB502GQ-Z_QFN16_3X3 PR407
<78> 5VALW_PG
1
PG 499_0402_1%
1
PR409
@ PR408 3 4 R2 10K_0402_1%
3.6V
2
150K_0201_5% 3V3 GND_1
5
GND_2 6
MODE1
2
2 GND_3 7
2
PGND GND_4
NC
LX_5V
1
14
8
PC414
1
@EMC@ PR410
2.2U_0402_6.3V6M
4.7_0805_5%
2
+5VALWP
1
MODE VREF
@ PR411 Vo<3V 0.6V +5VALW
0_0402_5% Vo>3V 1.8V @ PJP400
2
1 2
1
2
State VOUT Fs Resistor to GND R1= X R2 JUMP_43X118
680P_0603_50V7K
0 VREF - R2
@EMC@ PC415
M1 Vo<3V 700kHz
C M2 Vo<3V 1000kHz 90K VOUT-VREF R4 C
1
M3 Vo>=3V 1000kHz 150K
M4 Vo>=3V 700kHz >230K or float
2
2018/12/26 modify
CLM Resistor to GND

5VALWB
VCC MODE2 Set
0
7A
10A
0
90K
TDC 3.5A
INT VCC
EXT VCC Connect to VIN 13A 150K Peak Current 5A
EMC@ PL405
HCB2012KF-800T50_2P
16.5A >230K or float OCP 7A
H=1.2mm 1
700kHz
1
1 2
B+ Low noise MLCC SE00000X210 PR412 PR413
EMC@ PL402 0_0402_5% 0_0201_5% PR415 PC416
HCB2012KF-800T50_2P 0_0603_5% 0.22U_0402_16V7K 053T 2018/12/26 modify
1 2 BST_5VB 1 2 1 2
Main: ML, 2nd: CLSN
2
2
Package: 5.49 x 5.18 x 3
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
Idc=7.2A, Isat=11A
33U_B3_16VM_R45M
@EMC@ PC417
@EMC@ PC418
0.1U_0402_25V6
DCR=19.7mohm (Typ.)
16
11
10
1 H=1.2mm +5VALWBP
PC419
PC420
1
PU401
@ PC433
+ PL403 Low noise MLCC SE00000M020

CLM
BST
MODE2
1.5UH_MMD-05CZN1R5M-V1L_7.2A_20%
2
1 9 LX_5VB 1 2
B 2 VIN SW B
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
R4 PR416
PR418 PC421 R1 19.1K_0402_1%
PC423
PC424
PC425
PC426
PC422
PC428
1
1
274K_0402_1% 220P_0201_25V7K
15 1 2 1 2
<58> ALWON_5VALWB
2
EN 13 FB_5VB
2
1
FB
12 NB502GQ-Z_QFN16_3X3 PR419
<78> 5VALWB_PG PG
1
499_0402_1%
1
PR421
@ PR420 3 4 R2 10K_0402_1%
3.6V
2
150K_0201_5% 3V3 GND_1 5
GND_2 6
MODE1
2
GND_3
2 7
2
PGND GND_4
NC
LX_5VB
1
14
PC430
2.2U_0402_6.3V6M
2
1
@EMC@ PR422
4.7_0805_5%
@ PR423 +5VALWBP
0_0402_5% MODE VREF +5VALWB
Vo<3V 0.6V @ PJP401
Vo>3V 1.8V 1 2
2
State VOUT Fs Resistor to GND

M1 Vo<3V 700kHz 0 1 JUMP_43X118
M2 Vo<3V 1000kHz 90K R1= X R2
680P_0603_50V7K
150K VREF - R2
@EMC@ PC431
M3 Vo>=3V 1000kHz
M4 700kHz >230K or float VOUT-VREF R4
Vo>=3V
2 1
A A

PWR_+5VALW/+5VALWB
0.4 (X02)
5 4 3 2 1
5 4 3 2 1
2018/12/26 modify
D
+1.1V_MEM D
TDC 4.2A
Peak Current 6A
053T 2018/12/26 modify
Min. CL 12A
Main: ML, 2nd: CLSN Fsw 700KHz
Package: 5.3 x 4.7 x 3
Reserved for OT PR700 PC700 Idc=8.5A, Isat=14A
2018/02/21 0_0603_5% 0.22U_0402_25V6K
BST_1.1V_MEM_R 2
DCR=11mohm (Typ.)
1 2 1
H=1.2mm
BST_1.1V_MEM
@ PR702 PL702
+1.1V_MEMP
Low noise MLCC SE00000M020
0_0402_5% 0.68UH_MMD-05CZ-R68M-X2L_8.5A_20%
1 2 OT_1.1V_MEM LX_1.1V_MEM 1 2
<11,16,58,91> H_PROCHOT#
16.9K_0402_1%
Check this connection
220P_0402_50V8J
2200P_0402_50V7K
2200P_0402_50V7K
FB_1.1V_MEM
PC702
PR703
@EMC@ PC708
@EMC@ PC704
1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
SE00000M020
SE00000M020
SE00000M020
SE00000M020
SE00000M020
1
11
10
13
PC705
PC706
PC703
PC707
PC751
9
1
PU700
H=1.2mm
2
OTW
SW
FB
BST
2
EMC@ PL701 Low noise MLCC SE00000X210 1.23A/6V
2
HCB2012KF-800T50_2P @
1 2 B+_1.1V_MEM 1 6 +1.1V_MEMP
B+ VIN VDDQ
Vout = 0.6 x (1+ R1/R2)
1
10U_0603_25V6M
10U_0603_25V6M
20K_0402_1%
2200P_0402_25V7K
0.1U_0402_25V6
SE00000X210
SE00000X210
PC710
PC711
PR704
C EN1_1.1V_MEM 16 5 C
PC750
PC709
EN1 VTT
1
NB685GQ-Z_QFN16_3X3
2
2
2
EMC@
EMC@
EN2_1.1V_MEM 15 8 VTT_1.1V_MEM
EN2 VTTS
2018/12/26 modify
0.22U_0402_10V6K
12 7 REF_1.1V_MEM +1.1V_MEMP +1.1V_MEM
PG VTTREF
PC713
MODE
AGND
PGND
0.22U_0402_10V6K
@ PJP700
3V3
1 2
LX_1.1V_MEM
2
1 2
PC714
JUMP_43X79
14
2
PR706
0_0402_5%
MODE_1.1V_MEM
@EMC@ PR701
1 2
1
3V3_1.1V_MEM
4.7_0805_5%
0_0402_5%
1U_0402_16V6K
1
2
PR708
1
PC715
PR709
SN_1.1V_MEM
0_0402_5%
0_0402_5%
1
1 2
<25,78> 1.1V_MEM_EN
PR707
680P_0603_50V7K
2
@EMC@ PC701
1
B B
2
<25> 1.1V_MEM_PG
+3VALW R MODE = 0 ohm
2
Fsw = 700KHz
Mode EN1 EN2 VDDQ VTT

S0 H H on on
S3 L H on off
S4/S5 L L off off
Note: S3 - sleep ; S5 - power off
A A

PWR_+1.1V_MEM
5 4 3 2 1
5 4 3 2 1
D D
2018/12/26 modify
0.6V_VDDQ
TDC 0.5A
Peak Current 0.72A
Min. CL :6.5(A)
B+ EMC@ PL800
<25> 0.6V_VDDQ_EN_P
750kHz
HCB1608KF-121T30_0603
1 2 PR801 PC801
0_0603_5% 0.22U_0402_16V7K 2018/12/26 modify
2200P_0402_25V7K
BST_0.6V 1
0.1U_0402_25V6
10U_0603_25V6M
10U_0603_25V6M
2 1 2
Main: CLSN, 2nd: CLSN
Package: 3.2 x 1.5 x 1.2
PC802
PC803
EMC@ PC804
EMC@ PC805
1
1
Idc=3.7A, Isat=5.7A
DCR=27.5mohm (Typ.) +0.6V_VDDQP
11
2
7
C PU800 C
PL801
EN
BST
1UH_HEI322512A-1R0M-Q8_3.7A_20%
1 6 LX_0.6V 1 2
VIN SW
220P_0402_50V8J
1
@ PC812
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR803
0_0402_5%
PC806
PC807
PC808
PC809
1
1
NB691GG-Z_QFN11_2X2
2
5 SA0000BDK00
2
<25> 0.6V_VDDQ_PG PG FB_0.6V
10
2
FB
1
1
@ PR802
150K_0201_5% 2018/12/26 modify @ PR805
8 2 0_0402_5%
VCC 3.6V PGND_1
AGND
3
1 LX_0.6V
2
PGND_2
4
2
PGND_3
@EMC@ PR804
1
9
PC810 2018/12/26 modify
680P_0402_50V7K 4.7_0603_5%
2.2U_0402_6.3V6M
2
2
@EMC@ PC811
1
B +0.6V_VDDQP B
2
+0.6V_VDDQ
@ PJP800
1 2
1 2
JUMP_43X79
A A

PWR_VDDQ4x
5 4 3 2 1
5 4 3 2 1
D D
2018/12/26 modify
2018/12/26 modify 1.8V_PRIM

B+ <16> PCH_PRIM_EN
PR507
Main: CLSN, 2nd: TDC 1.9A
EMC@ PL501 0_0603_5%
HCB1608KF-121T30_0603 1 2 Package: 6.6 x 6.95 x 1.0 Peak Current 2.8A
1 2 Idc=6A, Isat=7.5A Min. CL :6.5(A)
BST_1.8V
Rdc=25mohm (Typ.)
0.22U_0402_16V7K
750kHz
2200P_0402_25V7K
1
0.1U_0402_25V6
10U_0603_25V6M
10U_0603_25V6M
C C
PC500
PC501
PC502
EMC@ PC503
EMC@ PC504
1
1
PL555
2
1UH_MHCI06012-1R0M-R8A_6A_20%
LX_1.8V 1 2 +1.8V_PRIMP
11
2
7
PU500
+3VALW @ PR510 PC505
EN
BST
274K_0402_1% 220P_0201_25V7K
1 6 1 2 1 2
VIN SW
1
20K_0402_1% 40.2K_0402_1%
PR509
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
100K_0201_5% PR501
PR502
499_0402_1% R1
PC506
PC507
PC508
@ PC509
1
1
NB691GG-Z_QFN11_2X2
2
5 SA0000BDK00
2
<58,89> 1.8V_PRIM_PG PG FB_1.8V
10
2
FB
1
1
@ PR503
150K_0201_5%
PR504
8 2
LX_1.8V
VCC 3.6V PGND_1
AGND
3 R2
2
PGND_2
4
2
PGND_3
1
1
@EMC@ PR506
PC510
4.7_0805_5%
2.2U_0402_6.3V6M
2
VOUT-0.6
R1= X R2
0.6
2
B B
680P_0603_50V7K
@EMC@ PC512
1
+1.8V_PRIMP
+1.8V_PRIM
2
JUMP_43X118
1 2
@ PJP500
A A

PWR_+1.8VPRIM
5 4 3 2 1
5 4 3 2 1
D D
EMC@ PL902
HCB2012KF-800T50_2P 2018/12/26 modify
1 2
B+ VCCIN_AUX (Base on PDG rev 0.71)
EMC@ PL903 VIN_AUX
HCB2012KF-800T50_2P Peak Current 32A (ICCmax)
1 2
X6S type TDC :14A
DC Load line :TBD mV/A
+3VALW AC Load line :TBD mV/A
PR900 PC900 2018/12/26 modify
OCP Current 32A
1
5.1_0402_1% 1U_0402_16VAK
1 2 1 2 2018/12/26 modify Fsw=700kHz
PR901 PR902 PC901
90.9K_0201_1% 2.2_0603_5% 1U_0402_25V6K
Main: ML, 2nd:
X6S, H=1.2mm BST1_AUX 1 2 1 2 Package: 5.49 x 5.18 x 1.2
2
Low noise MLCC SE00001BM10 Idc=12A, Isat=20A
VIN_AUX Rdc=5.9mohm(Typ.)
2018/12/26 delete X6S type
18
19
13
+VCCIN_AUX
7
33U_B3_16VM_R45M
1U_0402_16VAK
PL900
3V3
PGND_4
BST1
FS
10U_0603_16VAM
10U_0603_16VAM
10U_0603_16VAM
10U_0603_16VAM
10U_0603_16VAM
10U_0603_16VAM
0.15UH_MMD-05AB-R15M-T1L_12A_20%
1
PC909
1
2 12 LX1_AUX 1 2
PC903
PC904
PC905
PC902
C@ PC906
PC907
C@ PC908
VIN SW1
1
1
+ PL901
0.15UH_MMD-05AB-R15M-T1L_12A_20%
1
1 11 LX2_AUX 1 2
2
2
C 2 PGND_1 SW2 PR904 PC910 PR903 C
2.2_0603_5% 1U_0402_25V6K 100_0201_1%
3 10 BST2_AUX 1 2 1 2
PGND_2 PU900 BST2 PR915
2
MP2941GL-Z_QFN19_3X4 0_0402_5%
4 16 VCCIN_AUX_VCCSENSE_VR 1 2
PGND_3 SA0000BJK10 VOUT VCCIN_AUX_VCCSENSE <16>
5 17 VCCIN_AUX_VSSSENSE_VR 1 2
<16,78> CORE_VID1 VID1 RGND VCCIN_AUX_VSSSENSE <16>
1
PR916
6 9 0_0402_5% PR906
<16,78> CORE_VID0 VID0 PG VCCIN_AUX_VR_PG <58>
100_0201_1%
MODE
LX1_AUX
CLM
EN
2
8
14
15
PR912
1
@EMC@ PR910
0_0201_5%
4.7_0805_5%
1 2 2018/12/26 modify
1
<58,88> 1.8V_PRIM_PG
0.1U_0201_25V6K
@ PR907
0_0201_5% PR908
2
@ PC911
90.9K_0201_1%
680P_0603_50V7K
2
@EMC@ PC912
1
B B
2
Table---1:VID control Bit logics Table---2:CLM Select Table---3:MODE Select Table---4:FS Select
VID1 VID0 VOUT(V) State CLM Resistor to GND State Interleaving VID Down option Resistor to GND State Fs(kHz) Resistor to GND
0 0 0 M1 7A 0 M1 N Slew down 0 M1 500 0
0 1 1.1 M2 10A 90k M2 Y Slew down 90k M2 700 90k
1 0 1.65 M3 13A 150k M3 Y Decay 150k M3 1000 150k
1 1 1.8 M4 16A >230k or float M4 N Decay >230k or float M4 1200 >230k or float
A A

PWR_VCCIN_AUX
5 4 3 2 1
A
B
C
D
5
5
2 1 2 1
Support component(36.4)
2
1
+
2 1 PC1031 PC1014 PC1000
Backside
10U_0402_6.3V6M 10U_0402_6.3V6M 150U_B3_6.3VM_R35M
+VCCIN_AUX
@ PC1040 2 1 2 1
2
1
+
1U_0201_6.3V6M
Primary side
+VCCIN_AUX
2 1 PC1032 PC1015 PC1001
10U_0402_6.3V6M 10U_0402_6.3V6M 150U_B3_6.3VM_R35M
@ PC1041 2 1 2 1
2
1
+
1U_0201_6.3V6M
2 1 PC1033 PC1016 PC1002
10U_0402_6.3V6M 10U_0402_6.3V6M 150U_B3_6.3VM_R35M
@ PC1042 2 1 2 1
2
1
+
1U_0201_6.3V6M
2 1 PC1034 PC1017 PC1050
10U_0402_6.3V6M 10U_0402_6.3V6M 150U_B3_6.3VM_R35M
@ PC1043 2 1 2 1
1U_0201_6.3V6M
2 1 PC1035 PC1018
10U_0402_6.3V6M 10U_0402_6.3V6M
@ PC1044 2 1 2 1
1U_0201_6.3V6M
PC1036 PC1019
10U_0402_6.3V6M 10U_0402_6.3V6M
4
4
2 1 2 1
PC1037 PC1020
10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1
H=0.8mm
@ PC1038 top_side PC1021

2 1 10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1
@ PC1045
0.1U_0201_6.3V6K @ PC1039 PC1022
+VCCIN_AUX
2 1 10U_0402_6.3V6M 10U_0402_6.3V6M
2 1
Low noise MLCC SE00000UD10
@ PC1046
0.1U_0201_6.3V6K PC1023
12/18 unmount PC1308 & PC1309

2 1 10U_0402_6.3V6M
@ PC1047
0.1U_0201_6.3V6K
2 1
@ PC1048
0.1U_0201_6.3V6K
2 1
Issued Date
@ PC1049
0.1U_0201_6.3V6K
Security Classification
2 1 2 1
0.8mm PC1024 0.8mm PC1004

22U_0603_6.3V6M 22U_0603_6.3V6M
+VCCIN_AUX
2 1 2 1
3
3
0.8mm PC1025 0.8mm PC1005

22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PC1026 PC1006
2017/08/24
47U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
H=1.2mm
0.8mm PC1027 PC1007

22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PC1028 0.8mm PC1008

47U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
Low noise MLCC SE00000M020
PC1029 0.8mm PC1009

47U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PC1030 0.8mm PC1010
Compal Secret Data

47U_0603_6.3V6M 22U_0603_6.3V6M
Deciphered Date
2 1
0.8mm PC1011
22U_0603_6.3V6M
1U_0201 * 5 (NC*5)
2 1
0.1U_0201 * 5 (NC*5)
PC1012
22U_0603_6.3V6M
2 1
H=1.2mm
2
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
150U_B3 * 4 (POP*2, NC*2)
47U_0603 * 7 (POP*1, NC*6)
PC1013
22U_0603 * 10 (POP*1, NC*9)
2017/08/24
22U_0603_6.3V6M
10U_0402 * 19 (POP*14, NC*5)
Low noise MLCC SE000015510
Size
Title
Date:
1x 47uF 0805
3x 22uF 0603
2x 330uF 7343
12x 10uF 0402
Document Number
LA-G172P
Monday, January 28, 2019
1
1
Sheet
PDG ver 1.1 Primary side:
90
Compal Electronics, Inc.
of
100
PWR_DECOUPLING-VCCIN_AUX
Rev
A
B
C
D
0.4 (X02)
5 4 3 2 1
VCCIN (Base on PDG rev 0.71)

Peak Current 54A (ICCmax)
TDC :25A
DC Load line :2mV/A
D AC Load line :4mV/A D
OCP Current TBDA
Fsw=800kHz
<92> VRACPU_VTEMP
+3VALW
1
PR1101
1
49.9K_0402_1% PC1100
2.2U_0402_6.3V6M PR1102
2
4.7_0402_5%
2
PR1103
0_0201_5%
2
<58,83> I_SYS 1 2
6.8K_0402_1%
1
1
1000P_0402_25V8J
PC1101
CPU_B+Psys=45+52*2C=149W
PR1100
PC1102
1
4.7U_0402_6.3V6M
2
1 2
2
2
PR1104
2M_0402_1% PWM1 <92>
2018/12/26 modify IMVP_VR_ON_EN <78>
PWM2 <92>
C C
CSSUM
0.1U_0402_25V7K
133K_0402_1%
1.5K_0402_1%
1.5K_0402_1%
+3VALW +1.05V_VCCSTG +3VALW
1
28
27
26
25
24
23
22
PC1104
1
PR1108
PU1100
PR1106
PR1107
10K_0201_5%
VDD33
PWM1
PWM2
PWM3
VIN_SEN
PSYS
TEMP
1
@ PR1111
2
1.91K_0402_1%
10K_0201_5%
10K_0201_5%
10K_0201_5%
2
1
@ PR1109
@ PR1112
@ PR1113
@ PR1114
1 3.3V 21 PR1115
PR1110 CS3 EN
0_0402_5% 0_0201_5%
2
<92> CS2 1 2 2 20 PE 1 2
CS2 PE
2
<92> CS1 1 2 3 19
CS1 MP2940AGRT-0010-Z_TQFN28_4X4 STB SYNC <92>
PR1116
+VCCIN 0_0402_5% @ PC1105
390P_0402_50V7K
@ PR1120
4.99K_0402_1%
PR1117 1 2 806_0402_1% 4
VDIFF SA0000BDI10 SCL_P
18 IMVP_SMBCLK_VR @ PR1118 1 2 0_0402_5%
IMVP_SMBCLK <58>
1 2 1 2 1 2 5 17 IMVP_SMBDAT_VR @ PR1121 1 2 0_0402_5%
VFB SDA_P IMVP_SMBDAT <58>
@ PC1103 150P_0402_50V8J
PR1119
1 2 VFB 6 16 PR1123 1 2 75_0402_5%
VOSEN VRHOT# H_PROCHOT# <11,16,58,86>
100_0201_1%
1 2 VCCIN_SENSE_VR 7 15 PR1125 1 2 0_0201_5%
<14> VCCIN_SENSE 1.8V PCH_PWROK_P <11>
SCLK/VID0
VORTN VRRDY
SDIO/VID1
PR1122 0_0402_5%
VSSIN_SENSE_VR +1.05V_VCCST
CSSUM
1 2
VDD18
<14> VSSIN_SENSE
AGND
IMON
PR1124 0_0402_5%
ALT#
IREF
PR1126
1 2
100_0201_1%
45.3_0402_1%
45.3_0402_1%
1
1
100_0402_1%
@ PR1127
PR1128
PR1129
8
10
11
12
13
14
29
PC1106
B 0.1U_0201_25V6K B
2
CSSUM
2
SVID_ALERT#_VR PR1130 1
VDD18
2 0_0402_5%
SVID_ALERT# <14>
IMON
SVID_DAT_VR PR1131 1 2 0_0402_5%
SVID_DAT <14>
330P_0402_50V8J
60.4K_0402_1%
61.9K_0402_1%
1
SVID_CLK_VR PR1132 1 2 0_0402_5%

PR1133
PC1107
PR1134
SVID_CLK <14>
1
PC1108
2.2U_0402_6.3V6M
2
2
2
A A

PWR_VCCIN_CTRL
5 4 3 2 1
5 4 3 2 1
2018/12/26 modify
Support component(36.2),(36.3) VCCIN (Base on PDG rev 0.71)

Peak Current 62A (ICCmax)
PL2 TDC :36A
DC Load line :2mV/A
AC Load line :4mV/A
OCP Current TBDA
D Fsw=800kHz D
CPU_B+ X6S, H=1.2mm

Low noise MLCC SE00001BM10
X6S type
1000P_0402_50V7K
0.1U_0402_25V6
10U_0603_25V6M
10U_0603_25V6M
1U_0402_16VAK
10U_0603_16VAM
+3VS
EMC@ PC1200
EMC@ PC1201
PU1200
PR1200
PC1202
PC1203
PC1204
C@ PC1222
1
1
0_0402_5% X6S type 2019/01/14 modify
1 2 14 1
VCC VIN
8
Main: TAI, 2nd:
Package: 6.7 x 7.3 x 2.8
2
VIN
1
1U_0402_16VAK
PC1207 Idc=37A, Isat=41A
PC1206
normal
normal
0.22U_0603_25V7K Rdc=0.9mohm (Typ.)
2
13 15 BST1_VCCIN 1 2
AGND BST
EMC@ PL1202 PL1200
+VCCIN
HCB2012KF-800T50_2P 0.15UH_TMPC0603H-R15M_37A_20%
1 2 2 LX1_VCCIN 1 4
SW
9 3
<91> PWM1 PWM SW
EMC@ PL1203 4 2 3
@EMC@ PR1201
PR1204 SW
HCB2012KF-800T50_2P 1 2 11
4.7_1206_5%
<91,92> VRACPU_VTEMP VTEMP/FLT
1
1 2 0_0201_5%
10 5
<91,92> SYNC SYNC PGND
EMC@ PL1204 6
HCB2012KF-800T50_2P PGND
12 7
<91> CS1 CS PGND
B+ 1 2
2
C
EMC@ PL1205
CPU_B+ MP86902-BGLT-Z_TQFN21-15_3X4
C
680P_0603_50V7K
HCB2012KF-800T50_2P 12/18 add 3pcs
@EMC@ PC1208
1 2
1
33U_B3_16VM_R45M
33U_B3_16VM_R45M
33U_B3_16VM_R45M
33U_B3_16VM_R45M
33U_B3_16VM_R45M
33U_B3_16VM_R45M
33U_B3_16VM_R45M
2
1 1 1 1 1 1 1
PC1209
PC1210
PC1211
PC1212
C@ PC1341
C@ PC1342
C@ PC1343
+ + + + + + +
2 2 2 2 2 2 2
CPU_B+ X6S, H=1.2mm

Low noise MLCC SE00001BM10
X6S type
1000P_0402_50V7K
0.1U_0402_25V6
10U_0603_25V6M
10U_0603_25V6M
1U_0402_16VAK
10U_0603_16VAM
+3VS
EMC@ PC1213
EMC@ PC1214
B PU1201 2019/01/14 modify B

PR1202
PC1215
PC1216
PC1217
C@ PC1223
1
0_0402_5% X6S type Main: TAI, 2nd:

1 2 14 1
VCC VIN
8 Package: 6.7 x 7.3 x 2.8
2
VIN
1
Idc=37A, Isat=41A
1U_0402_16VAK PC1220 Rdc=0.9mohm (Typ.)
PC1219
normal
normal
2 0.22U_0603_25V7K
13 15 BST2_VCCIN 1 2
AGND BST
PL1201
+VCCIN
0.15UH_TMPC0603H-R15M_37A_20%
2 LX2_VCCIN 1 4
SW
9 3
<91> PWM2 PWM SW 4 2 3
@EMC@ PR1203
PR1205 SW
1 2 11
4.7_1206_5%
<91,92> VRACPU_VTEMP VTEMP/FLT
1
0_0201_5%
10 5
<91,92> SYNC SYNC PGND
6
PGND
12 7
<91> CS2 CS PGND
2
MP86902-BGLT-Z_TQFN21-15_3X4
680P_0603_50V7K
@EMC@ PC1221
2 1
A A

PWR_VCCIN_Driver MOS
5 4 3 2 1
5 4 3 2 1
150U_B3 * 4 (pop*2, NC*2)

D
10U_0402 * 8 (pop*4, NC*4) PDG ver 1.1 Primary side: D
Primary side 22U_0603 * 8 (pop*7, NC*1)

47U_0603 * 2 (NC*2)
2x 1uF 0402
+VCCIN 1U0402 * 2 4x 10uF 0402
1U_0201 * 5 (NC*5)
12/18 add 2pcs For no CPU debug 0.1U_0201 * 5 (NC*5) 8x 22uF 0603
150U_B3_6.3VM_R35M
1x 47uF 0805
150U_B3_6.3VM_R35M
150U_B3_6.3VM_R35M
150U_B3_6.3VM_R35M
150U_B3_6.3VM_R35M
150U_B3_6.3VM_R35M
+VCCIN H=1.2mm
2x 330uF 7343
1
1 1 1 1 1 1 Low noise MLCC SE00000M020
@ PR1300
PC1300
PC1301
PC1302
PC1334
C@ PC1336
C@ PC1337
+ + + + + + 1K_0402_5%
22U_0603_6.3V6M
2
2 2 2 2 2 2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC1304
PC1305
PC1306
0.8mm PC1307
PC1308
0.8mm PC1309
0.8mm PC1310
0.8mm PC1311
1
1
2
2
12/18 unmount PC1315 & PC1314
C C
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
PC1312
PC1313
PC1314
PC1315
@ PC1316
@ PC1317
@ PC1318
@ PC1319
1
47U_0603_6.3V6M
22U_0603_6.3V6M
2
PC1320
0.8mm PC1321
1
1
2
2
H=1.2mm
H=0.8mm Low noise MLCC SE000015510
Low noise MLCC SE00000UD10
1U_0402_6.3V6K
1U_0402_6.3V6K
@ PC1322
@ PC1323
1
1
2
B B
Backside
+VCCIN +VCCIN
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
@ PC1324
@ PC1325
@ PC1326
@ PC1327
@ PC1328
@ PC1329
@ PC1330
@ PC1331
@ PC1332
@ PC1333
1
1
2
A A

PWR_DECOUPLING-VCCIN
5 4 3 2 1
5 4 3 2 1
D D
DVT1_02
+3V_NB_LID
+3VALW
PD603
2 1
+3.3V_BAT_LDO RB520SM-30T2R_EMD2-2
PD604
2 1
BAT54HT1G_SOD323-2
C C
1
1
PR602
B+ @ PR606 549K_0402_1%
1
100K_0402_5%
1
2
@ PR601
PU600
PR600
2
100K_0402_5% SN74LVC1G123DCUR_VSSOP8
100K_0402_5%
1
A# 1 8
2
A# VCC PC600
2
1
B 2 7 4.7U_0402_6.3V6M
2
B R/CEXT
PR603
100K_0402_5% 3 6
CLR# CEXT
4 5 SYS_PRES# <82>
2
GND Q
1
1
2 PQ600
G L2N7002WT1G_SC70-3
S PR605
3
1M_0402_5%
1
2
PR604
100K_0402_5%
2
@ PD600
1 2 PR607
B <58,63,77,79> PWRBTN# B
0_0402_5%
1 2 A#
@ PD601
<58> LID_POWER_ON# 1 2
PR608
@ PD602 0_0402_5%
RB520SM-30T2R_EMD2-2 <58,84> ALWON_3VALW
1 2 B
<58,63> BATBTN# 1 2
<63> B+_FLAG_R
A A

PWR_SHIP_MODE
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

RESERVE
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

RESERVE
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

RESERVE
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

RESERVE
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

RESERVE
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

RESERVE
5 4 3 2 1

LA-H811P Seite 5

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A B C D E

MODEL NAME : Modena

SA0000CJ90L SA0000CJD1L SA0000CJ50L SA0000CJW0L

WLAN Option TPM Option

M.2 SSD-Key M PCIe Gen3 x 4lanes PCIe#9,10,11,12

LPDDR4x 8/16/32 GB X32x4 Memory Down

TPS65987-DH p.46,47 RT SPI USB2#8 DMIC FPC

Fingerprint Controller USB2.0

DCI Debug JESPI Debug

RT Programmer PWM LNG2DMTR 4

VCCIN Controller SMBUS PWM#1 Fan 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Monday, January 28, 2019 Sheet 2 of 100

Board ID Table PCIE/USB3.1

SMBUS Control Table Check

PCI-E#6 / USB 3.1#6

USB 2.0 CLK Thunderbolt 1

USB 2.0 PORT# DESTINATION DIFFERENTIAL DESTINATION TBT PORT# DESTINATION

1 USB DCI Debug CLKOUT_PCIE0 WLAN 0 USB Type-C_L

2 None CLKOUT_PCIE1 M.2 SSD TBT 1 None

3 None CLKOUT_PCIE2 None 2 USB Type-C_R

4 Type-C_R CLKOUT_PCIE3 None 3 None

6 None CLKOUT_PCIE5 None

: means Digital Ground

: means Analog Ground

Security Classification Compal Secret Data Compal Electronics, Inc.

Power Rail Modena POWER BLOCK DIAGRAM

VCCIN_AUX UT2 3.3V_TBT_R_EN

Q15 EN_INVPW R U60 RUN_ON_P

U36 AUD_PW R_EN

Security Classification Compal Secret Data Compal Electronics, Inc.

Power On Sequence Power Down Sequence

[AC in] for VBU_L/VBU_R [Battery only, AC absent]

ITEM Measure Point Time

Security Classification Compal Secret Data Compal Electronics, Inc.

HIGH 3.3V HIGH 3.3V

PLACE CLOSE TO THE SIGNAL TO AVOID STUB

Security Classification Compal Secret Data Compal Electronics, Inc.

Memory connection refer 573975 Rev1P1

CA48 LP4(NIL) / DDR4(NIL) LP4(NIL) / DDR4(NIL) BL48

@ Control Buf f er us e , L PDDR4/x don' t us e. CC740 @

Security Classification Compal Secret Data Compal Electronics, Inc.

Memory connection refer 573975 Rev1P1

LP4(NIL) / DDR4(NIL) LP4(NIL) / DDR4(NIL)

Security Classification Compal Secret Data Compal Electronics, Inc.

0 = Enable 0 = Enable 0 = Enable 0 = TLS CONFIDENTIALITY DISABLE 0 = Enable eSPI. (Default)

RH643 1 2 100K_0201_5% RH141 1 2 100K_0201_5% RH635 1 2 100K_0201_5% RH666 1 @ 2 4.7K_0201_5%

SOC_SPI_0_CLK_R RH719 1 2 4.99_0201_1% SOC_SPI_0_CLK DB42

PCH SPI RF Request

NPI pop D20 JSPI1 2

MP pop RC745 SOC_SPI_0_CS#1_R

SPI ROM ( 32MByte )

ROM is Quad SPI

Security Classification Compal Secret Data Compal Electronics, Inc.

RC222 2 1 49.9K_0201_1% UART_2_CRXD_DTXD

NRB_BIT RH621 1 @ 2 4.7K_0201_5% GPP_B23 RH647 1 @ 2 4.7K_0201_5% SPKR RH667 1 @ 2 8.2K_0201_5%

RH300 1 2 10K_0201_5% PCH_TBT_PERST# +1.8VS

DDR_CHA_EN RH738 1 @ 2 100K_0201_5%

DDR_CHA_EN RH740 1 @ 2 100K_0201_5%

CAM_DET# need to reserve pull high <39>

CNV_RF_RESET# <52> CNV_RF_RESET#

1 1 1 1 = DISABLE (ME can update)

Security Classification Compal Secret Data Compal Electronics, Inc.