Fundamental Logic Circuits

LAB WORK 1
FUNDAMENTAL LOGIC CIRCUITS
1. The purpose of the paper
The operation of the fundamental logical gates is studied experimentally: NOT , AND ,
NAND, OR, NOR, XOR, COINCIDENCE (NXOR) and their use in the implementation of some
elementary Boolean functions. The operation of simple combinational circuits is analyzed and
verified, establishing the connections between Boolean algebra and the fundamental logic gates.
We show the functionality of a TTL logic gate, which performs the NAND logic function.

2. Theoretical considerations
Boolean algebra is a symbolic tool for dealing with formal logical functions. It has
established itself as the most important mathematical means of analysis and synthesis of
switching circuits, because we can find the following analogies between formal logic and
switching circuits:

- logic studies the true or false value of statements.

- the switching circuits are made by interconnecting some switches, and their state can only
be closed or open.

2.1. Basic concepts

A Boolean function is a function of n variables y = f (x1, x2,…, xn) defined by the relation:

The function f will correspond to each element of the n-dimensional Cartesian product the
values 0 or 1.
Boolean functions can be used to describe the operation of devices built with two-state
circuit elements. The latter can be implemented through a closed or open switch, through a
blocked or conducting transistor, etc.
The way in which such a circuit element operates will be described by a Boolean variable x i
as shown in Figure 1.
Elementary Boolean functions are Boolean functions of one or two variables and describe the
operation of fundamental logic circuits. A logic gate is a circuit that performs an elementary
Boolean function.

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Fundamental Logic Circuits

Figure 2 Description of a 2-state circuit element using a Boolean

variable xi
In order to perform the Boolean functions with electronic circuits, it is necessary to
correspond the values of an electrical physical quality (voltage or current) with the elements of
the set {0,1} or {False, True}. The 2 values are implemented or represented by 2 disjoint
domains of the chosen physical quality.

Figure 1 Representation of Boolean

variables by voltages

The situation in which the maximum voltage values correspond to logical "1", and the
minimum to logical "0", defines what is called positive logic.
The situation in which the maximum voltage values correspond to logical "0", and the
minimum to logical "1", defines the negative logic.
1 or H (high) 1 or L (low)
0 or L (low) 0 or H (high)
Positive logic Negative logic
Figure 3 Voltage for logical levels

OBSERVATION:
Changing the convention is equivalent to the negation of Boolean variables. Next we will
work in positive logic.

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Fundamental Logic Circuits

2.2. Implementation technologies

Logic circuits can be classified according to the physical implementation technology (see the
appendix of the paper):
a) TTL (Transistor-Transistor Logic) logic circuits:
- standard TTL logic circuits;
- low-power TTL logic circuits;
- fast TTL logic circuits;
- Schottky TTL logic circuits.
b) logic circuits with MOS (Metal Oxide Semiconductor) transistors:
- MOS logic circuits;
- CMOS logic circuit (Complementary MOS).

Logic circuits can also be classified by output type:

- contretemps output;
- output with empty collector;
- 3-state output (tri-state).
The last two types of logic circuits are the most used to implement buses.

2.3. Elementary logic gates

2.3.1. NOT gate
The NOT gate (inverter) is defined by the elementary Boolean function of one variable: f (a) = 𝑎̅.
The function symbol is shown in Figure 4, and the truth table in Table 1.

Figure 4 NOT Logic gate symbol

Table 1 Truth table for the logical function NOT

2.3.2. AND gate

The output of the AND circuit with 2 inputs is defined by the Boolean function: f (a, b) =
a • b. The function symbol is shown in Figure 5, and the truth table in Table 2.

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Fundamental Logic Circuits

Figure 5 AND Logic gate symbol

Table 2 Truth table for the logical function AND

2.3.3. NAND gate

The Boolean function that describes the operation of the NAND circuit is:
̅̅̅̅̅̅̅̅
f (a, b) = 𝑎 • 𝑏. The symbol of the function is shown in figure 6, and the truth table in Table 3.

Figure 6 NAND Logic gate symbol

Table 3 Truth table for the logical function NAND

OBSERVATION: This gate can be implemented using an inverter and an AND gate as follows:

Figure 7 Implementing the NAND logic gate

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Fundamental Logic Circuits

2.3.4. OR gate
The output of the OR circuit with 2 inputs a and b is defined by the Boolean function:
f (a, b) = a + b. The function symbol is shown in Figure 8, and the truth table in Table 4.

Figure 8 OR Logic gate symbol

Table 4 Truth table for the logical function OR

2.3.5. NOR gate

The Boolean function that describes the operation of the ONR gate is: f (a, b) = ̅̅̅̅̅̅̅̅
𝑎 + 𝑏.
The function symbol is shown in Figure 9, and the truth table in Table 5.

Figure 9 NOR Logic gate symbol

Table 5 Truth table for the logical function NOR

OBSERVATION: This gate can be implemented using an inverter and an OR gate as follows:

Figure 10 Implementing the NOR logic gate

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Fundamental Logic Circuits

2.3.6. Exclusive-OR (XOR) and Coincidence (NXOR) gates

The Boolean EXCLUSIVE-OR (XOR) function is described by: f (a, b) = a ⊕ b; where
f (a, b) = a • b + a • b. The function symbol is shown in Figure 11, and the truth table in
Table 6.

Figure 11 XOR Logic gate symbol

Table 6 Truth table for the logical function XOR

The Boolean function COINCIDENCE (NXOR) is described by: f (a, b) = a ⊗ b;

f (a, b) = a • b + a • b. The symbol of the function is presented in Figure 12, and the truth
table in Table 7.

Figure 12 NXOR Logic gate symbol

Table 7 Truth table for the logical function NXOR

2.4. TTL Gates

We will study the TTL gate (Transistor-Transistor Logic) which performs the NAND
function, because it is the most used.
In order to understand the functionality of logic circuits, it is necessary to have a good
knowledge of both the operating regimes of semiconductor devices (diodes, bipolar transistors

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Fundamental Logic Circuits

and MOS transistors) and the polarizations necessary to be applied to them to obtain the desired
functions.
The main parameters are:

• the time of (delay of) propagation of the logical information from input to output (t pd)
• the average power consumed by the gate (Pd) and the quality factor (Pa), which is
defined as the product between Pd and tpd. The scheme of the TTL gate type NAND
is shown in Figure 13.

Figure 13 Internal schematic of the NAND gate

The operating principle of the TTL NAND gate is presented below. We assume that all
inputs are at a potential corresponding to the minimum value associated with logic level "1" at
input (2V); it follows that the emitter-base junction of transistor T1 is inversely polarized, so T1
works in the inverse active region. The circuit is designed so that when T1 conducts in reverse,
T2 is saturated and, due to the voltage drop on R 3, T3 opens and tends to saturate. The result is a
VOH voltage equal to VCEsat = 0.2V of the transistor T3 . Associating the logic level "1" at the
input of a voltage higher than 2 V and the logic level "0" at the output of a voltage lower than
0.4V results in the circuit ensuring the logic output "0" if all the inputs are logic "1".
If the input B is logic "0" (0V), then the emitter-base junction of the transistor T1 is open and
the potential of the point P, Up = 0.7V, is insufficient for the opening of the transistors T 2 and T3
(which remain blocked).
Then the potential of the M point is high and T 4 transmits. The value of the output voltage
VOH = VCC - VBEsat4 - R2 IB4 - VD3 = 3.6V results, which is associated with logic 1.
The transistors T3 and T4 therefore transmit in contretemps and the corresponding voltage
values obtained on the output are associated with the values of “0” logic, respectively “1” logic.
The characteristics of the TTL NAND gate are:
tpdHL = 8 ns for switching H → L
tpdLH = 12 ns for switching L → H
Pd = 10 mW

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2.5. Peculiarities in the use of logic gates

We consider that we have inputs a, b and an available gate of type NAND with four inputs.
We must realize the function f = 𝑎 ̅̅̅̅̅̅̅̅
• 𝑏, which based on the theorems of Boolean algebra can
also be written as f = 𝑎 • 𝑏 • 1 • 1 or f = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ 𝑎 • 𝑎 • 𝑏 • 𝑏 , where the connections result in
figure 14 :

Figure 14 Possible implementations of the NAND function

Note: Unused inputs connect to logical "1". Left unconnected (in "empty" or "wind", in
"air"), they introduce parasitic capacities, which cause a delay and lead to a malfunction of the
circuit. In the case of laboratory work, on the teaching panel, these inputs can still be
disconnected, because in this case the performance parameters are not so important.
The function NOT can be obtained from a gate NAND with three inputs in several ways, as
we write the expression of the inverter as f = ̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑎 • 𝑎 • 1 or f = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑎 • 𝑎 • 𝑎.

Figure 15 Possible implementations of the NOT function

The AND function of 2 variables can be realized starting from the expression:

𝑎 • 𝑏 = ̅̅̅̅̅̅̅̅
f = a • b = ̿̿̿̿̿̿̿̿ 𝑎̅ + 𝑏̅ (double negation, De Morgan's theorem), as follows (Figure 16):

Figure 16 Possible implementation of the AND function

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Fundamental Logic Circuits

Another component used in the synthesis of combinational circuits is the AND-OR-NOT

gate, which performs the function: f = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑎 • 𝑏 + 𝑐 • 𝑑 , having the symbol:

Figure 17 The AND-OR-NOT circuit

The EXCLUSIVE-OR function performs the mod 2 sum between two variables:
f = a⊕b = a • 𝑏̅ + 𝑎̅ • b. The transformation of the expression results in:

f = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑎̅ • 𝑏̅ + 𝑎 • 𝑏 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝑎̅ + 𝑏) • (𝑎 + ̅𝑏 ), so we have two more possibilities to implement
this function:

Figure 18 Possible implementation of the XOR function

3. Practical part of the lab work

3.1. Identify the functional elements of the teaching panel.
3.2. Check the correct operation of the 2- or 3-input AND gates, the 2-input NOR gate, and
the AND-OR-NOT component by following these steps:
a) Identify the type of TTL component
b) Identify the power supply of the component chosen in 3.2.a)
c) Check the functionality of the circuits.
3.3. Perform and verify the functionality of gates with more inputs than the number of
function variables.
3.4. Implement the XOR and XNOR circuits with NAND or AND-OR-NOT gates,
respectively.

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Fundamental Logic Circuits

3.5. Design and implement (with integrated circuits) the following functions, using AND,
OR, NOT gates.
a) x • (y + z)
b) x • y + x • z
c) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑥 • (𝑦 + 𝑧)
d) 𝑥̅ + 𝑦̅ • 𝑧̅
e) w • (x + y • z)
3.6. Draw and implement the following functions:
a) f = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑥̅ + (̅̅̅̅̅̅̅̅̅
𝑦 + 𝑧)
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
b) f = (𝑥̅ + 𝑦̅) + (𝑥̅ ̅̅̅̅̅̅̅̅
+ 𝑦̅)

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APPEDIX

1. TTL Family
There are several TTL subfamilies that perform the same functions, but differ in terms of
information propagation time and power consumed.
TTL integrated circuits are 14 to 62 pins.
Table 1 shows the TTL circuit family

Figure 19 TTL Circuit Family

The pins of the integrated circuit are numbered counterclockwise. For powering the
circuit, on most 14-pin TTL circuits, pin 7 is GND (ground = 0V dc), and pin 14 is Vcc
(+5Vdc).

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Fundamental Logic Circuits

2. MOS Family
The main advantages over the TTL family are:
• immunity to noise (noise margin is 1.5V from 0.4V to TTL);
• low power consumption
The most common MOS family is CMOS.
Figure 20 shows the differences between the voltage values associated with the logic
levels in the TTL family and the CMOS family.

Figure 20 Logic levels for TTL and CMOS

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