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Lab 11
Lab 11
Lab report 11
Submitted by
Adeel Sahto
Registration No:
FA20-BEE-019
Submitted to
Ma’am Faiza Rajab
Dated: 06/20/2021
Lab# 11 Implementation of a BCD Counter with
Control Inputs on FPGA
Verilog Code:
module Lab_11(clk, reset, bcd_counter
);
input reset;
input clk;
begin
if(reset == 1)
else
end
always@(counter_state)begin
case(counter_state)
4'b0000:begin
end
4'b0001:begin
end
4'b0010:begin
end
4'b0011:begin
end
4'b0100:begin
end
4'b0101:begin
end
4'b0110:begin
end
4'b0111:begin
end
4'b1000:begin
end
4'b1001:begin
end
endcase
end
always@(counter_state)begin
case(counter_state)
4'b0000:begin
end
4'b0001:begin
end
4'b0010:begin
end
4'b0011:begin
bcd_counter <= 7'b1111001;
end
4'b0100:begin
end
4'b0101:begin
end
4'b0110:begin
end
4'b0111:begin
end
4'b1000:begin
end
4'b1001:begin
end
default:begin
end
endcase
end
endmodule
Verilog Testbench:
module TB_Lab_11;
// Inputs
reg clk;
reg reset;
// Outputs
Lab_11 uut (
.clk(clk),
.reset(reset),
.bcd_counter(bcd_counter)
);
always
begin
clk = 0;
#10;
clk = 1;
#10;
end
initial begin
// Initialize Inputs
reset = 1;
#10;
reset = 0;
#10;
end
endmodule
Waveform: