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VLSI

DnIT
2 Mal
Stwitch level rmdelk ob /agos, PMOs,
h
) Drao
CASkrgie introcltuction

3) Abst medion 2S1 ) euign

VS Desi Proccu.
Schenalre Capteave
6 Dehine
Synthesi Sinulation

7Deb ine placemcnl souting


Sicle Diagram
Eaplain
HDL
Expand VS, HDI-,
)
19Explain CoP Po.

NMOS
All ates awg

2 All gates Ueing CMOC


Placment Rouling
Eaplain Stte Dieg m
CNIT
3 Maok

Explain HD
2) xplain enenal
Cntity rchiterttre

3)Syntar
the types a Macl:lirg
NOT, NA ND
VH D Code hor AND, OR,
ymbols
ndh tae
X-OR gato WiTh
NOR,
Explain Aroeu tatement

Atcdemrcnt
19 Cie
Caplain Dectaration S g n a l
C Sgnal
statemcn7
ynmcnt

1o Mare
)ypee Modeling
o VHDI Statomnt.
Mark
tlal s full addoy
Pxplain
Subla tor.
C
2) d

3)
fncodcn, Decodey
4
b i t (orparator.
4 bit vthmoti

Drnu the 2Dhngram o


Saubtrne tor.
addorn s
10 MaKA k
i?Hal4 & fel) Rdder, viðthalt
VHDL Code for
Full Subtractor

Cini) Hox, De-t


(iv? Fnceder, Detodey.
v ompaator,
Subt7octor.
Addeq %
Anthmetic
vi)
2 Manke
Soqucntial Cireuit
D a u o 7he Blrk dngam )
it
2
fin lpttep s

all 7ype of flipflops urh


fxplain
Tmdh able
hcal .ketch s
nefortton
tabli tor all
the

flpflop Diagoam 2bit Bynchre


Dmw the
Doun Counter.
tourier
of abit Synchran au
6Drao he Diegram
Down Counte.
UP
Decod, Ring,
7 Dga the. Diay Tam
Johnonn Courjer
lo Mark
VH Cocle or J T , flipflap
Without 7oct
(Without eiot lp,
With Teet {p)
Code o Synchronca tp,
VHDL
2)
Doun, OP Doun (ountor.

3) VHDL
Code tor Decade Canter , Ring
i,

Jornon
Counfer.
Maokt
Ded ine
n s i t yre
ndnntge

PrOti, Pn1, ru
3 C o m t a necn /

ASIC pEyA

anhget a Cru ,
6) Advantager s Diuadv

Asie
7) beu ab
Ds Design gl0.
s7
) ApPlication e ASI

loMaTk
PROM, P , PLA
Prcplerm bo
T y p e t of ASiC

sIC Deign flos


CPn, frG.

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