Unit-3 Sequential Logic Design

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third
Edition.
2. “Digital Design”, M Morris Mano, Prentice Hall, Third Edition.
3. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second
Edition.
 DISCLAIMER

This presentation and video is created as a

reference material for the students of SE-IT, PICT
(AY 2022-23 Sem-1).
It is restricted only for the internal use and any
circulation is strictly prohibited.

RVK-LDCO-3.1 2
 Syllabus
• Introduction to sequential circuits: Difference between
combinational circuits and sequential circuits; Memory element-latch
& Flip-Flop.
• Flip- Flops: Logic diagram, truth table & excitation table of SR, JK, D, T
flip flops; Conversion from one FF to another , Study of flip flops with
regard to asynchronous and synchronous, Preset & Clear, Master Slave
configuration ; Study of 7474, 7476 flip flop ICs.
• Application of flip-flops: Counters- asynchronous, synchronous and
modulo n counters, study of 7490 modulus n counter ICs & their
applications to implement mod counters; Registers- shift register
types (SISO, SIPO, PISO &PIPO)& applications.
• Case Study : Use of sequential logic design in a simple traffic light
controller

RVK-LDCO-3.1 3
 Contents

3.1 Introduction to sequential circuits

3.2 Flip-flops
3.3 Application of flip-flops

RVK-LDCO-3.1 4
 3.1 Introduction to Sequential
Circuits

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third
Edition.
2. “Digital Design”, M Morris Mano, Prentice Hall, Third Edition.
3. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second
Edition.
 Sequential Circuits
• Sequential circuits depend on current inputs and previous outputs
that defines the current state/memory.
Inputs Combinational Outputs
circuit

Memory

• It can be considered as a combinational circuit with memory.

• This makes things more difficult to understand, since the same inputs
can yield different outputs, depending on what’s stored in memory.

• The memory contents can also change as the circuit runs.

• We’ll need some new techniques for analyzing and designing

sequential circuits.
RVK-LDCO-3.1 6
 Examples of Sequential Devices
• Many real-life devices are sequential in
nature:
– Combination locks open if you enter numbers in
the right order.

– Elevators move up or down and open or close

depending on the buttons that are pressed on
different floors and in the elevator itself.

– Traffic lights may switch from red to green

depending on whether or not a car is waiting at the
intersection

RVK-LDCO-3.1 7
 Combinational vs. Sequential Circuit

(a) Combinational Circuit (b) Sequential Circuit

Output = F (In) Output = F (In, Previous In)

Sr.No. Combinational Circuit Sequential Circuit

1 It uses only the current inputs to It uses both current inputs and previous
determine the output. outputs to determine the current output.
2 Combinational logic does not require Sequential logic uses the feedbacks from the
feedbacks. output to inputs.
3 With combinational logic, the circuit In sequential logic sequence of input
always produces the same output operands is important.
solely based on combination of input
operands, regardless of the order of
the inputs. RVK-LDCO-3.1 8
 Combinational vs. Sequential Circuits (cont..)
Sr.No. Combinational Circuit
4 It is faster as delay between the input
and output is due to propagation delay
of gates only.
5 It is easy to design.
6 It is used to implement basic Boolean
operations.
7 Combinational circuits are broadly
classified as per the following
functions:
1) Arithmetic & logical functions
2) Data Transmission
3) Code conversion
8 E.g. Half adders, full adders,
multiplexers, demultiplexers, decoders
and encoders
RVK-LDCO-3.1
Sequential Circuit
It is slower than the combinational circuit.
It is comparatively harder to design
It is used to create memory elements and to
build finite state machines.
Sequential circuits are broadly classified as
per the timing of their signals:
1) Asynchronous/ Event Driven circuits
2) Synchronous/ Clock Driven circuits
E.g. Latches, flip-flops, registers, shift
registers, counters, memory devices.
9
Memory Element
 What Exactly is Memory?
• A memory should have at least three properties:
1. It should be able to hold a value.
2. You should be able to read the value that was saved.
3. You should be able to change the value that was saved.

• We’ll start with the simplest case, a one-bit memory:

1. It should be able to hold a single bit, 0 or 1.
2. You should be able to read the bit that was saved.
3. You should be able to change the value. Since there is only a single bit, there
are only two choices:
• Set the bit to 1
• Reset, or clear, the bit to 0.

RVK-LDCO-3.1 11
 The Basic Idea of Storage
• How can a circuit "remember" anything, when it is just a bunch of
gates that produce outputs according to the inputs?
• The basic idea is to make a loop, so the circuit outputs are also
inputs.
• Here is one initial attempt, shown with two equivalent layouts:

• Does this satisfy the properties of memory?

• These circuits "remember" Q, because its value never changes
(Similarly, Q' never changes either).
• We can also "read" Q, by attaching a probe or another circuit.
• But we can’t change Q! There are no external inputs here, so we
can’t control whether Q=1 orRVK-LDCO-3.1
Q=0. 12
SR Latch
 The S-R Latch Circuit
• Let’s use NOR gates instead of inverters.
• The SR latch below has two inputs S and R, which will let us control
the outputs Q' and Q.

• Here Q and Q' feed back into the circuit. They are not only outputs,
they are also inputs!
• To figure out how Q and Q' change, we have to look at not only the
inputs S and R, but also the current values of Q and Q':
Qnext = (R + Q'current)'
Q'next = (S + Qcurrent)'
• Let’s see how different input values for S and R affect this thing.
RVK-LDCO-3.1 14
 Storing a Value: SR = 00
• What if S = 0 and R = 0?

• The equations on the right reduce to:

Qnext = (0 + Q'current)' = Qcurrent
Q'next = (0 + Qcurrent)' = Q'current
Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’
• So when SR = 00, then Qnext = Qcurrent.
Whatever value Q (0 or 1) has, it keeps.

• This is exactly what we need to store values

in the latch.

RVK-LDCO-3.1 15
 Setting the Latch: SR = 10
• What if S = 1 and R = 0?
• Since S = 1, Q’next is 0, regardless of Qcurrent:

Q’next = (1 + Qcurrent)’ = 1’ = 0

• Then, this new value of Q’ goes into the top Qnext = (R + Q’current)’
NOR gate, along with R = 0 Q’next = (S + Qcurrent)’

Qnext = (0 + 0)’ = 0’ = 1
• So when SR = 10, then Q’next = 0 and Qnext = 1
• This is how you set the latch to 1. The S input
stands for “set”.
• Once Qnext becomes 1, the outputs will stop
changing. This is a stable state.
RVK-LDCO-3.1 16
 Resetting the Latch: SR = 01
• What if S = 0 and R = 1?
• Since R = 1, Qnext is 0, regardless of Q’current:

Qnext = (1 + Q’current)’ = 1’ = 0

• Then, this new value of Q goes into the

bottom NOR gate, where S = 0 Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’
Q’next = (0 + 0)’ = 0’ = 1

• So when SR = 01, then Qnext = 0 and Q’next = 1

• This is how you reset, or clear, the latch to 0
The R input stands for “reset”.

RVK-LDCO-3.1 17
 SR Latches are Memories!
• This little table shows that our latch
S R Q
provides everything we need in a
0 0 No change
memory: we can set it, reset it, and 0 1 0 (reset)
remember the current value. 1 0 1 (set)

• The output Q represents the data stored

in the latch. It is sometimes called the
state of the latch.
Inputs Current Next
S R Q Q’ Q Q’
• We can expand the table above into a
0 0 0 1 0 1
state table, which explicitly shows that 0 0 1 0 1 0
the next values of Q and Q’ depend on 0 1 0 1 0 1
their current values, as well as on the 0 1 1 0 0 1
inputs S and R. 1 0 0 1 1 0
1 0 1 0 1 0
RVK-LDCO-3.1 18
 SR Latches are Sequential!
• Notice that for inputs SR = 00, the next S R Q
value of Q could be either 0 or 1, 0 0 No change
depending on the current value of Q. 0 1 0 (reset)
1 0 1 (set)

• So the same inputs can yield different Inputs Current Next

outputs, depending on whether the latch S R Q Q’ Q Q’
was previously set or reset. 0 0 0 1 0 1
0 0 1 0 1 0
0 1 0 1 0 1
• This is very different from the 0 1 1 0 0 1
1 0 0 1 1 0
combinational circuits that we have seen 1 0 1 0 1 0
so far, where the same inputs always
yield the same outputs.

RVK-LDCO-3.1 19
 What about SR = 11?
• Since S = R = 1, both Qnext and Q'next will become 0 Qnext = (R + Q’current)’
that contradicts the assumption that Q and Q’ are Q’next = (S + Qcurrent)’
always complements.
• Another problem occurs if we then make S = 0 and
R = 0 together,
Qnext = (0 + 0)' = 1
Q’next = (0 + 0)' = 1
• But these new values go back into the NOR gates,
and in the next step we get:
Qnext = (0 + 1)' = 0
Q’next = (0 + 1)' = 0
• The circuit enters an infinite loop, where Q and Q’
cycle between 0 and 1 forever.
• This is actually the worst case, but the moral is
don’t ever set SR=11! RVK-LDCO-3.1 20
 S’R’ Latch
• There are several varieties of latches.
• You can use NAND instead of NOR gates to get a S’R’ latch.
• The input signals for the NAND latch are the complement of the
signals for the NOR latch, hence the name S’R’ latch.

S’ R’ Q
1 1 No change
1 0 0 (reset)
0 1 1 (set)
0 0 Avoid!

• You can derive this table by writing equations for the outputs in
terms of the inputs and the current state, just as we did for the SR
latch.
RVK-LDCO-3.1 21
 An SR Latch with a Control Input
• Here is an SR latch with a control input C.

C S R S’ R’ Q
0 x x 1 1 No change
1 0 0 1 1 No change
1 0 1 1 0 0 (reset)
1 1 0 0 1 1 (set)
1 1 1 0 0 Avoid!

• Notice the hierarchical design!

– The dotted purple box is the S’R’ latch.
– The additional NAND gates are simply used to generate the correct inputs for the
S’R’ latch.

• The control input acts just like an enable. Latch can only change when C = 1, all
other times the circuit remains in the same state no matter what values are on
the S and R inputs.

RVK-LDCO-3.1 22
D Latch
 D Latch
• The D latch is designed to eliminate the undefined state of the SR latch by
ensuring that the S and R inputs are never high at the same time.
• A D latch is based on an S'R' latch. The additional gates generate the S' and R'
signals, based on inputs D ("Data") and C ("Control").
• Hence the name is D latch as “D” stands for Data.
C D Q
0 x No change
1 0 0
1 1 1

• When C = 0, S' and R' are both 1, so the state Q does not change.
• When C = 1, the latch output Q will equal the input D.
• No more messing with one input for set and another input for reset!
• Also, this latch has no "bad" input combinations to avoid. Any of the four possible
assignments to C and D are valid

RVK-LDCO-3.1 24
 Transparent Latch
• A waveform illustrating the operation of a control input D latch is
shown in Figure

• Its input value can be seen directly from its output value. The
outputs respond immediately to the inputs. This is the case with the
D latch when its control, C, is high.
• Note that Q follows changes in the data input as long as the control
input is High. The circuit is often called a transparent latch.

RVK-LDCO-3.1 25
 Problem of Transparency
• When latches are used for the storage elements, a serious
difficulty arises
– If the inputs applied to the latches change while the enable control input, C,
is still in the logic 1 level, the latches will respond to new values and a new
output state may occur.
– The result is an unpredictable situation since the state of latches may keep
changing for as long as the enable control input stays in the active level.
• The problem with the latch is that it responds to a change in the
level (level-sensitive) of a control input, shown in Figure below

RVK-LDCO-3.1 26
 Problem of Transparency (Cont.)
• In a computer circuit, however, we do not want the memory state
to change at various times when the enable signal is asserted.
• Instead, we like to synchronize all of the state changes to happen at
precisely the same moment and at regular intervals.
• In order to achieve this, two things are needed:
(1) A synchronizing signal, and
(2) A memory circuit that is not level-sensitive
• The synchronizing signal, of course, is the clock, and the non-level-
sensitive memory circuit is the flip-flop.

RVK-LDCO-3.1 27
 Clocks and Synchronization
• A clock is a regular periodic signals whose output continuously
alternates between 0 and 1
duty cycle (in this case, 50%)

period

• The time between two consecutive ticks is called the clock period
• The clock frequency is the inverse of the clock period. The unit of
measurement for frequency is the hertz
• Clocks are often used to synchronize circuits
• Duty-cycle
– Fraction of the total period that a digital waveform is in the HIGH state
– Usually expressed as % of period

RVK-LDCO-3.1 28
 Clock Pulse Definition

• Edges can also be referred to as leading and trailing.

RVK-LDCO-3.1 29
 3.2 Flip flops

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third
Edition.
2. “Digital Design”, M Morris Mano, Prentice Hall, Third Edition.
3. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second
Edition.
 Flip-Flop Vs Latch
• The primary difference between a D flip-flop and D latch is the
EN/CLOCK input.

• The flip-flop’s CLOCK input is edge sensitive, meaning the flip-flop is

designed to change its output at the edge (rising or falling) of a
controlling CLOCK input signal.

• The latch’s EN input is level sensitive, meaning the latch’s output

changes on the level (high or low) of the EN input.

RVK-LDCO-3.2 31
 Edge Triggered Flip-Flops
• An edge triggered flip-flop changes state either at the positive edge
(rising edge) or a the negative edge (falling edge) of the clock pulse.
• It is sensitive to inputs only at this transition of the clock.
• Each flip-flop can be either positive edge triggered (no bubble at the
C input) or negative triggered (bubble at the C input).
• The dynamic input indicator means the flip flop changes state only
on the edge of a clock pulse.

Positive Edge
Triggered FF

Negative
Edge
RVK-LDCO-3.2 32
Triggered FF
 A Method of Edge Triggering
• The S-R flip-flop differs from the gated S-R latch only in that it has a
pulse transition detector.
• This circuit produces a very short duration spike on either the
positive-going transition or the negative-going transition of each
clock pulse.
• The circuit uses a AND gate as the input thereby providing a delay in
nanoseconds .
• The inverter is used to handle both positive and negative edge
triggering because of the inversion process.
• The Enable in this case is called the Clock (CLK).
S
Q
pulse
CLK transition
detector
Q'
R
RVK-LDCO-3.2 33
A simplified logic diagram for an edge-triggered S-R flip flop
 Convention
• The circuit is set means output = 1.

• The circuit is reset means output = 0.

• Flip-flops have two output Q and Q’.

• Due to time related characteristic of the flip-flop, Q and Q’ are

usually represented as followed:
– Q(t) or Q: present state
– Q(t+1) or Q+: next state

RVK-LDCO-3.2 34
SR Flip flop
 Edge Triggered S-R Flip-Flop
• The S and R inputs of the S-R flip-flop are called synchronous inputs
because data on these inputs are transferred to the flip-flop’s
output only on the triggering edge of the clock pulse.

• When the S is HIGH and R is LOW, the output goes HIGH on the
triggering edge of the clock pulse - flip flop is SET.

• When the S is LOW and R is HIGH, the output goes LOW on the
triggering edge of the clock pulse - flip flop is RESET.

• When both S and R are LOW, the output does not change from its
previous state.

• An invalid condition exists when both S and R are HIGH.

RVK-LDCO-3.2 36
 Operation of a Positive Edge-Triggered S-R
Flip-Flop

• Note: The operation and truth table for a negative edge-triggered flip-flop are
the same as those for a positive except that the falling edge of the clock pulse is
the triggering edge.
RVK-LDCO-3.2 37
Positive Edge Triggered S-R Flip-Flop Timing
Diagram

RVK-LDCO-3.2 38
D Flip flop
 The Edge Triggered D Flip-Flop
• The D flip-flop is useful when a single bit (1 or 0) is to be stored.
• The addition of an inverter to an S-R flip-flop creates a basic D flip-
flop.
• The flip-flop only has 1 input in addition to the clock.
• If there is a HIGH on the D when a clock pulse is applied, the flip flop
will set and the HIGH on the D input is stored by the flip-flop on the
triggering edge of the clock pulse.
• If there is a LOW on the D when the clock pulse is applied, the flip-
flop will reset and the LOW on the D input is stored by the flip-flop
on the triggering edge of the clock pulse
• In a SET state the flip-flop is storing a 1, and the RESET state is
storing a 0.
A positive edge-triggered D
Flip-Flop formed with an S-R
flip-flop and an inverter
RVK-LDCO-3.2 40
 Master-Slave Negative Edge Triggered
D Flip-Flop
• The first latch is called the master and the second the slave. The circuit samples
the D input and changes its output Q only at the negative edge of the
synchronizing or controlling clock (designated as Clk ). When the clock is 0, the
output of the inverter is 1.
• The slave latch is enabled, and its output Q is equal to the master output Y . The
master latch is disabled because Clk = 0. When the input pulse changes to the
logic-1 level, the data from the external D input are transferred to the master.
The slave, however, is disabled as long as the clock remains at the 1 level,
because its enable input is equal to 0.
• Any change in the input changes the master output at Y, but cannot affect the
slave output. When the clock pulse returns to 0, the master is disabled and is
isolated from the D input. At the same time, the slave is enabled and the value
of Y is transferred to the output of the flip-flop at Q . Thus, a change in the
output of the flip-flop can be triggered only by and during the transition of the
clock from 1 to 0.

RVK-LDCO-3.2 41
 The Positive Edge Triggered D Flip-Flop
Timing Diagram

Note: From the above timing diagram, it's called a D flip-flop because it delays
the signal. The output is just the input delayed until the next active clock
transition.
RVK-LDCO-3.2 42
JK Flip flop
 The Edge Triggered J-K Flip-Flop
• The J-K flip-flop is versatile and is a widely used type of flip-flop.
• The J and K designations for the inputs have no known significance
except that they adjacent letters in the alphabet.
• The function of the J-K flip-flop is identical to that of the S-R flip-flop
in the SET, RESET and no change conditions of operation.
• The difference is that the J-K flip-flop has no invalid state as does
the S-R flip-flop.
• J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.
• Include a toggle state
– J = HIGH and K = LOW  Q becomes HIGH (SET state)
– K = HIGH and J = LOW  Q becomes LOW (RESET state)
– Both J and K are LOW No change in output Q
– Both J and K are HIGH Toggle

RVK-LDCO-3.2 44
 J-K Flip-Flop
• J-K flip-flop circuit:

• Characteristic table:
J K CLK Q(t+1) Comments
0 0  Q(t) No change
0 1  0 Reset
1 0  1 Set
1 1  Q(t)' Toggle
 RVK-LDCO-3.2 45
J-K Flip-Flop Derived from S-R Flip-Flop

RVK-LDCO-3.2 46
 Race Around Condition
• For J-K flip-flop, if J=K=1, and if CLK=1 for a long period of time
(means, width of a clock pulse is too long), then Q output will toggle
as long as CLK is high, which makes the output of the flip-flop
unstable or uncertain. This problem is called race around condition
in J-K flip-flop.

• This problem (race around condition) can be avoided by ensuring

that the clock input is at logic “1” only for a very short time.

RVK-LDCO-3.2 47
Elimination of Race Around Condition
• There are three methods to eliminate race around condition as
described below:
• Increasing the delay of flip-flop:
– The propagation delay (Δt) should be made greater than the duration of the
clock pulse (T). But it is not a good solution as increasing the delay will
decrease the speed of the system.
• Use of edge-triggered flip-flop:
– If the clock is High for a time interval less than the propagation delay of the
flip-flop then racing around condition can be eliminated. This is done by using
the edge-triggered flip flop rather than using the level-triggered flip-flop.
• Use of master-slave JK flip-flop:
– If the flip-flop is made to toggle over one clock period then racing around
condition can be eliminated. This is done by using Master-Slave J-K flip-flop.

RVK-LDCO-3.2 48
 J-K Master-Slave Flip-Flop
• The master is set according to J and K while the clock is high; the
contents of the master are then shifted into the slave (Q changes
state) when the clock goes low.

7
1 5
2 12 2 3
13 1 2 1
3 1 2
3 1
3

2
4 2
2 1
8 2
6
1 3 Master-slave flip-lop
1 1 3
2 12 3
13

9
1 2

RVK-LDCO-3.2 49
7476 JK master flip-flop
The Negative Edge Triggered J-K Flip-Flop
Timing Diagram

RVK-LDCO-3.2 50
 Asynchronous Preset and Clear Inputs
• The S-R, D and J-K inputs just discussed are called
synchronous inputs because data on these inputs
are transferred to the flip-flop’s output only on the
triggering edge of the clock pulse → data is
transferred synchronously with clock.

• Most IC flip-flops also have asynchronous inputs.

• These inputs affect the state of the flip-flop

independent of the clock.
Logic symbol for a
J-K flip-flop with
• They are normally known as preset (PRE) and clear active-LOW preset
(CLR) by the manufacturer. and clear inputs

RVK-LDCO-3.2 51
 Asynchronous Input
• A J-K flip-flop with active-low PRESET and CLEAR asynchronous
inputs:

RVK-LDCO-3.2 52
Negative Edge Triggered J-K Flip-Flop with Preset
and Clear Inputs Timing Diagram

RVK-LDCO-3.2 53
T Flip flop
 The Edge Triggered T Flip-Flop
• This type of flip-flop is a simplified version of the J-K flip-flop.
• It is used in many kinds of circuits, especially counter and dividers.
• If the T input is high, the T flip-flop changes state ("toggles") on the
triggering edge of the clock pulse. If the T input is low, the flip-flop
holds the previous value.
• Its only function is that it toggles itself with every clock pulse (on
either the leading edge, on the trailing edge) it can be constructed
from the JK flip-flop by tying the J and K inputs together to form
the T input

T J Q Q
A positive edge-triggered T
CLK flip-flop formed by a J-K flip-
flop
K Q Q'
RVK-LDCO-3.2 55
The Positive Edge Triggered T Flip-Flop
Timing Diagram

RVK-LDCO-3.2 56
Characteristic Tables and
Equations of Flip-Flops
 Characteristic Tables
• Flip flop is sequential, not combinational - can't describe using
truth table.

• Alternatives:
– Characteristic table
– State diagram

• The tables that we’ve made so far are called characteristic tables.
– They show the next state Q(t+1) in terms of the current state Q(t) and the
given inputs.
– For simplicity, the control input C is not usually listed.
– Again, these tables don’t indicate the edge-triggered behavior of the flip-
flops that we have been using.

RVK-LDCO-3.2 58
 Characteristic Tables (Cont.)
S-R flip-flop J-K flip-flop
S R Q(t+1) Operation J K Q(t+1) Operation
0 0 Q(t) No change 0 0 Q(t) No change
0 1 0 Reset 0 1 0 Reset
1 0 1 Set 1 0 1 Set
1 1 Undefined Invalid 1 1 Q’(t) Toggle

D flip-flop T flip-flop

D Q(t+1) Operation T Q(t+1) Operation

0 0 Reset 0 Q(t) No change
1 1 Set 1 Q’(t) Toggle

RVK-LDCO-3.2 59
 Characteristic Equations
• We can also write characteristic equations, where the next state
Q(t+1) is defined in terms of the current state Q(t) and inputs.

S-R flip-flop
S R Q(t+1) Operation
0 0 Q(t) No change Q(t+1) = R’Q(t) + S
0 1 0 Reset
1 0 1 Set
1 1 Undefined Invalid

J-K flip-flop
J K Q(t+1) Operation
0 0 Q(t) No change Q(t+1) = K’Q(t) + JQ’(t)
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Toggle
RVK-LDCO-3.2 60
 Characteristic Equations (cont..)
D flip-flop
D Q(t+1) Operation Q(t+1) = D
0 0 Reset
1 1 Set

T flip-flop
T Q(t+1) Operation
0 Q(t) No change Q(t+1) = T ’Q(t) + TQ’(t)
1 Q’(t) Toggle = T  Q(t)

RVK-LDCO-3.2 61
Excitation Tables of Flip-Flops
 Excitation Table
• The excitation table tells the designer the minimum inputs that
are necessary to generate (or to “excite”) a particular next state
when the current state is known.

• It is similar to truth table and state table with the rearrangement

of the data so that the current state and next state are next to
each other on the left-hand side of the table, and the inputs
needed to make that state change happen are shown on the right
side of the table.

• This is the same information that is given in the transition table,

but presented “backwards”.

RVK-LDCO-3.2 63
 Excitation Table for S-R Flip-Flop
Transition Table Excitation Table

S R Q Q+
Q Q+ S R
0 0 0 0
0 0 1 1 Rearranging rows and/or columns… 0 0 0 X
0 1 0 0 0 1 1 0
1 0 0 1
0 1 1 0
1 1 X 0
1 0 0 1
1 0 1 1 Tells what input is needed
to achieve desired
1 1 0 Undefined output transition
1 1 1 Undefined
Tells how inputs affect output

In the end, they are the same tables, just rearranged…

RVK-LDCO-3.2 64
 Excitation Table for J-K Flip-Flop
Transition Table Excitation Table

J K Q Q+
0 0 0 0 Q Q+ J K
Rearranging rows and/or columns…
0 0 1 1 0 0 0 X
0 1 0 0 0 1 1 X
0 1 1 0 1 0 X 1
1 0 0 1 1 1 X 0
1 0 1 1 Tells what input is needed
1 1 0 1 to achieve desired
1 1 1 0 output transition

Tells how inputs affect output

In the end, they are the same table, just rearranged…

RVK-LDCO-3.2 65
 Excitation Table for D Flip-Flop

Transition Table Excitation Table

D Q Q+ Q Q+ D
Rearranging rows and/or columns…
0 0 0 0 0 0
0 1 0 0 1 1
1 0 1 1 0 0
1 1 1 1 1 1

Tells how inputs affect output Tells what input is needed

to achieve desired
output transition

In the end, they are the same table, just rearranged…

RVK-LDCO-3.2 66
 Excitation Table for T Flip Flop
Transition Table Excitation Table

T Q Q+ Q Q+ T
Rearranging rows and/or columns…
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 1 1 0

Tells how inputs affect output Tells what input is needed

to achieve desired
output transition

In the end, they are the same table, just rearranged…

RVK-LDCO-3.2 67
Excitation Table of S-R, J-K, D & T Flip-Flops

Q(t) Q(t+1) S R J K D T

0 0 0 x 0 x 0 0

0 1 1 0 1 x 1 1

1 0 0 1 x 1 0 1

1 1 x 0 x 0 1 0

RVK-LDCO-3.2 68
State Tables of Flip-Flops
 State Table
• For a combinational circuit we could find a truth table, which
shows how the outputs are related to the inputs.

• A state table is the sequential analog of a truth table. It shows

inputs and current states on the left, and outputs and next states
on the right.
– For a sequential circuit, the outputs are dependent upon not only the
inputs, but also the current state of the flip-flops.
– In addition to finding outputs, we also need to find the state of the flip-
flops on the next clock cycle.

RVK-LDCO-3.2 70
 Sequential Circuits and State Diagrams
• To describe combinational circuits, we used Boolean expressions
and truth tables. With sequential circuits, we can still use
expression and tables, but we can also use another form called a
state diagram.
• We draw one node for each state that the circuit can be in. Latches
have only two states: Q=0 and Q=1.
• Arrows between nodes are labeled with “input/output” and
indicate how the circuit changes states and what its outputs are. In
this case the state and the output are the same. This represents the
Mealy Model whose output values are determined both by its
current state and by the values of its inputs.

• Moore Model whose output values are determined only by its

current state. This is in contrast to a Mealy model.

RVK-LDCO-3.2 71
 State Diagram- Mealy Model

• S-R flip-flop 

• J-K flip-flop 

• D flip-flop 

• T flip-flop 
RVK-LDCO-3.2 72
 State Diagram- Moore Model

• S-R flip-flop 

• J-K flip-flop 

• D flip-flop 

• T flip-flop 
RVK-LDCO-3.2 73
 State Table vs. State Diagram
• Same information
• Table is perhaps easier to fill in from description
• Diagram is easier for understanding and writing code
– You can label states with English description
– Eliminate repetitive portions (for example, when reset is an input)

RVK-LDCO-3.2 74
 3.3 Applications of Flip-Flops

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third
Edition.
2. “Digital Design”, M Morris Mano, Prentice Hall, Third Edition.
3. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second
Edition.
Counters
 Counters
• A counter is a specific type of sequential circuit that goes through a
prescribed sequence of states each time an input clock pulse makes
an active transition.

Clock Count
The state, or the flip-
Counter flop values
themselves, serves
as the “output”
Load an initial value, reset May also enable count,
to starting count, etc. select direction, etc.

optional inputs
RVK-LDCO-3.3 77
 Counters (Cont.)
• Counters differ by a number of basic characteristics, including

Characteristic Description 000

Modulus Length of sequence
101 001
Coding Count sequence
Direction Up or down
Resetable Reset to zero 100 010
Loadable Load a specific value
011

After the largest value, the output “wraps around” back

to 0.
The sequence of states: may follow the binary number
sequence ( Binary counter) or any other sequence of
states.
RVK-LDCO-3.3 78
 States/Modulus/Flip-Flops
• The number of flip-flops determines the count limit or number of
states. If N flip-flops are connected:
No. of states = 2N; where N = number of flip-flops
• The number of states used is called the MODULUS.
• E.g. a Modulus-12 counter (Mod-12) or divide-by-12 counter would
count from 0 (0000)2 to 11 (1011)2 and would require four flip-flops
(24 = 16 states; 12 are used).
• Power-of-2 counters use all states. Non-power-of-2 counters have
extra, unused states
• E.g. 4-bit Binary / Hex / Mod-16 Counter
– 0000, 0001, 0010, … 1110, 1111, 0000, 0001, … All states are used.
• E.g. 4-bit BCD / Decade / Mod-10 Counter
– 0000, 0001, 0010, … 1000, 1001, 0000, 0001, … Last 6 states are unused.

RVK-LDCO-3.3 79
 Types of Counters
1. Asynchronous (ripple) counters
– The flip-flop output transition serves as a source for triggering other flip-
flops
– No common clock pulse (not synchronous).

HIGH

J0 Q0 J1 Q1 J2 Q2

CLK C C C
Q0 Q1
K0 K1 K2

An example of a 3-bit asynchronous counter which use J-K flip-

flops in the toggle mode

RVK-LDCO-3.3 80
 Types of Counters (Cont.)
2. Synchronous counters:
– The CLK inputs of all flip-flops receive a common clock
– Synchronous counters overcome the disadvantage of accumulated
propagation delays, but generally they require more circuitry to control
states changes.

HIGH Q0

Q0Q1
Q0 Q1 Q2
J0 J1 J2

C C C

K0 K1 K2

CLK

RVK-LDCO-3.3 81
 Counting in Binary
• The binary counting sequence is shown on
the right.
• Look at the column labelled Q0. It reads 0, 1,
0, 1, 0, 1, etc. If this were drawn as a timing
diagram, it would look like a clock. Assume
that this clock has period T.
• Now look at the column labelled Q1. It reads
0, 0, 1, 1, 0, 0, 1, 1. It looks like a clock too!
However, it stays 0 twice as long, then 1
twice as long. In fact, it looks like a clock that
has a period of 2T.
• Now look at the column labelled Q2. It reads
0, 0, 0, 0, 1, 1, 1, 1. Again, this looks like a
clock, except it's going twice as slow! It has a
period of 4T.
RVK-LDCO-3.3 82
 The Timing Diagram that Shows How the
Counter Behaves

“0” “1” “2” “3” “4” “5” “6” “7”

CLK

Q0 0 1 0 1 0 1 0 1
Q1 0 0 1 1 0 0 1 Repeats →
1
Q2
0 0 0 0 1 1 1 1

Note: assume the flip-flops used are positive edge trigger

RVK-LDCO-3.3 83
 IC7476 J-K Master-Slave Flip-flop
• The 7476 is a master-slave J-K and the 74LS76 is a negative edge-
triggered J-K flip-flop.
• Both chips have the same pin configuration.
• Both chips have synchronous inputs of J, K and CLK.
• Both chips have asynchronous inputs normally labeled as preset
(PRE) and clear (CLR). These inputs are usually active LOW.
• The J-K flip-flop can be made into a D flip-flop by bringing the data
input into the J and the inverse of the data input into the K input.

RVK-LDCO-3.3 84
IC7476 J-K Master-Slave Flip-flop (Cont.)

(b) Function Table

(a) Package Configuration

RVK-LDCO-3.3 85
Asynchronous (Ripple) Counters
 Build a 3-bit Asynchronous (Ripple)
Counter
1
Q0 1
Q1 1
Q2
J Q J Q J Q

CLK ? ?
K Q Q0 K Q Q1 K Q Q2

• Starting with three positive edge triggered J-K flip-flops connected in

"toggle" mode, we need to determine how to connect the clock
inputs in such a way so that each succeeding bit toggles when the bit
before it transitions from 1 to 0.
• The Q outputs of each flip-flop will serve as the respective binary bits
of the final, three-bit count.

RVK-LDCO-3.3 87
 Build a 3-bit Asynchronous (Ripple)
Counter (Cont.)
• If we look at the previous timing diagram, we really want Q1 to
toggle on negative edges of Q0.
• However, the J-K flip-flop in "toggle" mode will toggle on positive
edges. How can we solve this problem?
• Answer: Since the Q' output will always be the exact opposite state
of the Q output on a J-K flip-flop. To toggle on negative edges of Q0
is equivalent to toggling on the positive edges of Q0', which is the
negation of Q0.
In other words, each time the Q0 output of a flip-flop transitions
from 1 to 0, the Q0' output of the same flip-flop will transition from
0 to 1, providing the positive-going clock pulse we would need to
toggle a positive-edge triggered flip-flop at the right moment
• Similarly, we want Q2 to toggle on negative edges of Q1 and thus we
have:
RVK-LDCO-3.3 88
 Build a 3-bit Asynchronous (Ripple)
Counter (Cont.)
• The following is a three-bit asynchronous binary counter and its
timing diagram for one cycle

HIGH
J Q Q0 J Q Q1 J Q Q2
CLK
K Q K Q K Q

1 2 3 4 5 6 7 8

CLK
Q0

Q1
Q2
0 1 2 3 4
RVK-LDCO-3.3 5 6 7 0 89
 Build a 3-bit Asynchronous (Ripple)
Counter (Cont.)
• To expand the idea above, the following is the three-bit
asynchronous binary counter that using negative edge triggered J-K
flip flop and its timing diagram for one cycle:

HIGH
Q0 Q1 Q2
J Q J Q J Q

CLK
K Q K Q K Q

CLK 1 2 3 4 5 6 7 8 9
Q0
Q1
Q2
RVK-LDCO-3.3 90
 Build a 3-bit Asynchronous (Ripple)
Counter (Cont.)
• An asynchronous toggle flip-flop can also be built using an edge-
triggered D flip-flop.
• It is common practice to make a D flip-flop act as a T flip-flop by
connecting its D input fed from its own inverted output. Then each
pulse to the clock input will load the D input from the opposite state
at its own inverted output.

D Q Q D Q Q
CLK CLK
Q Q

positive edge trigger T flip-flop negative edge trigger T flip-flop

formed by D flip-flop formed by D flip-flop

RVK-LDCO-3.3 91
 Build a 3-bit Asynchronous (Ripple)
Counter (Cont.)
• Thus, the following is the three-bit asynchronous binary counter
that using negative edge triggered D type flip flop and its timing
diagram for one cycle:
Q0 Q1 Q2

D Q D Q D Q

CLK
Q Q Q

CLK 1 2 3 4 5 6 7 8 9
Q0
Q1
Q2
RVK-LDCO-3.3 92
 Asynchronous Down Counter
• The previous ripple up-counter can be converted into a down-
counter in one of two ways:
1. Replace the negative-edge triggered FFs by positive-edge triggered FFs, or
2. For the negative-edge triggered FFs, instead of connecting CLK input of FF Qi to the
output of the preceding FF (Qi-1), connect it to the complement output of that FF (Q'i-
1).

Asynchronous down
counter with positive
triggered JK flip-flop

Asynchronous down
counter with positive
triggered D flip-flop
RVK-LDCO-3.3 93
 Asynchronous Down Counter (Cont.)

“7” “6” “5” “4” “3” “2” “1” “0”

Q2 1 1 1 1 0 0 0 0

Q1 1 1 0 0 1 1 0 0 Repeats →

Q0 1 0 1 0 1 0 1 0

CLK

RVK-LDCO-3.3 94
 Asynchronous Counter Summary
• Up Counters
– Connect the CLK input to the Q output with the opposite polarity

Q Q

Q CLK Q CLK

• Down Counters
– Connect the CLK input to the Q output with the same polarity

Q Q

Q CLK Q CLK
RVK-LDCO-3.3 95
Asynchronous (Ripple) Up-Down
Counter
 Build a 3-bit Asynchronous Up-Down
Counter
• It can count both in upward & downward direction.

• It is also called as a forward & backward counter or bidirectional

counter so a control signal or a mode signal M is required to choose
the direction of the count.

• For the up or down counters the design of the circuit is the same as.
The only difference is that for the up counter the output is taken at
the non-inverting output ports of the flip-flops. Whereas, for the
down counter, the output is taken at the inverting output ports of the
flip-flops.

RVK-LDCO-3.3 97
 Build a 3-bit Asynchronous Up-Down
Counter (cont..)
• Logic Diagram:

RVK-LDCO-3.3 98
 Propagation Delay
• Due to the "rippling" effect of toggling sequential FFs, there is
a small delay associated with this triggering event
• The rippling effect is due to the input clock pulse triggering
the first FF and then each additional FF triggering it's adjacent
neighbor
• Therefore, the switching of each FF is not all change together
• This propagation delay is a disadvantage to using
Asynchronous Binary Counters.
• The Up-Down counter is slower than up counter or a down
counter, because the addition propagation delay will get
added to the NAND gate network.

RVK-LDCO-3.3 99
 Propagation Delay (Cont.)

CLK 1 2 3 4
Notice how delays
are cumulative as Q0
each stage in a Q1
counter is clocked
later than the Q2
previous stage.

Q0 is delayed by 1 propagation delay, Q2 by 2 delays and Q3 by 3 delays.

RVK-LDCO-3.3 100
Synchronous Counters
 Build a 3-bit Synchronous Up Counter
• A synchronous counter, in contrast to an asynchronous counter, is
one whose output bits change state simultaneously, with no ripple.

• The only way we can build such a counter circuit from J-K flip-flops
is to connect all the clock inputs together, so that each and every
flip-flop receives the exact same clock pulse at the exact same time

Q0 Q1 Q2

? J Q ? J Q ? J Q

? K Q ? K Q ? K Q

CLK
RVK-LDCO-3.3 102
 Build a 3-bit Synchronous Up Counter
(Cont.)
• Examining the four-bit binary count sequence,
another predictive pattern can be seen
• Q0 toggles on each clock pulse
• Q1 changes state on the next clock pulse when
Q0=1
• Q2 changes state on the next clock pulse when
Q0=Q1=1

RVK-LDCO-3.3 103
 Build a 3-bit Synchronous Up Counter (Cont.)
• Each of the higher-order flip-flops are made ready to toggle (both J
and K inputs “high”) if the Q outputs of all previous flip-flops are
“high”.

• Otherwise, the J and K inputs for that flip-flop will both be "low,"
placing it into the "latch" mode where it will maintain its present
output state at the next clock pulse.

• Since the first (LSB) flip-flop needs to toggle at every clock pulse, its
J and K inputs are connected to Vcc, where they will be "high" all the
time.

RVK-LDCO-3.3 104
 Build a 3-bit Synchronous Up Counter (Cont.)
• The next flip-flop needs to only "recognize" that the first flip-flop's Q
output is high to be made ready to toggle, so no AND gate is
needed.

• However, the remaining flip-flops should be made ready to toggle

only when all lower-order output bits are "high," thus there is a
need for AND gates.

RVK-LDCO-3.3 105
Build a 3-bit Synchronous Up Counter (Cont.)

1 Q0 Q1 Q2
J Q J Q J Q

K Q K Q K Q

CLK

This flip-flop toggles This flip-flop toggles This flip-flop toggles only if
on every clock pulse only if Q0 is "high" Q0 AND Q1 are "high"

RVK-LDCO-3.3 106
 Build a 3-bit Synchronous Down Counter
• To make a synchronous "down" counter, we can use the Q' outputs
to enable the toggle mode on each succeeding flip-flop.

1 Q0 Q1 Q2
J Q J Q J Q

K Q K Q K Q

CLK

This flip-flop toggles This flip-flop toggles This flip-flop toggles only if
on every clock pulse only if Q0' is "high" Q0' AND Q1' are "high"

RVK-LDCO-3.3 107
 Build a 4-bit Synchronous Up Counter

1 Q0 Q1 Q2 Q3
J Q J Q J Q J Q

K Q K Q K Q K Q

CLK

This flip-flop toggles This flip-flop toggles This flip-flop toggles only This flip-flop toggles only if
on every clock pulse only if Q0 is "high" if Q0 AND Q1 are "high" Q0, Q1 AND Q2 are "high"

RVK-LDCO-3.3 108
Mod X Counters
 How to Build a Binary Counter to Go from
Zero to Mod Number X
1. Determine smallest number of flip-flop's such that 2N  X. If 2N
= X, skip steps 2 and 3.

2. Connect a NAND gate output to asynchronous clears of all flip-

flops.

3. Determine which flip-flop(s) will be high at count = X

Connect the Q outputs of these flip-flops to NAND gate inputs.

RVK-LDCO-3.3 110
 Build a Synchronous Counter that Counts
from Zero to 13 (X=Mod 14)
• Since 23 = 8 and 24 = 16; thus four flip-flops are required.
• Because the counter is to have stable operation up to the count of
1101, it must be reset to zero when the count of 1110 is reached.
• Therefore, flip-flop outputs Q1 to Q3 must be connected as the
NAND gate inputs as shown in the figure below:

1 Q0
J Q J Q Q1 J Q Q2 J Q Q3

K CLRQ K CLRQ K CLR Q K CLRQ

CLK

RVK-LDCO-3.3 111
 Asynchronous Mod 10 (Decade) Counter
• The binary counters previously introduced have two to the power n
states.
• But counters with states less than this number are also possible.
• They are designed to have the number of states in their sequences,
which are called truncated sequences.
• These sequences are achieved by forcing the counter to recycle
before going through all of its normal states.
• A common modulus for counters with truncated sequences is ten
• A counter with ten states in its sequence is called a decade counter.
• The circuit below is an implementation of a decade counter.

RVK-LDCO-3.3 112
 Asynchronous Decade Counter (Cont.)

HIGH
Q0 Q1 Q2 Q3
J S Q J S Q J S Q J S Q

CLK
K R Q K R Q K R Q K R Q

• Once the counter counts to ten (1010), all the flip-flops are
being reset
• Notice that only Q1 and Q3 are used to decode the count of ten
• This is called partial decoding, as none of the other states (zero
to nine) have both Q1 and Q3 HIGH at the same time
RVK-LDCO-3.3 113
Asynchronous Decade Counter (Cont.)
• The sequence of the decade counter is shown in the table
below

RVK-LDCO-3.3 114
 Introduction to Flip-Flop Excitation Table

• We have described flip-flop behavior by using a transition

table which gives the new state as a function of the present
state and inputs
– This is what we need if we know the state and inputs and was to
determine the new state

• Sometimes, though, we know the state we are in and the

state we wish to be in, and need to know the inputs required
– For this purpose, we can consult an excitation table

RVK-LDCO-3.3 115
 Designing Synchronous Counter with
Arbitrary Sequences
• Synchronous Counter Design by Inspection (already covered)
– Based on the use of T flip-flops (or JK flip-flops in the toggle mode).
Determine when each flip-flop must toggle by observing the bit changes in
the counting sequence
– This method is sometimes useful for simple counter designs
– This method may not yield the simplest solution, but it is typically easy to
perform
• Synchronous Counter Design by Excitation Table
– There are situations where a special sequence is needed that is not a
regular binary pattern, for example, 000, 010, 101, 001, 110, 000, ... Then,
a commonly used technique - excitation table design method would be
employed

RVK-LDCO-3.3 116
Synchronous Counter Design by Excitation Table
• Design Procedure:
Step 1: Determine the desired number of bits (FFs) and the desired
counting sequence.
Step 2: Draw the state transition diagram showing all possible states,
including those that are not part of the desired counting sequence.
Step 3: Use the state diagram to create a state table listing all
PRESENT states and their NEXT states.
Step 4: Determine the type of flip-flop to use (SR, JK, D, or T).
Step 5: Derive the circuit excitation table from the state table for
each flip flop control input.
Step 6: Use K-map to find the minimal Boolean expression for each
Flip-Flop control input.
Step 7: Draw the logic circuits to generate each Flip-Flop control
input to create the counter.
RVK-LDCO-3.3 117
 Counter Design: Example
• 3-bit binary counter
• 3 Flip-Flops are needed
– we will use JK
• Current state and next state
outputs are 3 bits each.
• 3 pairs of JK inputs to specify
• Missing states 1, 2, and 4
– Use don’t cares for these states
035760

RVK-LDCO-3.3 118
Counter Design: Example (Cont.)
The state table is created from the state diagram

u
n
u
s
e
d

s
t
a
t
e
s
X = d = don’t care

RVK-LDCO-3.3 119
 Counter Design: Example (Cont.)
• A Karnaugh Map is created
for each of the six control
inputs.

• These yield the Boolean

equations that specify the
control inputs.

• The J input for Flip-Flop B is

notable.

RVK-LDCO-3.3 120
 Counter Design: Example (Cont.)
• The Boolean equations are used to construct the logic circuit
diagram for the counter
– Signals are labeled

JC = A JB = 1 JA = B
KC = A∙B KB = A+C
RVK-LDCO-3.3 KA = C 121
Registers
 Registers
• A register is a collection of flip-flops that act as an extension of a
flip-flop which can store multiple bits.

• It has two basic functions: Data Storage and Data Movement.

• A shift register provides the data movement function where it is

capable of shifting their binary contents in one or both directions
(shifting data to the left or right).
– It “shifts” its output once every clock cycle

RVK-LDCO-3.3 123
 A Basic Register
• Basic registers are easy to build. We can store multiple bits just by
putting a bunch of flip-flops together!

• A 4-bit register with its internal implementation is as shown below

– This register uses D flip-flops
– All the flip-flops share a common CLK and CLR signal

RVK-LDCO-3.3 124
 Shift Registers
• A shift register "shifts" its output once every clock cycle.

Q0(t+1) = SI
Q1(t+1) = Q0(t)
Q2(t+1) = Q1(t)
Q3(t+1) = Q2(t)

• SI is an input that supplies a new bit to shift "into" the register

• For example, if on some positive clock edge we have:
SI = 1
Q0-Q3 = 0110 then the next state will be:
Q0-Q3 = 1011
• The current Q3 (0 in this example) will be lost on the next cycle.
RVK-LDCO-3.3 125
 Basic Shift Register Operation
• Some basic data movements are illustrated here:
– Serial In Serial Out(SISO)
– Serial In Parallel Out(SIPO)
– Parallel In Serial Out(PISO)
– Parallel In Parallel Out(PIPO)
Data in

Data in Data out Data out Data in

Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out

Data in

Data in

Data out Data out

Serial in/parallel out Parallel in/parallel out Rotate right Rotate left
RVK-LDCO-3.3 126
 Data Movement
• Block diagrams for shift registers with various input/output options:

RVK-LDCO-3.3 127
 Serial Transfer vs. Parallel Transfer
• Serial transfer
– Information is transferred one bit at a time
– Shifts the bits out of the source register into the
destination register
• Parallel transfer:
– All the bits of the register are transferred at the
same time
• For example:
– Older printers use parallel data transfer
– USB devices use serial data transfer

RVK-LDCO-3.3 128
 Parallel Data Transfer

Parallel data transfer moves data from one register

to another at one time

Reg. A Reg. B

clock

When clock occurs, all bits of A are copied to B

RVK-LDCO-3.3 129
 Serial Data Transfer
One application of shift registers is converting between "serial data" and
"parallel data“

Serial transfer moves data bits from A to B one bit per clock Rx and Tx
have single wire between the two.

For ‘n’ bit registers, it takes ‘n’ clocks for data move

1 bit
signal
Reg. A Reg. B

clock Usual implementation is with a shift register

RVK-LDCO-3.3 130
 Serial Data Transfer (cont..)
• Typical serial transfer is a multi-step process
– Load transmit shift register with data to send
– Shift data bit by bit from transmit to receive shift register
– Transfer received data to other registers

• The transmit shift register must have parallel load

– This is known as parallel to serial shift register

• The receive shift register must have parallel outputs

– This is known as serial to parallel shift register

• Other control/timing signals usually needed

RVK-LDCO-3.3 131
 Serial Data Transfer (cont..)

Parallel
Transmit
Data
‘n’ bits
load 1 bit signal
(serial data)
L
S
Reg. A (P to S) Reg. B (S to P)

‘n’ bits
clock
Parallel
Receive
Data
RVK-LDCO-3.3 132
Thank You!

RVK-LDCO-3.3 133