©Thorn EMI Television Rentals Group Technical Training Department

1979,1980,1981,1982,1985

All rights reserved. No part of this publication

may be reproduced or transmitted, in any form
or by any means, without permission

Part 1 originally published as Book 9 Microproct~~~ors, 1982

Part 2 originally published es Book 10 Microprocessor controlled systems, 1984

Published in this format in 1985 by

MACMILLAN EDUCATION L TO
London and Basingstoke
Companies and representatives
throughout the world

British Library Cataloguing in Publication Data

An introduction to microprocessor systems.-(Thorn
EMI Macmillan series)
1. Microprocessors
I. Thorn EMI Television Rentals II. Series
001.64'04 QA76.5

ISBN 978-0-333-36414-7 ISBN 978-1-349-07075-6 (eBook)

DOl 10.1007/978-1-349-07075-6
An introduction to microprocessor systems
THORN EMI Home Electronics Macmillan Series

An introduction to digital techniques books

An introduction to digital techniques
Digital displays and applications
An introduction to microprocessor systems
VHS recording principles

Tutor boards
Digital tutor board with exercises
Transistor tutor board with exercises

Video tapes
Introduction to microprocessor systems
Introduction to the Teletext system
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Basic mathematical skills

Contents

Part 1 Microprocessors 1
The processor 3
The program 15
The 6502 microprocessor 20
Programming the microprocessor 28

Part 2 Microprocessor controlled systems 41

Introduction 43
Digital and analogue interfacing 44
Digital to analogue conversion 45
Analogue to digital conversion 51
Analogue signal timesharing 59
Digital system timesharing 66
Digital data transfer 72

Glossary 79
Appendix 81
Index 85
 Part 1

Microprocessors
 CHAPTER 1 Data i n - Processor-Data out
Select line Select line
Low(NOR) High(NAND)

THE PROCESSOR Data

mput
A
8
Transfer
function X
Data
output
A
0
B
0
X
1
X
1
The microprocessor is a uniquely versatile logic Fig.1.1 1 0 0 1
device. Mere precisely, it is a variety of logic devices

:=o-x
etched onto one silicon chip. 0 1 0 1
The versatility of the microprocessor stems from its 1 1 0 0
ability to follow a series of definitive instructions called
the program. That is, unlike oth~r large-scale
integration (LSI) devices, the microprocessor is not
dedicated to one specific task or set of tasks but can
Fig. 1.2 The NAND gate Fig. 1.5 Truth table for NANDINOR package
perform an infinite variety offunctions depending
upon the instructions within the program.

Data processing
The basis of data processing may be shown by the A B X
drawing in figure 1.1. The data is applied to the 0 0 1
A Select Funct.
processor on lines A and Band the data output is 0 1 1 X
available on line X. The relationship of data input to B 00 AND
data output is expressed by the transfer function ofthe 1 0 1
01 NAND
processor. 1 1 0
10 OR
An example of transfer function is shown in figure Select
1.2. In the case of a single gate, the transfer function lines 11 NOR
has been given a name; this is the NAND function gate. Fig. 1.3 The NAND truth table
It may be expressed in Boolean form as X= A . B or the
function may be represented in tabular form like the
A Fig. 1.6 A 4-function package
truth table in figure 1.3.
X
(See Appendix for more on Boolean notation). B
Although the single logic gate is a very useful
Logic 1
building block, its function is determined by its design
and cannot subsequently be modified. Select OLogicO
A more useful device would be one that could Fig. 1.4 NAND and NOR in one package
perform two functions. For example, NAND and NOR Select Funct.
(figure 1.4). Again, there are two data input lines and Adding a third select line would allow up to eight (2 3 ) 000 AND
one data output line, but now the transfer function will functions inside the one package. In figure 1.7 there are
depend upon a third input called the 'select' line. With AND, OR 001 NAND
the four basic functions, plus Exclusive OR, Exclusive A
a logic 1 on the se!!!£!1ine the transfer function can be NAND, NOR 010
NOR, add and subtract. x.OR,x.NOR X
OR
expressed as X = A . B (i.e. NAND). lfthe select line is The inclusion of the add and subtract facility is B Add, 011 NOR
at logic 0, the transfer function is X= A+ B (i.e. NOR). important because it gives the device arithmetic Subtract
Figure 1.5 shows the truth table for this device. 100 Ex. OR
capability as well as the logic functions already
If all four basic logic functions were contained in one discussed. In data processing terminology, such a 101 Ex. NOR
package, two select lines would be needed in order to device could now be referred to as an Arithmetic/Logic Select 110 Add
determine which transfer function is applied to the lines
Unit or ALU and it forms the heart of all but the 111 Sub
in-coming data. Figure 1.6 shows the device and the simplest operations carried out upon the data.
effect of different logic conditions on the select lines. (See Appendix for details on binary arithmetic). Fig. 1.7 An 8-function package

3
 Bits, bytes and words
In the construction of the ALU, two data input lines, A
and 8, and one data output line, X, were considered.
Each ofthese lines may be in one of two conditions, i.e.
logic 1 or logic 0 and can therefore each represent one
Data A 1 --+---.,_--f"--l binary digit. The contracted form of binary digit is bit.
word A A 2 --+--;. In figure 1.8, the data capacity ofthe ALU has been
doubled. Data input A now has two bits, data input B
--+--X 1 Data
has two bits and data output X has two bits. The ALU
---t--X 2 word X may now be said to operate upon data words which
Data 81 --+--' are two bits wide.
word B 82 --+----1----i A data word of eight bits may be expressed as one
L-----' byte. For example, a 16-bit word is made up of two
bytes, a 24-bit word is three bytes wide, and so on.
An ALU with two bit data word capacity, as shown in
Function select figure 1.8, would have limited use in a microprocessor.
lines If its capability was extended to 8-bit words, .however,
a much more practical design would result. In figure
Fig. 1.8 A 2-bit ALU 1.9, if the NAND function was selected, for example,
each of the corresponding bits of the two 8-bit words
would be acted upon by the ALU to effect the NAND

-}
transfer function and produce an 8-bit result at the

{
output. Figure 1.10 shows the result.
8 ==== Word A-
lines
-
8 bit ==== 8bit
r-WordX ====data
ALU
result

8 ====}
lines WordB-

0 0 1
Function select
lines

Fig.1.9 An8-bitALU

bit 8 7 6 5 4 3 2
Word A 0 1 1 0 1 0 0 1
WordB 1 1 1 0 0 1 0 1
Word X 1 0 0 1 1 1 1 0

Fig. 1.10 The NAND function applied to a/18 bits in parallel.

4
The data port and bus
The object of the exercise so far has been to design a
versatile arithmetic -logic unit into one IC package.
Data
However, in the last example (figure 1.9), twenty-four direction
pins have been used for data routing (two 8-bit inputs

~~}?:
ALU
and one 8-bit output) which is extremely wasteful. A
more practical solution would be to reduce the number
of data pins to eight, that is, the minimum needed to
accommodate one data word. This data port will now / r---...............
be the in put for the two data words and also the output Data
for the result. A separate control section is employed port
to switch these lines inside the device to avoid input
and output occurring simultaneously (figure 1.11 ). The
eight data lines are referred to as the data bus. Select

Internal registers Fig. 1.11 The ALU using a single Data port
As both the input words cannot be available on the
data bus simultaneously, they must be held outside in
a memory and brought, one at a time, into the unit
where they are stored in two 8-bit registers. One of Data
,;
-
these registers is called the Accumulator (ACC), the
other; the data buffer (figure 1.12). The control section 8

-{
now fetches the data words one at a time from the \.

}
Ace.
memory, and routes them via the internal data bus to 8 Data
the appropriate registers, so that the ALU (which is Memory
switch
also acting on command from the control section) may 0
'
perform the required function. Data I
bus ALU ~
8
System clock
The action of, for instance, adding two 8-bit numbers (}
must now be carried out by a sequence of small steps
which are initiated by the control section. The timing is Data
Data ) buffer
quite complex and so the whole system needs to be

J
synchronised. The system clock is provided for this
purpose.
The output from the clock is simply a squarewave at Control
a frequency in the range 100kHz to 4MHz (for NMOS System
clock
microprocessors), rising and falling between 0 and 5
volts. I I
III
Select

Fig. 1.12 The Accumulator (Ace.) and the Data buffer

allow temporary storage of the data

5
 Instructions and program
As the logical or arithmetic function that is actually
performed on the data by the ALU depends upon the
state of the three select lines, the 3-bit number that is
applied to these lines can be called an instruction.
Data
Howeve1:, things are more complicated now and in

-
8 \ order to fetch the data from memory and route it to the
registers, perform a logical or arithmetic function or
'
}
Ace. store a value back into memory, many more
~~~-{ 8
, Data
switch
{~
instructions will be needed than can be
accommodated on the three select lines.
Oata
bu s 8 • ALU 1-
By increasing the number of select lines to eight, a
possible maximum of 256 (2 8 ) instructions are
available which should be more than adequate (figure
(\ 1.13).
Now it can be arranged that certain binary numbers
from 00000000 to 11111111 cause the control to carry
"'
Data
Data
buffer out particular functions. For example, 11000101 could
mean: 'fetch a data word from memory and store it in

Control
J, the accumulator'. Or 00111010 could mean: 'add the
contents of the accumulator to the contents of the data
buffer' and so on.
Clock
These are 8-bit instruction words, each of which,
Ill 1111 when executed, will cause a different electronic
11111111 function to be carried out in the device.
~
Instruction
As already mentioned, adding two data words
together may require a number of instructions to be
applied to the control sequentially. These instructions
form the system program and must be stored in
Fig. 1.13 The binary pattern applied to the 8 select another memory in the same way as the data words
lines is an instruction to the control section. (figure 1.14).

6
Reset
By incorporating a reset pin on the processor the
internal circuitry can be arranged so that whenever
this pin is taken to ground (logic 0), the control looks at
the first instruction in the program memory. This could
be: 'fetch the first data word in the data memory and
store it in the accumulator'. When-it has done this it will
look at the second instruction and perform this and so
on, until it has completed all the instructions.
The logic device has grown from the original NAND
~J.
Data
gate of figure 1.2. It can now:
Fetch data from the data memory. 8

----
Store data in the internal registers.

}
\.
Perform one or more logical functions on the data. Ace.
Store the result in either one of the internal Data a, Data
registers or back into the data memory. Memory switch
0
In essence, this is exactly what a large computer
does and our logic device may rightly be called a data
processor.
Data
8 • ALU ....
Although the processor, as designed, would work, it ().
is rather inelegant. There are a number of
improvements that can be made which may be clear Data
Data /
buffer
from figure 1.14. For example, if both data and
instructions are 8-bit words, could the instructions be
transferred from the program memory to the control
via the data bus and so cut out eight pins on the Control
J
processor? The answer is yes, but only ifthe processor Clock
has some method of identifying which 8-bit binary ~
word on the bus is data and which is an instruction. If
the two ever became confused, the result would be
rubbish.
Instruction
(Program)
memory } 8
I
~
II 111111

Instruction bus
l
Reset

Instructions

Fig. 1.14 The list of instructions (the Program) must be

held in memory to be applied in sequence to the
control section.

7
 Memory address
First of all, it can be arranged that after the reset button
has been pressed, the processor takes the first 8-bit
word from program memory and assumes that it is an
instruction. However, ifthe first instruction called for
the processor to fetch a data word from memory, the
processor would need to know the precise location in
which the data was stored.
This requires that each memory location has an
individual number and this unique number is called
the memory address.
For example, figure 1.15 shows a simple memory
device which contains four 8-bit memory locations (a
32-bit memory). To select a particular memory
location, a 2-bit binary number is applied to the
address input lines AO and A 1. These control the binary
8 (21ineto41ine) decoder which will apply a logic 1 to the

{
::::::~ select line of one location depending upon the applied
-02
-03
address.
-04
-05
-06 Binary A1 AO Selected
A1 -1--:----1 8 -07
Address Location
Data bus
0 0 0 0
1 0 1 1
2 1 0 2
3 1 1 3

R/W In this way, any location within a memory device is

Fig. 1.15 4 byte (32-bit) Read/Write memory (RAM)
accessible and will always respond to a unique binary
address number.
When selected, the contents ofthe location are
made available at the eight data pins DO- 07 which
will connect to the data bus of the system.

Read/Write control
So that our data processor may write data into the
memory as well as read from it, each memory device
will contain a Read/Write (R/W) control section. The
function is selected by the data processor, using the
R/W input.
The write sequence would be as follows:

8
1. The processor applies the required address
number to AO and A1.
2. The data that it wishes to store is put onto the data
bus and at the same time the processor takes the
read/write line low (logic 0). writing the data into
the selected location. Address
inputs

Practical memory storage A0--+----1 t--+--oo

Al--+----1 t---+--o,
Even the simplest data processor will, however, A2 --+----1 Address 128x8 Input/ 02 To
Memory output t--+-~
require more than four bytes of memory to operate. ~~ decoder locations buffer
data
A5--+----l t---+--o 5 bus
A commonly used memory device contains 128 x 8-bit A6--+---i t--+--os
locations or 128 bytes. To address each location 1--+--07
uniquely, requires a 7-bit binary address code and
therefore at least seven address pins will be provided
on the device (AO-A6). This device is referred to as 1K
RAM. That is, 1024 ( 128 x 8) bits of Random Access
Select lines
,_--+-- R/W
Memory; so called because each location is
individually addressable. Its internal organisation can
be seen in figure 1.16.

The 3-bus system Fig. 1.16 128x8bit(1K)RAM

In the system diagram of figure 1.17, it can be seen that
as well as the data bus, a control bus and an address
bus are now required.

The control bus

The control bus is made up of various signal lines
carrying inputs and outputs to and from the MPU and
other system components. Three of these lines (R/W,
reset and the clock signal) have already been
discussed, the others vary according to the particular
microprocessor involved and will be considered more System
memory
closely in Chapter 3. (program
and data)
The address bus
This bus is required in order to select individual
memory locations. Currently, it is common for micro-
processors to have a 16-bit address bus. The extremes
of the addressable range are therefore:
from AO - A 15 all Os i.e. 0000000000000000
to AO - A 15 all 1s i.e. 1111111111111111
This allows the MPU to directly address 65536
separate 8-bit locations which, by convention, is
referred to as 64K (where K is 1024 ).
10 Fig.1.17 The3-bussystem

9
Addresses in hexadecimal notation Decimal to hexadecimal
Unfortunately, humans find the handling of 16-bit The decimal value 18,603 may be converted to
binary numbers extremely difficult. For example, here hexadecimal in the following way:
is a 16-bit binary address:
1000001111101010 18603116 = 1162 remainder ..................... 11
Try copying it onto a spare piece of paper. 1162 I 16 = 72 ...... remainder ...... 10
Now imagine that you had to write a program
consisting of thousands of such numbers. Qujte 72 I 16 = 4 .... remainder .... 8
plainly, it would be impossible to achieve one hundred 4116 = 0 remainder 4
,J,
per cent accuracy throughout that-program. 4 8 A 8 16
Unfortunately, the microprocessor is completely
incapable of recognising an error of the sort that may Therefore the hexadecimal equivalent of 1860310
result from using binary notation in this way. A one bit is 48AB 16
error is quite likely to cause a complete program to fail.
Hexadecimal notation is a system of counting to the
base 16. Figure 1.18 shows the digits used in this
system.ln order to represent 0-15 with different
digits, more digits are needed than we are used to 16 3 16 2 161 16°
seeing in the decimal system. Therefore, after 9, letters 0 0 0 0
ofthe alphabet are used. Thus: 1
2
A= 10 3
B = 11 4
c = 12 5
6
D = 13 7
E = 14 8
F = 15 9
A
Hexadecimal to decimal conversion B
c
The columns in figure 1.18 have the values: D
E
16 3 16 2 161 16° F
1 0
These are equivalent to the decimal values: 1 1
4096 256 16 1 1 F
Therefore, the hexadecimal number 1 2 D F 2 0

may be converted to decimal by multiplying each digit 9 F

A 0
by its associated column decimal value and adding the
products, i.e. F F
1 0 0
1 X 4096 = 4096
F F F
2 X 256 512 1 0 0 0
D (13 10 ) x 16 = 208 F F F F
F(15 10 ) x 1 = 15
4831 10 Fig. 1.18 Hexadecimal numbers

10
Binary to hexadecimal to binary Address pagination Read-only-memory and the system program
Although decimal/hexadecimal conversions are Now the extremes of the microprocessors addressable The system as shown in figure 1.17 contains a micro-
sometimes necessary, when programming micro- range can be expressed much more conveniently in processor and a system memory but as yet no means
processors in machine code, it is the relationship hexadecimal as OOOO(h) to FFFF(h). of loading memory with either instructions or data. If
between hexadecimal and binary that becomes This 4-digit hexadecimal number can be considered the reset button was pressed now, the microprocessor
important. to be. made up of a two digit page number followed by would look at the first location in memory and treat it
Here is that 16-bit binary number again, but now it a two digit byte number. as an instruction. It has no way of telling that the RAM
has been split into 4-bit groups. For example: devices contain meaningless binary numbers and not
Group 1 Group 2 Group 3 Group 4 Hexadecimal address 1___....._
0
valid instructions or data. Exactly what the micro-
B
___....._5 processor will do is indeterminate because random
1000 0011 1110 1010 means Page 10(h) access memory is volatile. That is, it forgets its
In binary notation 4-bits may represent values from and Byte B5(h) contents when its supply voltage is removed and when
0 to 15 10 . powered up again, contains a completely random set
Therefore, the 64K address field comprises 256 (FF) of ones and zeros.
It follows then that each 4-bit group may be pages with 256 bytes within each page boundary. The way out ofthis situation is to store some or all of
represented by one hexadecimal digit. For example: the instructions and data in a Read Only Memory or
Treating each group as a 4-bit binary number, Addresses OOOO(h) to OOFF(h) are all on Page 0. ROM. As the name suggests, the microprocessor can
But the next address, 01 00( h) is the first on Page 1, and only read out the information in the ROM, it cannot
810 410 210 110 soon. write into it. The big advantage of ROM over RAM is
Group 1 is 1 0 0 0 = 816 Figure 1.19 shows this idea graphically with a that it is non-volatile. That is, it will not lose its contents
Group2 is possible (but not very practical) example of a memory when the power is removed.
0 0 1 1 = 316 decoder. The top eight lines of the address bus (AS to It can be arranged for the ROM to occupy the area of
Group3 is 1 1 1 0 =(1410) = E16 A 15) are taken to an 8 line to 256 line decoder which memory that the microprocessor goes to for its first
Group4 is 1 0 1 0 = (10 10) =A,& selects the page. The lower eight bus lines (AO to A7) instruction after reset. This will cause the micro-
are fed to the address input pins of the memory processor to run through a list of instructions which
giving a hexadecimal value of 83EA 16 . devices that make up the pages in order to select a will be the system program. The exact nature ofthis
This number is easier to produce or copy accurately particular 8-bit location. program will depend upon the requirements ofthe
than the equivalent binary value. Figure 1.19 also shows that although the decoder system but will at the very least ensure that the micro-
When working the other way, that is from hexa- has 256 page selection outputs, there need not be processor is in a pre-arranged and stable condition
decimal to binary, the process is simply reversed. For memory devices connected to all of them. ready for any demand that may be placed upon it by
example, the hexadecimal number 3F is split, and a
external devices.
4-bit binary number produced for each digit.
Hexadecimal 3 F --------------.
= Binary 0011 1111 A8-A15
-----v
8 line to 1-of-2561ine decoder

256memory
locations

AO-A7 _ _ _ _ _ _ _ _ _ _ _ _ _____,

Fig.1.19 A 161ineaddressdecoder
AB -A 15 select the page. AO -A 7 select the byte.

11
 Figure 1.20 shows the microprocessor unit (MPU)
Stack and connected via its address and data buses to the system
System program
ROM
Scratch pad program ROM. Even in this basic configuration some
RAM RAM must be provided for the program so that it can
store interim results of calculations for later use. This is
called scratchpad RAM.
Also, under certain program conditions, which will
be discussed later, the MPU will need to store the
contents of some of its internal registers in a small area
of RAM. This RAM is usually reserved for the exclusive
use of the MPU and is called stack RAM.
Fig. 1.20
Tri-state buffers
\ \
\ PO
~ ~
v P1
Input/output
The circuit of figure 1.20 can be considered to be
common to all microprocessor based systems.
However, in order that it may perform a useful
function, it must be able to communicate the results of
its calculations to outside circuitry and devices.
Similarly, almost all applications require that data
from external logic be made available for the micro-
processor's use. In short, all MPU systems need input/
output interface circuitry.
There is usually a strict protocol concerning data
input and output which is inherent to the design of the
MPU. This has led to the use of special ised Input/
Output (1/0) devices which will connect to the address
and data buses ofthe MPU system. Figure 1.21 shows
a typical parallel input and output (P/0) device
arrangement.
The PIO shown consists ofthree registers and eight
tristate buffer amplifiers. The lines PO- P7 form the
PIO output port and it is these lines which will connect
to external circuitry.
The three registers connectto the common data bus
and are individually selected by the logic levels of

address line AO and the R/W line as shown in

_v P2
figure 1.21.
~'b"' v ...
P3

The data direction register (DDR)

Address
v P4

Each ofthe eight port lines PO-P7 may be configured

~decoder v P5
either as an input or an output in order to match the
v P6
function of external circuitry.
For example, if the system calls for outputs on all
1
~
P7
port lines (PO- P7), the binary value 11111111 2 ,
would be placed in the DDR, thus switching on all the
Data output
Data
Data input tri-state buffers. Alternatively, ifthe system required
~ direction
register register register that lines PO to P5 should be inputs and lines P6 and P7
outputs, the binary value of 110000002 would be
E1 I ' I
E2 E1 I • I E1 j fj E2
written into the DDR, switching on those buffers
D0 - 07 Data bus associated with P6 and P7 only.
The remaining buffers are off and present a high

~
impedance to the lines PO- P5, allowing external
R/W circuits to drive the lines up or down.
This versatile method of configuration ofthe 1/0 port
AO
-[>o-1 lines allows the program to set and alter the function of
each line at any time during program execution.

Fig. 1.21 Parallellnput/Output device (P/0)

12
Data 0/P and 1/P Registers (DOR and DIR)
Having configured each line to suit the external
circuitry, the program may alter the logic levels at the
output port lines simply by writing a new value into the
DOR.
Similarly, to sense the logic levels ofthose port lines
acting as inputs, the contents ofthe DIR are read and
the binary value interpreted in the MPU .
Address decoding
The external address decoder selects the PIO by
activating the Chip Select (CS) line when the address
on the address bus is within a certain range. Address
line AO is then used to select a particular internal
register (in conjunction with the R/W line). This results
in the DDR responding to one address and the DOR and
DIR share another. In this way, the PIO looks like two
standard memory adresses to the MPU and simplifies
the handling of data to and from the 'outside world'.
In most PIO devices, the circuitry of figure 1.21 is
repeated to allow two 8-bit ports to be controlled
through just one 1/0 integrated circuit. A second
address line (A 1) is added to allow selection of the
duplicate register set for the other port. The PIO now
appears to the MPU as four memory locations.
By using such an 1/0 device, the protocol of data
A minimum configuration microcomputer
The diagram of figure 1.22 shows a minimum
configuration for a microprocessor system.
Along with the microprocessor, the system requires
a list of program instructions which is held in ROM.
Some RAM is required so that the program can store
interim results of calculations and finally, some form
of 1/0 device must be supplied so that the system may
communicate with external circuits. These devices
form the absolute minimum requirement for the
system to deserve the title of a microcomputer.
The microcomputer chip
Since the introduction ofthe first microprocessor, the
scale of integration possible on a single chip of silicon
has grown considerably. As a result, it is now possible
to incorporate all the devices that form the minimum
configuration into one IC.
IC1 IJPD552C 045
400kHz
Clock
Port co
C1
C2
C3
As the ROM, RAM and 1/0 devices are all inside the
device, it is no longer necessary to make the address
and data buses available to external devices. This frees
many of the package pins for buffered 1/0 connection
to the outside world.
The THORN EMI Ferguson electronic VHS tape
recorder 3V23 contains a number of these specialised
ICs and figure 1.23 shows the pinout arrangement of
one of them. The pins are labelled according to their
particular function within the equipment.
While this level of integration is extremely practical
in high-volume production, the 'discrete' system using
separate ROM, RAM and/or 1/0 will remain the usual
solution for small runs or for products that may need to
be developed or expanded. In a discrete system, only
the program ROM need be changed to effect either
minor or major changes to the way in which the
system functions.
Clock 42 400kHz Clock
VGG 10v
Counter up/down
83 H =up L =down
82 Count zero reset in
81 Count pulse input

l
input and output may be strictly controlled by the MPU
INT Port 80
or, more precisely, by the system program and the Low = Count display
data and address buses are protected from severe Reset A3 Display address data
loading effects that could occur through direct Port DO A2 4 bit parallel input
connection to the external circuitry. D1 A1

Data D2 Port AO

System program Input/Output

in &out Week data out

Digit out Port

D31
EO
b
11
J 1st
2nd out
ROM device (PIO)
E1 Port Io Dot 2. Repeat col. out
E2 H3
E3 H2 Counter! 100 out
0!100=H
Port FO H1
Counter zero out
F1 Port HO Counter zero = H
F2 G3
MPU
F3 G2
Test G1
Vss Port GO

Fig. 1.22 A minimum configuration system Fig. 1.23 An example of a microcomputer on a chip

13
The memory map
Figure 1.24 is an example of a Memory map which is

T
the customary way of showing how the various areas
of a microprocessor's addressable range have been
allocated. It is important to realise that the 8K

1
organisation of memory shown in figure 1.24 is just
one example of an almost infinite number of config-
urations possible. The size ofthe program ROM and
RAM devices will depend upon the level of
complication of the overall function of the system.
Similarly, the number of channels of communication
required will determine the need for more or less Allocated
Input/Output ports mapped into the system.
The program is shown to reside in BK bytes of ROM
located between the addresses EOOO(h) and FFFF(h).
D
Unallocated
The placing of the program ROM at the upper or lower
extremes ofthe addressable range is quite common.
The choice between the two is largely dictated by the
address which the MPU puts onto the address bus DDA Pon 8 0823} PIO
after the reset input has been activated. Atthis address Pon 8 0822 - - ~mEm!mtlrmitm:ml~D~ ...,_4 bytes
DDAPonA0821 F
(and also the following one), the MPU expects to find Pon A 0820 03FF
the starting address of the program.
Chapter 3 explains the exact reset sequence for the
6502 microprocessor which is typical of many
commonly available MPUs.

Fig. 1.24 Memory map (not to scale)

A data processing system
lfthe minimum configuration system of figure 1.22 is
considered as one block as in figure 1.25, the similarity
to figure 1.1 at the beginning of this chapter can be
seen. Data in--Processor--Data out
As in figure 1.1, data is accepted atthe input, a
specific transfer function (or set of transfer functions)
Data
is applied to the data and the result is accessible at the processor
output. The major difference between the simple gate system
of figure 1.2 and the microprocessor is that the
function ofthe gate is fixed by its design, i.e. hardware
defined. With the microprocessor, the function is
software defined and may be altered slightly or
completely simply by changing the system program. Fig. 1.25

14
 CHAPTER 2
THE PROGRAM
Chapter 1 dealt exclusively with the hardware side of
a microprocessor system. That is, the microprocessor
and the support devices which make up a minimum
configuration system. However, all this hardware is
completely useless without a set of instructions which
tells the processor exactly what to do and the order in
which to do it.
The procedure followed by a microprocessor may
be simply expressed as a sequence of two steps. That
is:
1. Fetch- Get the next instruction from memory.
2. Execute- Carry out the instruction.
The microprocessor will continue this process for as
long as power and the system clock signal are
maintained. The instructions which the micro-
processor is executing form the program.
To arrive at a program that actually achieves the
objectives set for the system, each individual action
required ofthe processor must be carefully listed. A
simple method of representing the program
procedure graphically has been in use for many years.
This is the flowchart.
Flowcharts
All but the very simplest actions may be expressed as a
series of small steps and, when dealing with intelligent
action, these steps fall into two broad categories.
These are processes and decisions. The flowchart
represents these as rectangles and diamonds
D
respectively as shown in figure 2.1.
C--------)
Multiple
Terminator process
D
Single
process
Fig. 2.1 The basic flowcharting symbols
PROGRAM EXAMPLE 1
As an example of the use of flowcharts, the simple
After the decision of step 3, a second decision, about
the interest value of the programme, has to be made
process of switching on a television receiver and and so on. Eventually, having exhausted all
searching for a programme of interest, is broken down programmes on all channels, there is nothing left to do
into small steps. The resulting flowchart is shown in but switch off and retire.
figure 2.2.
After switching on the receiver, the viewer waits for
the picture to appear. These two actions are processes
and are represented by the rectangles 1 and 2. During
the wait period, the first decision is being made i.e. is
the picture up? The decision is represented by a
diamond. The diamond should always have one path
leading in and two paths leading out. The two output
paths represent the true and false results of the
decision. In this case, the false result leads the viewer
back to perform the previous process once again. Switch on
TV receiver
It can be seen that this example is not complete. If
the receiver was faulty, the viewer would be waiting
for ever. This is known as an infinite loop and can
happen in computer programs too if they are not
carefully designed. In real life, of course, there would Wait for
picture
be a control within the loop, which would cause some
other action to be followed if the picture took too long
to appear.
Watch for
awhile
Switch off
and go to
bed
Fig. 2.2 Program example 1 flowchart
15
PROGRAM EXAMPLE 2 STEP 1 -INITIALISE PIO The method used to produce the correct number on
In the next example, the problem is of a more technical As was seen in Chapter 1, the PIO port lines may the display is discussed fully in the explanation of
nature. It is typical ofthe many small functions carried each be configured either as an input or an output flowchart step 8.
out in the television receiver by discreet components by clearing or setting the associated bit in the data
that will eventually be handled by one microprocessor. direction register.
Figure 2.3 shows the circuit diagram of the inter- For this particular application, port lines PO- P6
face between the microprocesso r system and a must be configured as outputs and P7 as an input.
channel number indicator. Therefore, the data direction register needs to be
One port of the PIO device has been allocated to this loaded with the following binary pattern.
function. Seven ofthe port lines (PO- P6) are con-
figured as outputs and are driving the cathodes of the P7 P6 P5 P4 P3 P2 P1 PO
display LED's via buffer inverters. P7 ofthe PIO is used 0 1
as an input and is connected to the switch 51. This
Therefore, the initialisation of the PIO for this
switch would be the channel advance button
application would be to store the hexadecimal value
(assuming a simple channel stepping function is
7F(h) in the DDR.
required).
The problem is as follows. At switch-on, the micro-
STEP2-SET COUNTTO 1 AND DISPLAY
processor must display channel 1. Each time the
The microprocess or must be aware of the current
channel button is pressed, the number must be
number being displayed so that when the channel step
advanced until channel number 8 is displayed.
button is pressed, the correct display will follow. A
When S 1 is next pressed, the display should revert to a
convenient memory location is chosen to hold the
number 1.
Figure 2.4 shows the flowchart that describes all the binary equivalent of the displayed number and, for
reference purposes, is given the name 'counf.
processor actions necessary to satisfy the
The value 1 is loaded into count and the same value
requirement.
is displayed on the 7-segment LED. From now on, the
program will ensure that the value in 'count' always
reflects the displayed number.
+Vee
Common
anodes
PO a
P1 b
a ®
P2 c =
P3 ~~ g b~
PIO
d
= ®
Fig. 2.3
P4 e ~e d c~
P5 =
Data bus P6 g @)
P7
S1
..Cl...
<>--+Vee
No

Ov

Fig. 2.4 Program example 2 flowchart

16
STEP 3 - TESTS 1
The method that the microprocessor uses to test the
channel switch is straightforward. The MPU reads the
contents of the input register in the PIO and places it
into the accumulator. It then ignores the binary values
of bits 0-6 and tests bit 7 for a '1 '.

STEP 4 -IS S 1 CLOSED?

If bit 7 is logic '0' then the switch remains open and the
program branches back to the beginning of step 3. This
is another program loop which the MPU will happily
follow for ever if the switch remains open.
As soon as the switch is closed, the next pass +Vee
through step 4 will reveal a logic '1' in bit 7 ofthe Common
accumulator. The loop will not now take place and the anodes
PO a
MPU will pass onto step 5.
P1

-
b
a
STEP 5 -INCREMENT COUNT P2 c
~f
0
The contents of the byte in memory which was given P3 9 b'
d
the name 'count' is incremented, (i.e. count becomes 0 =
PIO
count+ 1 ). 0
P4 e ~e d c~
P5 =
0
STEP 6-IS COUNT= 9? AND STEP7-SETCOUNT
P6 9
TO 1. 0
The test in step 6 ensures thatthe number nine is never P7
S1
displayed. Instead, when true, this decision results in ..r:::J..
o---+Vee
the contents of count being reloaded with the number
1 and this will be the next number displayed.
lfthe result ofthe test is false, the number in count is
not adjusted. Ov

STEP 8 - GET SEGMENT CODE

The method used to produce the correct display to
Fig. 2.5 Writing the value of 'count' directly to the PIO
reflect the value of count is not straightforward. For
instance, writing the value in count directly to the PIO
port would not have the desired effect.
E.g. figure 2.5 shows the resulting display if count
was 3, which is obviously incorrect.

17
 If the system was a microcomputer chip and the
designer was short of port lines, he may opt for the
solution in figure 2.6. Only four lines of port A are
used and these will reflect the value of count. An
external BCD to 7-segment decoder is used to produce
the necessary drive to the 7-segment display. This
would release lines P4-6 for other functions, but
adds another I C to the system.
Assuming the port lines are available, a more
sensible solution would be to perform the BCD to 7-
segment decoding in software instead of hardware. In
other words, given the necessary information, the
program can produce the correct pattern of 1s and Os
at the PIO port to directly drive the display. Figure 2.7
shows the binary pattern (segment code) needed at
the port to display the number 3.
Unfortunately, there is no direct relationship
between the binary value of count and the 7-segment
code required to display that number in decimal.
Therefore, the segmentcodeforeach numeral that will
be displayed, must be stored in memory for the use of
the program. This is called a look-up table and takes
the form of the table below.
a
=
~f g b~
=
~e d c~ Ov
=

Digit Segment Memory Hex

g f e d c b a address code Fig 2.6 The hardware solution to segment decoding.
1 0 0 0 0 1 1 0 EOOO 06 Lines P4-P6 are released for other uses.
2 1 0 1 1 0 1 1 E001 58
3 1 0 0 1 1 1 1 E002 4F
4 1 1 0 0 1 1 0 E003 66
5 1 1 0 1 1 0 1 E004 6D
6 1 1 1 1 1 0 1 E005 7D
7 0 0 0 0 1 1 1 E006 07
8 1 1 1 1 1 1 1 E007 7F

In the above example, the segment codes are held in 8

bytes of memory between addresses EOOO and E007.
For each value of count, the program of step 8 fetches
the associated segment code from the table.

18
 STEP 9- DISPLAY NEW NUMBER
The segment code is written to the PIO port to drive the
correct segments to display the value of count.

STEP 10- TEST 51 AND STEP 11-51 OPEN?

The actual time taken by the microprocessor to
execute the program between the true result of step 4
(51 closed) and step 10, is in the order of about 100
microseconds, or less, on a modern microprocessor.
This means thatthe physical action that was necessary
to close the push-button switch is probably still in
+Vee
progress and 51 remains closed. lfthe program was
Common
anodes
simply to loop back to step 3, the test of step 4 would
PO a be true, count would be incremented again, the new
P1 b
number displayed, and so on. For as long as 51
a remained closed, the displayed number would
P2 increment once every 100 or so microseconds.
~------~=r---:~ ~;:-:,
P3 This is obviously not the required effect and so
step 10 and step 11 are included in order to test for
~------~=r---e~ ~:::,
-
PIO P4
0 the release of S1. The 'false' loop of the program will
P5 be followed by the microprocessor until this occurs.
0
P6 g When the switch is released, the program loops back
to step 3, and the microprocessor will patiently
P7
51 revolve around the step 3/step 4 loop until S1 is
...r:::::J._
o---+Vee pressed again.
When the programmer is satisfied that the flowchart
represents the most efficient way of implementing the
program, the next step is to convert the flowchart steps
Ov into instructions which the microprocessor can
recognise and execute. This activity is called 'coding'
and to demonstrate how this may be achieved, Chapter
Fig. 2. 7 The software solution for segment decoding. 3 will take a closer look at a 'real' microprocessor.
The program provides the correct binary pattern on However, it can be seen at this stage that the flow-
the port lines. chart is a very important piece of documentation, not
only for the programmer but also for anyone else who
will need to understand how the program works. For
example, the flowchart for the program running a
microprocessor-based system is an invaluable aid to
the service technician who must fault-find on the
equipment. By showing the technician the sequence in
which the microprocessor performs its tasks, he is able
to determine where in the sequence the system is
failing. By considering which devices are active during
that time, the general area ofthe fault may be isolated.

19
 CHAPTER 3 Control bus
This bus carries various signal lines whose functions
RES:
This is the master reset input and it is normally held up

THE 6502 are specifically related to the operation and archi-

tecture ofthe particular MPU. However, most of the
control lines found on the 6502 have close parallels in
to logic 1 by an external resistor. It may be activated
(pulled low) by automatic circuitry at power-up or
simply by a physical reset switch (or both). The MPU
MICROPROCESSOR the other popular 8-bit MPUs currently available.
Briefly, the function of each line is as follows:
action that follows reset is explained on page 27.

The 6502 Microprocessor was first manufactured by

MOS Technology in the United States and is the
heart of many currently popular microcomputers and
some sophisticated television games machines.
However, it is also well suited to performing control
functions from complex numerical control of
machinery to simple display applications.
The internal architecture and programming method-
ology are broadly typical of current 8-bit micro-
processors and for this reason it has been chosen to
act as an illustration to the following discussions.
n.c.
NMI
6502 pin assignments Sync
Figure 3.1 shows the pin functions of the 6502. Vee
AO
Address bus A1
Pins 9 to 20 and 22 to 25 inclusive, carry the sixteen A2 6502
Data
address lines. This allows the 6502 to address i 6 or A3 bus
65,536 (64K) separate 8-bit locations in memory. The A4
A5
address lines act only as outputs.
A6
A7
Data bus AS
Pins 26 to 33 form the data port which transfers data A9
between the MPU and external support devices via the A10
data bus. A11 Address
The data bus is a bidirectional bus, the direction of bus
the port being controlled by the MPU. n.c. = not connected

Fig. 3.1 6502 Microprocessor pin assignment diagram

20
IRQ:
This is the Interrupt Request input which is also active
low. After executing each instruction, the MPU checks
the state of the IRQ input. If it is high (non-active), the
normal program sequence continues. lfthe IRQ line is
activated, the MPU temporarily jumps to another part
of its program which will have been written specifically
to deal with (service) the interrupting device. At the
end of the service routine, the main program is taken
up at the point where it was interrupted, (see
figure 3.2).
Certain parts of the main program may have high
priority and, under these conditions, the programmer
may use an instruction which prevents interruption
from the IRQ input. This is referred to as interrupt
masking.
NMI:
This is the Non-Maskable Interrupt input. This input
acts on the MPU in the same manner as IRQ but, as its
name suggests, it cannot be overriden by an interrupt
mask instruction in the main program.
Devices which use this means to call for MPU service
will have high priority in the system.
R/W:
This pin is the Read/Write line as discussed in
Chapter 1. It will be a logic 1 when the MPU is
reading in from external memory and logic 0 when
the MPU is writing out to external memory.
SYNC:
The Sync pin produces a logic 1 during thetimethatan
instruction is being fetched from the program
memory. It will remain at logic 0 when data is being
read or written (and at all other times). It may be used
in conjunction with the ROY pin to allow single
instruction execution of the program. This is a useful
technique to aid program fault-finding.
ROY:
The Ready (ROY) line is used when slow memory
devices are being accessed by the MPU. If, during a
read or write operation, the ROY line is pulled down to
logic 0, the logic level ofthe R/W line and the address
code on the address bus are maintained. This will
extend the cycle time to allow slow memory devices to
respond.
SO:
The Set Overflow (SO) input allows external devices to
'flag' the MPU by setting the overflow bit in the
processor status register (see explanation on page 25).
This has no direct effect upon the MPU, but the
program may test this bit and make the necessary
response.
<1>0, <1>1, <1>2:
IJ>O (in) receives the incoming system clock signal
which is a squarewave whose frequency will be bet-
ween 100kHz and 1MHz (6502), 2M Hz (6502A) or 3MHz
(65028). The MPU woduces from this signal, lf>1 (out)
and <1>2 (out). These are anti-phase, non-overlapping
clock signals which are used inside the MPU and for
synchronising the action of other system components
such as ROM, RAM, etc.
The non-overlapping nature of these clock signals
may be seen from figure 3.3.

<1>0 (IN)
\
...____

<1>1 (OUT)

\~_____,/ \
'----
*2(0UT)

----------------------- -----•End
Interrupt program instructions

Fig. 3.3 Non - overlapping clock signals generated by

Fig. 3.2 MPU interrupt procedure 6502MPU

21
 6502 internal architecture
In Chapter 1, an MPU was built up, stage by stage, to
finally contain an accumulator, data buffer, an ALU,
Address bus a control section and some data routing circuitry. The
6502 MPU has all of these, plus other registers the
functions of which will be considered in the next few
pages.
Figure 3.4 shows a simplified block diagram of the
6502 internal structure. All registers and buffers of the
system are connected via the internal 8-bit bus.

Program Program Address and data register buffers

counter(H) counter (L) The sixteen address lines (AO-A15) are driven from
two 8-bit register buffers. The buffers ensure that each
line has sufficient drive current available to operate the
other devices connected to the bus lines. Address
Index reg.
X information may only be transmitted by the MPU on
this bus.
The data register however is bi-directional, allowing
8-bit data (DO- D7) to enter from the data bus or be
Index reg. placed on it by the MPU. This transmit/receive
y function of the data register is controlled by the MPU
itself, according to the instruction being followed.

Program counter register

As previously explained, the instructions which form
the program are stored in external memory and must
be brought into the MPU in the exact sequence that
they appear in the program.
Stack The program counter always contains the address of
pointer
the next byte to be fetched from the program memory.
When the current instruction has been completed, the
16-bit address contained in the program counter is
transferred to the address output registers, (figure 3.5).
Data 1/0 The program memory will respond by placing the
register contents ofthe addressed location (i.e. the next
instruction), onto the data bus making it available at
the data 1/0 register ofthe MPU.
After the transfer between program counter and
address output registers has been made, the contents
of the program counter are automatically incremented
to the address of the next byte of the program.
This complete operation is called the instruction
Fig. 3.4 6502 MPU internal architecture
fetch cycle.

22
Instruction register
At the end of the instruction fetch cycle, the instructioP
byte is available at the data 1/0 register and therefore to
the internal data bus. The MPU places the instruction
in the instruction register where it is held for the.
duration of the required operation.

Instruction decoder and control

After the fetch cycle, the instruction will be available to
the instruction decoder and control section ofthe
MPU.
It is this circuitry which is responsible for carrying
out the operation or operations specified by the
instruction bit pattern. Data routing and ALU
commands are affected via internal control lines from
the instruction decoder to all other sections of the
MPU.

The accumulator
The accumulator is a general purpose 8-bit register
used for temporary storage of data. As we saw in
Chapter 1 when called upon to add two 8-bit Addressed
numbers, the MPU will expect to find one of those location
numbers in the accumulator. The result of the
addition (or other logic operation) will also be Program memory
placed in the accumulator by the MPU overwriting ROM
the original contents.

Fig. 3.5 The instruction fetch cycle

1. The program counter contents are transferred to

the address registers and therefore to the address
bus.

2. The address decoder in the program ROM

responds and selects the addressed location.

3. The contents of the location appear on the data bus

and the MPU places them in the instruction
register for decoding.

23
The arithmetic logic unit (ALU) or cleared by the execution of an instruction and the a result of a subtraction or a shift operation carried out
Under the control of the instruction decoder, the ALU following list gives details of each bit function. on the data. The presence or absence of a logic 1 in the
performs all the logical and arithmetic functions that carry flag may or may not be significant to the
may be required by the program. Also, any internal The Carry (C) flag program. Therefore, the condition of this flag alone
register operations that require these functions must Suppose the two numbers that were added were as has no direct effect upon the MPU. It is up to the
be carried out by the ALU. For example, after each follows: programmer to decide the importance of the carry flag
instruction fetch cycle, the contents ofthe program + 11000110 = + 198 and to ensure the program takes appropriate action.
counter must be incremented to point to the next + 10110101 + 181
address in the program. This is performed in two
steps, the ALU carrying out the operation on each byte
1 01111011 123 ?
Address bus
of the program counter contents separately. From this example it can be seen that the result has
When called upon to add the contents ofthe accum- extended beyond the 8-bit capacity of the ALU. If the
ulator to a number held in external memory, the extra '1' was just ignored, the sum of 198 and 181
control section loads the address of the memory would result in 123 instead ofthe correct 379; the error
location onto the address bus. The contents of that being 256. That is, the value of a logic 1 in the ninth bit
location appear on the data bus and therefore at the position if it was available.
data 1/0 register. The control places that data into the Although the ALU handles only 8-bit data, it has the
temporary storage register inside the ALU (the data ability to store this extra carry bit in a one bit indicator Program Program
buffer of Part 1). Via the internal control lines, the called the carry flag. As can be seen in figure 3.6, this is counter (H) counter (L)
control section then commands the ALU to add the bit 0 in the 'P' register. External
number in the accumulator to the number in the data control lines

eo,~~rnl {----.j
buffer and place the result back into the accumulator. Double precision arithmetic
Index reg.
Numbers greater than 255 10 cannot be accom- X
The processor status register modated in an 8-bit binary word. Therefore, when the
The processor status register 'P' is an 8-bit register, the program calls for the addition of two numbers above
contents of which may be altered as a result of an this value, it must perform the addition in 8-bit bytes.
operation carried out by the ALU. Figure 3.6 shows a Figure 3.7 shows the addition of two 16-bit numbers. Index reg.
y
typical arrangement although the details of bit alloc-
High order word Low order word
ation may vary in different microprocessors. The bits
inside the status register may be referred to as 11001110 10011000
condition codes or flags. Each individual bit may be set +00101010 10110110
B~ B~ + 1~.
7 0 11111001 ·~01001110

[N[v[, [slol 1lzlcl Carry flag set

Stack
pointer
N1t Fig. 3. 7 Double precision addition
used Carry
The corresponding low order words of each number
Zero
are added in the ALU and the carry flag is set as a
Interrupt mask result. The program stores the result back in memory Data 1/0
and tests the carry flag status and notes that it is set. register
Decimal mode The corresponding high order words are then brought
in and added and the result is incremented by 1 to
Break command
include the carry from the previous operation.
Overflow If a carry had been generated from the high order
word addition, then a third order word would be
Negative necessary to accommodate the result (i.e. triple Fig. 3.4 6502 MPU internal architecture
Fig. 3.6 Processor status register 'P' precision arithmetic). The carry flag may also be set as

24
The Zero (Z) flag
Bit 1 ofthe 'P' register is the zero flag. If an operation is
carried out by the ALU and the result is 'all zeros',
then the Z flag is set.
The Interrupt mask (I) flag
Most microprocessors have at least one input pin
reserved for interrupt requests from external circuitry.
When this input is activated, it will cause the micro-
processor to temporarily abandon the current
instruction sequence and jump to another area ofthe
system program. This will contain instructions for the
MPU on how to service the interrupting device. Having
completed this routine, the MPU returns to the main
program at the point where it left off.
If, at some point in the program, it is imperative that
the main processing should not be interrupted, the
programmer may set the interrupt mask flag. When
the MPU receives an interrupt request, it will check the
I flag. If it is set, it will note that the request has been
made, but will not interrupt the main program.
If the instruction to clear the I flag is found in the
main program at some later time, the MPU will clear
the I flag and then service the interrupting device. Bit 2
of the 'P' register is the I flag.
The Decimal mode (D) flag
When performing Binary Coded Decimal (BCD) arith-
metic the 8-bit byte can be interpreted as two groups of
four bits, each group representing one decimal digit.
e.g.
B7 B6 B5 B4 B3 B2 B1 BO
0 0 1 1 0 1 1 0 Data byte
\ v /'---v---/
BCD= 3 10 BCD= 6 10 = 3610
It must be stressed that BCD grouping in this way is an
interpretation placed upon the data by the
programmer. There is no way that the MPU can auto-
matically recognise this fact and, therefore, when
performing addition or subtraction on BCD data, the
programmer must 'inform' the MPU that this is the
case.
The 6502 MPU simplifies BCD arithmetic by the
facility of a decimal mode flag in the 'P' register (bit 3).
The decimal mode may be called by the program by Note:
the 'set decimal mode' instruction. After execution of Negative numbers are represented in 2s complement
this instruction all arithmetic operations carried out by form, (see appendix page 45).
the ALU will assume BCD data until the 'clear decimal Consider the following addition of two signed binary
mode' instruction is encountered in the program. numbers with values+ 100 10 and+ 74 10 . Obviously,
While in the decimal mode, bit 3 of the 'P' register the result should be 174 10 , but in our signed binary
will be set to logic 1. addition a '1' has been carried over from bit 6 to bit 7.
As bit-7 is reserved for the sign, the number will be
The Break command (B) flag interpreted as minus 82, (2's complement). This
When the MPU encounters the 'BRK' instruction [OO(hU condition is called overflow.
it behaves as if an interrupt had occurred at the IRQ
or NMI inputs. Because it has been called by the 01100100 + 100
program, however, it is referred to as a software 01001010 + 74
interrupt. As the interrupt procedure followed by the 10101110 -82 + 174
MPU is the same for either a hardware or software lt.J
interrupt, the 'BRK' flag (bit 4 of the 'P' register) is B6--B7 carry
set only in the latter case. This allows the interrupt
Again, the microprocessor will consider this condition
service routine to determine the type of interrupt it is
to be perfectly legal so it is the programmer who must
handling and perform different operations for each.
take the necessary steps to avoid an erroneous result.
The 'P' register- Bit 5
This bit of the 'P' register is unused.
The oVerflow (V) flag
When considering the operation of the carry flag, 8-bit
binary numbers were used in the example. Each byte
could represent decimal values from 0-255. Under
these conditions the sign of the number is unspecified.
When handling positive and negative numbers, one of
the 8 bits must be reserved to indicate the sign and by
convention, bit 7 performs this function.
87 86 85
.
84 83 82 81 80
I I
'
Sign bit 7-bit number
Again, by convention, a logic '0' in bit 7 indicates a
positive number while a logic 1 means the number is
negative.
The range of our 8-bit signed binary number is now:
-128-0-+127whic h, in binary, appears as:
10000000--000000 00--01111111
negative positive
25
 For full overflow error detection when performing The stack pointer
signed binary arithmetic, the condition of the carry flag In Chapter 1, a minimum configuration system was
Address bus
must also be considered (see appendix on binary described. It showed that even in a basic system, the
arithmetic page 82). The following truth table shows program will require some RAM to store interim
the logic of overflow error detection. results. Also, ifthe MPU is interrupted during program
execution, it will need some RAM space to store the
Carry Carry Overflow values held in its internal registers. After the interrupt
from B7 from 86 flag has been serviced, the MPU will call back those values
0 0 0 so that it can continue the main program from the
Program 1 0 1 point of interruption.
counter (L)
0 1 1 This RAM is usually called stack RAM and the stack
1 1 0 pointer will hold the low byte ofthe next unused RAM
location in the address field 010D-01FF(h) (i.e. page
From the truth table it can be seen that the result of a one). The high byte (01) is generated automatically by
Index reg .
X signed binary operation is erroneous when only one the 6502. Each time the MPU stores an 8-bit value onto
carry from either bit 6 or bit 7 is generated. If neither or the stack, the stack pointer register contents are decre-
both are generated, the result is true. This is the mented so that they 'point' to the next available RAM
Exclusive OR condition and is the function which, location. Similarly, each time the MPU pulls a value off
Index reg. the stack, the stack pointer is incremented to reflect the
y when satisfied, will set the V flag.
i.e. carry 87 (f) carry 86 = V flag fact that one extra location has become free.
Bit 6 ofthe 'P' register is the overflow (V) flag and will
be set by the ALU whenever the result of a signed
binary arithmetic operation is in error. Now the
program can test for the condition and take
appropriate remedial action, where necessary.
Stack
pointer The Negative (N) flag
Whenever an ALU operation produces a logic 1 in bit7
of the resulting data the N flag is set. As previously
mentioned, when using signed binary numbers, a '1' in
Data 1/0
bit 7 indicates that the number is negative. TheN flag
register can be used by the program to detect the negative
condition.

Index registers X and Y

These two registers may be used as general purpose
a~bit registers. Their contents may be loaded from, or
stored to, memory. They may both be incremented or
Fig. 3.4 6502 MPU internal architecture decremented and they will set orclearthe Nand Zflags
as a result of operations performed upon their
contents.
By the use of these registers in general purpose
counting routines, the need to use individual memory
locations is reduced and this leads to more efficient
programs.
Their most useful function however, is utilised in the
'indexed addressing modes' which are explained in
detail in Chapter 4.
26
The reset sequence
Now that the various registers within the 6502 have Program memory
Event Address Program
been explained, the full sequence of events that take bus counter Address Contents
place after reset may be discussed. As a reminder, the r - - 1-

I
purpose of the reset function is to 'point' the MPU to Switch on X X X X X X X X
the first program instruction in the system program. FFFD EO
Figure 3.8 shows the sequence of events that takes FFFC 00
place after'reset'.ln this case, the MPU expects to find
the program start address in locations FFFC(h) and
Reset cycle 1 F F F C X X 0 0
'-.r::::::::._
I
I j I
I
I I
FFFD(h). In the first fetch cycle following reset, the I I
microprocessor applies the address FFFC(h) to the I I
address bus. The program memory responds by Reset cycle 2 F F F D 0 0 0 I I
I
applying the contents of that location to the data bus,

~o~o e~o _rEooo~

(in this case OO(h)). The MPU stores this byte of data in
the low order register of the program counter.
1st instruction
In the second cycle after reset, FFFD(h) is applied to
the address bus and the contents ofthis location are
fetch cycle
stored into the high order byte ofthe program counter
(e.g. EO(h)).
The full address in the program counter now points
to the first location at the start of the program. There-
fore the next fetch cycle will automatically pick up the
first instruction.
As the system designer/programmer may place any
address these two next locations, the system program
may begin at a·ny point in the 64K address range ofthe
6502.
E o ______ __o__,__________
1st program
X = Don't know instruction
Fig. 3.8 6502 Reset sequence
CYCLE 1. The MPU puts out the address FFFC(h) and
the program memory responds by placing the
contents of this location onto the data bus. The MPU
places the number in the low byte of the program
counter.
CYCLE 2. The MPU repeats the procedure for the
address FFFD(h) and the contents of this location are
placed in the high byte of the program counter.
Instruction fetch cycle. The full start address that is
now in the program counter is transferred to the
address bus and the first instruction is fetched (in the
example, the contents of address EOOO(h).

27
 CHAPTER 4 The instruction set
In Chapter 3, the instruction fetch cycle was discussed
in which the instructions in the program memory wer~
The instruction format
All instructions may be classified into two main types.

PROGRAMMING THE
These are:
directed in sequence to the instruction register inside
Non-memory-referenced instructions
the MPU. These 8-bit binary words, which present a
MICROPROCESSOR certain bit pattern to the instruction decoder, are
referred to as machine (or object) code. This means
Memory-referenced instructions.
The firsttype of instruction does not require the micro-
The 'soft' model that the instruction decoder may be presented with processor to access any external memory location. For
Having gained an appreciation ofthe internal 256 different machine code words and each may cause example, in figure 4.2, the instruction 'Clear the Carry
hardware architecture ofthe MPU, much of it may be the decoder to perform a different function within the Flag' (CLC) involves only the internal 'P' register and
omitted in further discussions. For the purpose of MPU. therefore is non-memory referenced.
programming the microprocessor, the model offigure With the exception of some manufacturers 'in- An example ofthe second type of instruction from
4.1 gives sufficient detail of the device. house' derivatives, each microprocessor type has its figure 4.2 is LOA. This tells the microprocesor to load
Figure 4.1 is the 'soft' or programming model of the own way of responding to the machine code presented the accumulator with the contents of a memory
MPU and shows all the registers that may be directly to the instruction decoder. Or, in other words, each has location. Simply including the code forth is instruction,
affected by programmed instructions. Although the an instruction set which is unique to itself. however, does not convey sufficient information to the
contents of other registers, such as the instruction Figure 4.2 shows part of the instruction set for the MPU. It will need to know the address of the relevant
register and the ALU will be continuously changing 6502 MPU but it is representative of all commonly memory location in order to comply. The general
during the execution of a program, they are only of available microprocessors. format for memory-referenced instruction is as
marginal interest to the programmer. The mnemonic is literally an 'aid to memory'.lt is an follows:
abbreviation, usually no more than three or four letters Op code Address of operand
long, which describes the function of the instruction.
For example, mnemonic INX, in the instruction set of Opcode is short for 'operating code' and is the 8-bit
figure 4.2, is a shortened version ofthe function 'add 1 number associated with the instruction mnemonic (i.e.
7 0 to the contents of register X'.lfthe requirement was to the 'object code' of figure 4.2).
I A
I Accumulator increment the register Y or the contents of a memory
location, the mnemonics INY or INC would be used
The operand is 'the aata that is to be operated upon'.
E.g. The instruction 'load the accumulator from the
7 0 memory location whose hexadecimal address is 0944'
respectively. The third column offigure 4.2 gives some
I X I Index register X
of the object code numbers or the actual value that would be coded as follows:
7 0 must be stored in the program memory to ensure that Op code Address of operand
the MPU carries out the required operation. Rather
I y
I Index register Y
than listing the binary values, it is customary to AD 44 09
15 7 0 present object code in hexadecimal form. 1st Byte 2nd Byte 3rd Byte
I PCH I PCL I Program counter Hexadecimal notation was explained in Chapter 1
but, briefly, it performs a similar function to the When dealing with a full 16-bit address, the 6502
7 0 mnemonics. That is, it is used only as an aid to the microprocessor expects to receive the low byte before
1~1 s I Stack pointer programmer. The MPU has no use for either the
mnemonics or hexadecimal notation as it can only
the high byte. This is unfortunate because when
coding 6502 programs, the addresses always appear
7 0
interpret pure binary. The programmer, however, is 'backwards' as shown in the example above.
INivl Is IoII Izlei Processor status
register 'P' human and has great difficulty handling long streams
of binary 1'sand O's accurately. The mnemonics can be
said to aid the programmer's memory while hexa-
decimal notation aids his numeracy.
Fig. 4.1 6502 Programming model

28
Addressing modes Mnemonic Function Object code (Hex)
The method used to address the instruction LOA ADC ACC4-- ACC +M +C 60
shown above, is only one of many different ways of
AND ACC...,_ ACC AND M 20
giving the MPU the relevant address. In the example,
ASL c .--\7 (ACC) 0\4---0 OA
the full16-bit address is given as part ofthe instruction.
This is called absolute addressing butthere are always BCC BRANCH IF CARRY CLEAR (C = 0) 90
other addressing modes available irrespective of the BCS BRANCH IF CARRY SET (C = 1) BO
MPU type. BEO BRANCH IF ZERO (Z = 1) FO
The six major addressing modes that are supported BMI BRANCH IF MINUS (N = 1) 30
by most commonly available MPUs are: BNE BRANCH IF NON-ZERO (Z = 0) DO
1. Implied BPL BRANCH IF PLUS (N = 0) 10
2. Immediate BRK SOFTWARE INTERRUPT (BREAK) 00
3. Absolute BVC BRANCH IF OVERFLOW CLEAR (V = 0) 50
4. Zero page BVS BRANCH IF OVERFLOW SET (V = 1) 70
5. Relative CLC CLEAR CARRY (C~ 0) 18
6. Indexed CLD CLEAR DECIMAL MODE (D..,._ 0) DB
CLI CLEAR INTERRUPT MASK BIT (I 4--- 0) 58
CLV CLEAR OVERFLOW FLAG (V.-- 0) BB
DEC M..--M-1 CE
DEX DECREMENT CONTENTS INDEX X CA
DEY DECREMENT CONTENTS INDEX Y 88
EOR Acc-Acc0 M 40
INC M.--M+1 EE
INX INCREMENT CONTENTS INDEX X EB
INY INCREMENT CONTENTS INDEX Y C8
JMP JUMP TO NEW LOCATION 4C
JSR JUMP TO SUB-ROUTINE 20
LOA LOAD ACCUMULATOR FROM MEMORY AD
LOX LOAD INDEX X FROM MEMORY AE
LOY LOAD INDEX Y FROM MEMORY AC
ORA ACC 4 - ACC OR M OD
RTS RETURN FROM SUB-ROUTINE 60
SBC ACC . _ ACC-M-C ED
SEC SET CARRY (C -----1) 38
SED SET DECIMAL MODE (D....__ 1) Fa
SEI SET INTERRUPT MASK (J..-1) 78
STA STORE ACCUMULATOR TO MEMORY 80
STX STORE INDEX X TO MEMORY BE
STY STORE INDEX Y TO MEMORY ac
TAX TRANSFER ACC TO INDEX X AA
TAY TRANSFER ACC TO INDEX Y A8
TXA TRANSFER INDEX X TO ACC 8A
Fig. 4.2 6502 Instruction set (part) TVA TRANSFER INDEX Y TO ACC 98

29
 MNEMONIC IMMEDIATE ABSOLUTE ZERO PAGE IMPUED ZERO PAGE INDEXED ABSOLUTE INDEXED RELATIVE Care must be taken when reading the following
X v X v address mode descriptions. Different manufacturers
ADC 69 60 65 75 70 79 use the above terms and others to describe slightly dif-
AND 29 20 25 35 30 39 ferent addressing functions. Therefore, these should
ASL OE 06 OA 16 1E
BCC 90 be looked upon as a guide only and for micro-
BCS BO processors other than the 6502, the manufacturers
BEO FO
data should be studied carefully.
BIT 2C 24 If an instruction may be addressed in more than one
BMI 30
BNE DO mode, it must have a different number for each. Figure
BPL 10 4.3 shows the op codes for the instruction set of the
BRK 00
BVC 50 6502 for those addressing modes that are listed on
page 29.
BVS 70
CLC 18
CLD 08 Implied addressing
CLI 58 Implied addressing uses only one byte for the instruc-
CLV BS
CMP C9 CD C5 05 DO 09 tion. The address of the operand (the data) is implied
CPX EO EC E4 by the instruction itself.
CPY co cc C4 For example, the instruction INX implies that the
DEC CE C6 06 DE data must have one added to it and that it may be
DEX CA
DEY 88 found in the index register X. No further information is
EOR 49 40 45 55 50 59 required for the MPU to execute the instruction, i.e:
INC EE E6 F6 FE
INX E8 Instruction Mnemonic Code
INY C8
JMP 4C Increment register X INX
JSR 20 E8
LOA A9 AD AS B5 BD B9
Immediate addressing
LOX A2 AE A6 B6 BE
LOY AO AC A4 B4 BC If the MPU fetches an instruction and the code indi-
LSR 4E 46 4A 56 5E cates that the immediate addressing mode is being
NOP EA
ORA 09 00 05 15 10 19 used, it will expect to find the data in the memory
PHA 48 location immediately following that which held the
PHP 08 instruction op code. That is, in this addressing mode,
PLA 68 the data forms part of the program.
PLP 28 For example, figure 4.4 shows the execution of the
ROL 2E 26 2A 36 3E
ROR 6E 66 6A 76 7E immediate mode version of LOA (op code A9(h)). The
RTI 40 accumulator is loaded with the data in the memory
RTS 60 location following the op code (in this case FF(h)), i.e.
SBC E9 ED E5 F5 FD F9
SEC 38 Instruction Mnemonic
SED F8 Code
SEI 78
STA 80 85 95 90 99 Load Ace. immediate LQAFF A9FF
with FF(h)
STX BE 86 96
STY 8C 84 94
TAX AA Immediate addressing is only used when the va.lues
TAY AS that are being manipulated remain the same under all
TSX BA
TXA 8A program conditions. They are stored in the program
Fig.4.3 ROM along with the op codes and are therefore
TXS 9A
TVA 98 unalterable.
6502 Instruction codes

30
 Program Program
memory Accumulator memory Accumulator Memory location AOOO

Load Ace. immediate

with this data
A9 IX IX IX IX IX IX IX IX I F~t~~tion Store Ace. Absolute 80 x_._lx. . .l'-x. . .l_x_..l_x....~..l_x..~..l_x x_,l ~~~~~~tion
._I .J....I

FF in address{ t---o_o---l LB
l1 l1 l1 l1 l1 l1 l1 l1 I After AO
1------j
HB

~
F F

X = Don't know
Fig. 4.4 Immediate addressing
Fig. 4.5 Absolute addressing
Absolute addressing
Instructions that use the absolute addressing mode
are three bytes long and are made up ofthe op code
followed by a two byte address, i.e:
Instruction Mnemonic Code Program
memory Accumulator
Store accumulator contents STAAOOO 8000AO
to memory location AOOO Store Ace. Zero page t---8_5---l
in Zero page address 75
1------j
As soon as the MPU fetches the op code '80', it will
Location
note that the absolute addressing mode is being used 0075
and expect that the first and second bytes following
the op code will be the low byte and the high byte
respectively of the full sixteen bit address.
Figure 4.5 shows the effects ofthe STA (absolute)
instruction.

Zero page addressing Fig. 4.6 Zero page addressing

In Chapter 1, the concept of splitting the 64K address
range into 256 pages each of 256 bytes was discussed.
The bytes that reside in page zero are those with
addresses OOOO(h) and OOFF(h).
Zero page addressing is the same as absolute addre-
ssing in that the address is part ofthe instruction and
follows the op code. However, in this mode, the high
byte of the address is assumed to be OO(h) so only the
low byte of the address needs to be specified in the
instruction.
The following instruction uses zero page
addressing:
Instruction Mnemonic Code
Only two bytes are required for an instructior. using
zero page addressing. It is used to best advantage
when a small area of RAM memory is set aside for data
storage that is regularly accessed by the program. If
page zero is chosen for the storage area, then the use
of zero page addresing may considerably improve the
program efficiency, (i.e. it will use less code and
execute faster).
Figure 4.6 shows the effect of the above instruction
example.
Relative addressing
All instructions that use relative addressing are two
byte instructions. A more correct name forth is mode is
program counter relative addressing as the instruction
consists of the op code followed by an offset value that
is added to the program counter contents. Relative
addressing is only used with the conditional branching
instructions, i.e:
Instruction Mnemonic Code

Store accumulator contents STA0075 8575 Branch if minus BMI offset 30XX
in location 0075 (i.e. N flag= 1)

31
 Program Program Zero page indexed addressing
memory Program counter memory This addressing mode behaves exactly like the abso-
Branch IF minus E020 30 IE I0 I2 I0 I ~ne:t~~~tion STA indexed (X) 90 [£]£] Accumulator
lute indexed mode exceptthat, like standard zero page
addressing, the address of the operand is assumed to
Offset E021 62 6-0
Base address 1--- ---1} ~ Index register X be in page zero. Therefore, only the low byte address

Next instr. op code E022
I'--
I I
I I
I I Branch
I I
I
I
I
I ~:s
E084 ~
Fig. 4.7 Relative addressing
Figure 4.7 shows the effect of this i~struction.
The instruction BMI is held in locat1on E020(h) so th1s
will be the address in the PC (program counter) when
the op code is fetched (30).
The program counter is incremented to the second
byte ofthe instruction and the offset (62) is fetched, the
PC again being incremented to point to the next
instruction opcode. The PC now contains E022(h). Two
possible actions may now occur.
1. If the N flag was set at the time that the MPU was
interpreting the BMI op code, the offset 62(h) would
now be added to the PC making it E084(h) as shown in
figure 4.7. The next instruction op code will be fetched
from this address.
2. If the N flag had been zero, the offset would not
have been added to the PC leaving it pointing to
E022(h), i.e. the next instruction op code.
As the offset is interpreted as a signed binary
number, relative addressing may be used to branch
forward or backward from the current program
address. The branching range is, therefore, + 127 to
-128 bytes from the prevailing program counter
value.
Absolute indexed addressing
Instructions that use the absolute indexed addressing
mode are three bytes long. The op code is followed by
~
need be included in the instruction.
For example:
AO Effect;ve •dd"" ;, )
Base =A 0 6 0
+Index = 2 E Instruction Mnemonic Code
A08E Load the accumulator from LDAC5,X 85C5
Data Zero Page address C5 plus
memory the contents ofthe X register
Other 6502 addressing modes
The 6502 supports a large range of addressing modes
most of which have already been discussed. The
I remaining modes, although important for serious pro-
gramming, are outside the scope ofthis introductory
book.
AOBE~ Those who wish to go further into the subject are
referred to the MOS Technology MCS6500
. programming manual.
Fig. 4.8 Absolute indexed addressing
a two byte address just as it was with the standard Simple programming techniques
absolute mode, but the effective address ofthe THE COUNT LOOP
operand is obtained by the MPU by adding this At some time during a program, it will be necessary to
address to the contents of one of the index registers X repeat a given sequence of instructions a number of
or Y. For example, the effect of the following times. To achieve maximum programming efficiency,
instruction is illustrated in figure 4.8. the sequence is written just once and the MPU is
directed to branch back over that sequence. This is
Instruction Mnemonic Code called a program loop.
Merely getting the MPU to follow a loop is not
Store accumulator contents STAA060.X 9060AO
at base address A060 plus enough however, as once in, the MPU will continue
the contents of register X
looping forever unless a counting routine is included
to cause the MPU to branch out after the required
The base address is given in the instruction, in the
number of loops.
example of figure 4.8, this is A060(h). To find the effec-
tive address, the MPU fetches the base address and adds
the contents ofthe index register X [2E(h)]. This gives an
effective address of A08E(h) and the accumulator
contents are stored here to comply with the op code.
This form of addressing is a very powerful aid when
the program needs to deal with tables of data (which is
a common requirement). The base address must
remain the same at all times as it forms part of the
program but if the index register contents are incre-
mented or decremented, the effective address will
move up or down the data table.

32
 Figure 4.9a shows the flowchart for a program loop
that does not contain a count routine. The code, shown
in figure 4.9b, is located in memory from location
EOOO(h), although this could be any address within the Program Program Mnemonic MPUaction
range of the microprocessor. address code
The first instruction at EOOO(h) loads the accum- EOOO A9 LOA Load accumulator immediate
ulator 01 (h) and then its contents are stored in the
output register of a PIO device which responds to E001 01 with 01 (h)
address A001 (h). At the end of the STA instruction, bit Loop
E002 80 STA .. Store accumulator contents ~ begins
0 of the PIO output port will be +5 volts and the bits here
1-7 will be at zero volts (figure 4.10). E003 01 in the PIO at address
The next instruction is ASL which results in the E004 AO A001 (h)
contents ofthe accumulator being shifted one position
EOOS OA ASL Shift accumulator contents left
left (i.e. towards bit 7). The accumulator contents
become 02(h). The next command is the JMP instruc- E006 4C JMP- Jump back
tion which causes the program to loop back to address
E007 02 llToE002
E002. The new value in the accumulator is then stored
in the PIO with the result that bit 1 of the port switches
to 5 volts and bit 0 and bits 2-7 are at zero volts.
EOOS EO If
The next instruction shifts the accumulator contents
left again (i.e. accumulator becomes 04(h)) and then Fig.4.9b
the loop is repeated. Because the program includes no
means of branching out of the loop, it will continue
looping until the power is switched off or until an inter-
ruption from an external device forces the MPU to
follow another part of the program.
The total effect of the program offigure 4.9b would be
that each bit of the output port will rise and fall in ,....----, BitO ,---svolts
sequence ending at bit 7. When the voltage at bit 7
falls, no further change will occur and all port lines will
remain at zero volts.
Let us suppose that after all bits have been strobed, PIO
Ovolts
that is, after eight loops, we want the MPU to follow the
next part ofthe program. To do this, a count routine Data
must be inserted. bus

Fig. 4.10 P/0 condition after one loop

Fig. 4.9a The program loop

33
 Figures 4.11 (a and b) show the same program as
before but with a count routine. As before, the
accumulator is loaded with 01 (h). Now index register X
is loaded with OS( h) to act as the loop counter. The
contents ofthe accumulator are stored in the PIO and
then shifted one bit left as before. The new command
DEX is now inserted which decrements the contents of
register X by one after each loop.
The DEX command is followed by the conditional
branch command BNE. This tests the Z flag in the pro-
cessor status register 'P' which will have been set or
reset as a result of the preceding DEX instruction.lfthe
index register is not zero, the condition ofthe branch is
satisfied and the MPU will now add the branch offsetto
the program counter. As mentioned earlier, the offset
is a signed binary number and therefore F9(h) will
cause the program counter (now at EOOB) to be
adjusted down to E004; that is, the beginning of the
loop.
After eight loops, the last DEX command causes the
index register to reach zero which will set the Z flag.
Now, when the MPU executes the BNE instruction it
will test the Z flag and, on finding it set, ignore the Fig. 4.11a The count loop
branch command and increment the program counter
to EOOB(h) from where it will continue the next part of
the program.
Program Program Mnemonic MPUaction
address code
EOOO A9 LOA Load accumulator immediate
E001 01 with 01 (h)

E002 A2 LOX Load register X immediate

E003 08 with08(h)
Loop
E004 80 STA• Store accumulator contents ~ begins
here
E005 01 11 in PIO address A001
E006 AO IJ
E007 OA ASL Shift accumulator contents left
E008 CA DEX Decrement register X
E009 DO BNE- Branch IF not equal to 0
EOOA F9 Offset F9 (h)
EOOB Next routine of program

Fig. 4.11 b Looping program with counter

34
DELAY LOOPS This kind of nesting may be extended as far as is
It is often necessary to slow the action of a micro- required for a given delay. It is limited only by the
processor down especially when dealing with the amount of memory that is available to hold the count
analogue world of man and mechanical devices. As values.
the MPU cannot easily be stopped, it must be occupied
in some other routine in order to delay its next action.
A delay loop is a count loop of calculated duration.
Figure 4.12a shows the flowchart for a simple delay
loop routine. The delay produced by this routine is
equal to:
(Processing time of step a + step b) x count
For the 6502 working from a clock frequency of
1MHz, this figure would be typically 5 microseconds
multiplied by the value of count. If the count was
limited to one byte, the longest delay possible would
be:
255 x 5l.IS = approx. 1.3 milliseconds
For longer delays, the value of count must occupy Fig. 4.12a Delay loop
more than one byte or alternatively the deiay program
of figure 4.12a may be repeatedly executed in order to
produce the required delay figure. Rather than write
the code out over and over again, it would be sensible
to place the delay routine itself in another loop. Figure
4.12b shows a nested delay loop using two count
figures to generate the delay. The program operates as
follows:
1. The two counters are set to the required value.
2. Count 2 is decremented and tested. The processor
will remain in this loop until the count is zero.
3. Count 1 is decremented and tested for zero and, if it
is not, the program loops back and resets count 2.
4. The inner count 21oop is repeated again and so on
until both count 1 and count 2 are zero when the
combined delay ends.
The delay inherent in this kind of 'nested delay loop' is
found by the following formula:
Total delay=
Count 1 x count 2 x processing time in one count 2
loop.
The inner, count 2 loop is the same as the simple loop
offigure4.12a.lfwe assume a 1MHzclock signal again,
then this time represents about 5uS If both counts
were set to maximum (i.e. 255), the delay would be as
follows:
255 x 255 x 5l.IS = 0.33 seconds. Fig. 4.12b Nested delay loop

35
SUBROUTINES 2. The program counter contents are stored in the The subroutine that resides between 0210 and 0240
Often, it is necessary to perform the same program- stack RAM so that the return address may be may be called any numberoftimesfrom any partofthe
ming task or set oftasks in different parts of a program. recalled to the program counter after the sub- main program. Similarly, subroutines themselves may
Rather than code the section twice, it would be more routine has been executed. call other subroutines as illustrated graphically in
efficient to create a subroutine which may be called 3. The address ofthe first instruction in the sub- figure 4.14. This is called nesting subroutines and each
from the main program any number oftimes. routine is loaded into the program counter time a subroutine is called, the return address is stored
Figure 4.13 shows how a subroutine may be called. (0210(h) in figure 4.13). on the stack. As the stack is a 'last in- first out'
The 6502 instruction JSR or 'jump to subroutine' (hex 4. The subroutine is executed until the RTS or 'return memory arrangement, the exit from the nested sub-
code 20) is used. The following sequence of events from subroutine' instruction is encountered routines is an exactly opposite route to the entry path.
occurs when the JSR instruction is encountered: (60(h)). For example:
1. As usual, the MPU automatically increments the 5. The return address on the stack is loaded into the
program counter to point to the next instruction program counter and the main program is res- Entry Path
op code (i.e. 0013(h)) while interpreting the JSR umed atthe next instruction aftertheJSR.In figure Main program JSR
instruction. 4.13 this is 0013(h).
Subroutine levei1¥"'JSR
Subroutine level 211"'JSR
Subroutine level 311"'
Main
Stack
Program Exit path
0010 20 Ju mp to subroutine Subroutine level3 RTS
0011
0012
10
02 } at address 0210

Return
SP
SP-1
Subroutine level 2M"RTS
Subroutine level 1M"RTS
0013 XX
address Main program /
/
I I
Main program / JSR
I I
I I
I I
I I

0210~·
I I
I I ;.- Subroutine
I I
I I

~ 60 Ret urn from subroutine

Fig. 4.13 Jump to subroutine example Fig. 4.14 Nested subroutines

36
Coding the program LABEL-
The program that was developed in Chapter 2 may An arbitrary name chosen by the programmer to
now be coded for the 6502 microprocessor. Figure identify an instruction for later reference.
4.15 shows the interface circuit and figure 4.16 MNEMONIC-
shows the flowchart for the programmed solution. The mnemonic representing the opcode part of the
The requirement was that, at switch-on, the number 1 instruction
is displayed on the seven segment display, artl each OPERAND-
time switch 51 is pressed the displayed number is The data (or the address of the data) to be operated
incremented until 8 is displayed. When 51 is pressed upon.
again, the display returns to 1. COMMENT-
Each step of the flowchart will be considered and the To document the program'.
code produced to satisfy the program requirement for
that step. The code will be written in 'assembler' form.
This simply means that the documentation format will
be as follows:

ADDRESS OBJECT CODE LABEL MNEMC. OPERAND COMMENT

ADDRESS-
This is the location in memory in which the opcode of
the instruction is stored.
OBJECT CODE-
The one, two or three bytes that form the complete
instruction.

+Vee
Common
anodes
PO
P1
a
b
®
a
P2 c =
P3 d ~f 9 bu ®
PIO =
P4 e ffe d cff
P5 =
@)
P6 9
P7
51
..c::L No
o--+Vee

Ov
Fig. 4.16 Flowchart for channel number advance
Fig. 4.15 Interface circuit between microprocessor program
system and 7-segment LED display

37
 ADDRESS OBJECT CODE LABEL MNEMC. OPERAND COMMENT INITIALISE PIO
ADDRESS OBJECT CODE LABEL MNEMC OPERAND COMMENT
EOOO A9 7F LOA 7F LOAD ACC. WITH 7F (h) EOOO A9 7F LDA 7F LOAD ACC. WITH 7F I h)
E002 80 21 08 STA DDR PIO P7 =INPUT AND E002 BD 21 08 STA DDR PIO P7 = INPUT AND
PO-P6 =OUTPUTS
Po-P6 = OUTPUTS
E005 A2 01 BEGIN LOX 01 X= COUNT= 1 Explanation: In order to set port lines PO to P6 as
E007 20 21 EO JSR DISPLAY JUMP TO 'DISPLAY' outputs and P7 as an input, the binary pattern
EOOA AD 20 08 SWTEST1 LOA PIO LOAD ACC. FROM PIO TO 0 1 1 1 1 1 1 1 (7F(h)) must be stored into the data
TESTS1 direction register of the PIO. As this cannot be done
EOOD 10 FB BPL SWTEST1 LOOP BACK IF SWITCH directly, the number is loaded into the accumulator by
STILL OPEN the first instruction, i.e. A9 is the immediate mode
EOOF E8 INX COUNT= COUNT+ 1 version ofthe instruction 'load the accumulator' so the
E010 EO 09 CPX 09 COMPARE COUNT WITH 9 MPU expects the next byte ofthe program to contain
E012 DO 02 BNE NEWNUM IF NOT 9 BRANCH OVER the operand. EOOO contains the op code so 7F is found
NEXT INSTRUCTION in the next byte E001.
E014 A2 01 LOX 01 RESETCOUNTTO 1 The next instruction is found in the very next byte of
E016 20 21 EO NEWNUM JSR DISPLAY SUBROUTINE TO DISPLAY memory at E002. The accumulator contents are stored
NEW COUNT in the data direction register by the instruction STA
E019 AD 20 08 SWTEST2 LOA PIO TESTS1 followed by the address of the DDR. Remember that
E01C 30 FB BMI SWTEST2 IF S 1 STILL CLOSED the 6502 expects the low byte of the address first and
LOOP BACK, TEST AGAIN then the high byte, so the true address of the DDR is
E01E 4C OA EO JMP SWTEST1 JUMP BACK 0821 (h).
E021 BD 28 EO DISPLAY LOA TABLE, X INDEXED LOAD FROM
CODE TABLE SET COUNT TO 1 AND DISPLAY
ADDRESS OBJECT CODE LABEL MNEMC OPERAND COMMENT
E024 80 20 08 STA PIO STORE SEGMENT CODE
IN PIO TO DISPLAY E005 A2 01 BEGIN LDX 01 X= COUNT= 1
E007 20 21 EO JSR DISPLAY JUMP TO 'DISPLAY'
E027 60 RTS RETURN FROM SUBROUTINE SUBROUTINE

E028 00 SEGMENT CODE TABLE

Explanation: The X register has been chosen to
E029 06 SEGMENT CODE FOR '1' contain the value count. From now on, the program
E02A 58 SEGMENT CODE FOR '2' will ensure that the value of count (i.e. the X register)
E02B 4F SEGMENT CODE FOR '3' will always reflect the number that is being displayed
E02C 66 SEGMENT CODE FOR '4' on the 7-segment display. The instruction LOX 01 sets
E02D 60 SEGMENT CODE FOR '5' count to 1.
E02E 70 SEGMENT CODE FOR '6' The next step is to display the number held in count.
E02F 07 SEGMENT CODE FOR '7' As the routine that performs this will be required again
E030 7F SEGMENT CODE FOR '8'
in step 9 ofthe program, it has been written as a
subroutine located at address E021.
Therefore at address E007, the microprocessor
Fig. 4.17 Full assembler listing for the flowchart shown in figure 4.16 encounters the instruction JSR DiSPLAY which takes
the form 20 (JSR) followed by the address of the first
instruction in the display subroutine which happens to
The full assembler listing for the program is shown binary form when they are placed in memory. be E021 in this case. The microprocessor will execute
in figure 4.17. Remember that most ofthe information For the sake of discussion, the program has been the instructions in the display routine and then return
contained in the listing is for the benefit of the shown to start at address EOOO(h) butthis could be any to the next instruction in the main program which is at
programmer or anyone else who needs to understand number within the 64k byte memory range. address EOOA.
how the program operates. The microprocessor Also, the port ofthe PIO responds to addresses 0820
requires only the numbers which appear under the for input and output and 0821 for the data direction
heading 'OBJECT CODE' and even these will be in register. (See memory map on page 15).

38
TEST 51 branch would take place and the processor jumps over
ADDRESS OBJECT CODE LABEL MNEMC OPERAND COMMENT
the LOX command.
EOOA AD 20 08 SWTESTl LOA PIO LOAD ACC. FROM PIO
TO TEST SWITCH DISPLAY NEW NUMBER & TEST 51
EOOD 10 FB BPL SWTESTl LOOP BACK IF SWITCH
STILL OPEN ADDRESS OBJECT CODE LABEL MNEMC OPERAND COMMENT

E016 20 21 EO NEWNUM .JSR DISPLAY SUBROUTINE TO DISPLAY

NEW COUNT VALUE

Explanation: The contents ofthe PIO input register are E019 AD 20 08 SWTESTl LOA PIO TESTS1
SWTEST2 IF S 1 STILL CLOSED LOOP
loaded into the accumulator. If P7 is logic 1, that is, 51 E01C 30 FB BMl
BACK AND TEST AGAIN

closed, the N flag in the status register 'P' is set to 1. E01E 4C OA EO JMP SWTESTl

The next instruction at EOOD is the conditional Explanation: The JSR to DISPLAY results in the new
branch instruction 'branch if plus' (BPL). This results in value of count being displayed on the 7-segment
the branch taking place if the switch has not been device. Step 10 requires that 51 be tested again butthis
pressed. time for release. If 51 is still closed, theN flag will be
The offset, which the microprocessor interprets as a set, the BMI instruction will be satisfied and the branch
signed binary number, is FB. This is added to the will occur back to SWTEST2. This loop will continue
program counter contents which results in the PC until 51 is released. When this occurs, the JMP
value EOOA. The next instruction to be fetched will instruction will be executed and the processor is
therefore be the previous one labelled SWTEST1. This directed back to SWTEST1 to wait for the next 51
loop will continue until 51 is pressed, after which, the closure.
next read operation from the PIO will set theN flag to 1.
The BPL condition is not satisfied and the branch will THE 'DISPLAY' SUBROUTINE
not take place. This time, the next instruction to be ADDRESS OBJECT CODE LABEL MNEMC OPERAND COMMENT
executed is at the next address in the program E021 BD 28 EO DISPLAY LOA TABLE, X INDEXED LOAD FROM
CODE TABLE
memory, i.e. EOOF. E024 80 20 08 STA PIO STORE SEGMENT CODE IN
PIO FOR DISPLAY
E027 60 RTS RETURN
INCREMENT COUNT E028 00 SEGMENT CODE TABLE
E029 06 SEGMENT CODE FOR '1'
E02A 58 SEGMENT CODE FOR '2'
E02B 4F SEGMENT CODE FOR '3'
E02C 66 SEGMENT CODE FOR '4'

Explanation: The next step is to increment count. As E02D

E02E
60
70
SEGMENT CODE FOR '5'
SEGMENT CODE FOR '6'
count is being held in the X register, the instruction E02F 07 SEGMENT CODE FOR '7'
'increment X' is all that is required. E030 7F SEGMENT CODE FOR ·a·

IS COUNT= 9? IF SO RESET TO 1. Explanation: In order to display the correct segments

ADDRESS OBJECTCDDE LABEL MNEMC OPERAND COMMENT
to represent the number in count, the code information
E010 EO 09 CPX 09 COMPARE COUNT WITH 9
must be held in a look-up table somewhere in memory.
E012 DO 02 BNE NEWNUM IF NOT 9 BRANCH OVER This table extends from address E028 to E030. The
NEXT INSTRUCTION
E014 A2 01 LOX 01 RESET COUNT TO 1 table contains the segment codes for the digits 1 to 8
(see page 18 in Chapter 2).
The contents of the X register are compared with 9 to The display subroutine begins with the instruction
determine whether the value of count has exceeded 'load the accumulator absolute indexed X mode' on
the maximum display number. If the number in X is 9 base address E028. The microprocessor takes the base
the Z flag in the status register will be set. Under these address given in the instruction, in this case E028, and
conditions, the following 'branch if not equal to zero' adds the X register contents to it to find the effective
(BNE) is not satisfied and no branch takes place. The address. For example, if count was 1, the X register
next instruction to be executed is therefore LOX 01 would be 1 and the effective address would be E029. Fig. 4.16 Flowchart for channel number advance
which resets countto 1.1fcount had been any number So the accumulator will be loaded from this address program
other than 9, the Z flag would remain clear, the BNE which contains the segment code for '1 '.
39
 If the number in count was 5, then the effective
address would be E028 + 5 = E020 which is the
location in the code table that contains the segment
code for the digit 5. Therefore, whatever the value of X,
the display subroutine will always pick up the correct
code from the table.
Having placed the code into the accumulator, the
number may be displayed simply by storing the
accumulator contents into the PIO. That is, STA PIO at
address 0820. The processor is then directed back into
the main program by the RTS instruction.

40
 Part 2

Microprocessor Controlled Systems

41
 INTRODUCTION
Basic digital building blocks, gates, flip-flops,
counters, microprocessors etc., have been dealt with
in some detail in the previous books in this series.
This book shows how these components can be
connected to perform useful tasks.
First, subsystems which might exist in televisions
or similar apparatus are discussed and second,
examples of complete systems will be given. Where
applicable, examples of both hardware (gates,
counters etc) and software (program for a
microprocessor) approaches are given.ln either case
these are chosen to illustrate the general principles
involved, rather than to offer a ready to manufacture
final circuit/program solution.
Where necessary, additional components will be
introduced and, when applicable, reference will be
made to current equipment which uses the principle
under discussion. It should however be borne in
mind that often a large scale integrated circuit is fitted
to a television and its precise internal circuitry is not
available. In these cases the circuit offered is a
'typical' configuration.
To obtain maximum benefit from this book you are
advised to quickly look through the other books in the
series. By this means you will be able to look up any
odd points that may trouble you as you progress. The
microprocessor programs offered are at flowchart
level. For a deeper understanding ofthe
microprocessor programs offered are at flowchart
level. For a deeper understanding of the
microprocessor actions required to achieve these
results, you should read Part 1 of this book.

43
 CHAPTER 5
satisfactory results. using a high speed D to A converter, the analogue
Finally, the binary input words may represent an signal can be reconstituted. For a video signal, in the

DIGITAL AND
actual signal. Here, many words are each presented order of thirteen million words per second will be
to the D to A converter in a short period of time. By presented to the D to A converter.

ANALOGUE
INTERFACING Binary input
A B C D Binary input
A B C D
Systems concepts
L= c
'---~D
D 05 F
'-------IC
The purpose of a digital system is to prqcess binary 04 E
'---------1 B 03 D
words. All binary words have one thing in common. ROM
B 02 c
They can represent 2n permutations, where n is the L--------IA
A 01 ~
B
number of bits in the word. The precise meaning of .,5. DO A
any particular word will however depend on the 4-161ine
wishes ofthe system designer. decoder
Figure 5.1 shows, perhaps, the simplest concept. A
4-bit word is used to represent one of sixteen Fig. 5.1 One of 16 commands Fig. 5.2 One of 16 addresses
commands. A four to sixteen decoder recognises the
individual input words and just one of its outputs will
go high, dependent on the input conditions. Via a Binary input
driver transistor, the command may be executed. A B c D
This concept is used in the U707 and U714 remote I D Binary input

I
I Analogue
D-A 'digitised' video . - - - - - - - - - - .
control systems to achieve remote channel change. c converter
control A -- H H
1---- signal
A similar concept is shown in figure 5.2. Here the B (low speed) I
I
D-A
binary input is a request for the ROM to output the A converter
contents of one of its sixteen memory addresses. (high speed)
Analogue output
Each address is storing a 6-bit word, so a 4-bit input Sig nal output A signal
results in a corresponding 6-bit output from the Signal input
Vol~age
system. Both decoders and ROMS have been dealt
with in previous books.
f0 Controlled
Amplifier
~

The next two concepts may be new to you: figure 5.3

shows a binary input controlling an analogue signal. Fig. 5.4 One of 256 signal voltage levels
Fig. 5.3 One of 16 volume settings
Each binary word input is converted to a
corresponding voltage level by a digital to analogue
converter (to be covered in this book). The de output,
in turn, may control a voltage controlled amplifier
which is processing an analogue signal. A different
binary input word will therefore produce a different
output signal level. This concept may be used to
provide digital (possibly remote) control of analogue
functions, such as volume, contrast, colour,
brightness, etc. If more than sixteen levels are
required, the binary input can be made wider, say,
8-bits wide (256 combinations) and an 8-bit digital to
analogue (D to A) converter used. Since the binary
word is not going to change very often, a relatively
low speed (and cheap) D to A converter will give

44
 CHAPTER 6 A
LT

DIGITAL TO Digital
input
B
c
D
Pulse width
modulator
Filter
de output
(analogue)

ANALOGUE CK
(0-A)

CONVERSION
The pulse width modulator Fig. 6.1 A digital to analogue converter
Figure 6.1 shows, at block level, a popular form of
digital to analogue converter. The binary word,
together with a clock signal, is fed to a circuit
consisting of counters, flip-flops and gates. The
output will go high for a number of clock cycles,
dependent upon the binary word, as in figure 6.2. It
CLOCK
will then revert to the low state. The whole sequence
of events is controlled by the clock signal, which is
split into batches of sixteen cycles (for a 5-bit D to A HT
Input
pulse width modulator (PWM) the clock will be split D c
B A_. PWM
into batches of thirty-two and so on). If the binary 0 0 0 1
input has a low value, the output will be high for a (1)
- -- -- - - - -- -- - - --...,
small percentage of the time and will have a small de 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 de recovered
component. If the binary value is high, the PWM by filter
output will be in the high state for a relatively long Input
HT - - -- -- -~

period so its de component is high. D c

B A_.. PWM
Thus the de component, which is an analogue 1 1 0 1 output
(13) 0
signal, is directly proportional to the value of the
binary input word and can be recovered by a simple
filter. It may be used as a control voltage, e.g. volume Fig. 6.2 PWM waveforms
or contrast setting. PWMs are to be found in IC2 of
the U707 remote control receiver. This method of
digital to analogue conversion is relatively slow, and
is more applicable to figure 5.3 than figure 5.4

45
PWM circuit - figure 6.3 1410kHz..
f'410kHz-t
a
The output comes from the terminal of FF1 which is Counter 1

_n__r
A 8 A
either set, or reset. The flip-flop will be commanded CK cot--..._-,
to change state by signal A (set) or signal 8 (reset) 1MkHz_,~--~~A~B_£C~D~j
which are themselves derived from counters.
Counter 1 will set FF1 every sixteen clock pulses. The
flip-flop will be reset some time later, dependent
upon the binary word input. A gating circuit Counter2
compares the binary word to counter 2 output and
when they are equal, signal 8 resets FF1. Rr--.~--------~
A 8 C D
The sequence of events is as follows. Assume FF1
a
is reset. (the PWM output) is low and 0 is high,
holding counter 2 permanently reset. Counter 2 will
ignore its clock pulses. Assume the binary word input
is 0011 (3). Since this is not equal to counter 2 output
signal 8 will be low.
Eventually, counter 1 reaches 15. Signal A pulses
a
high and sets FF1. goes high and 0 goes low,
counter 2 may now proceed to count subsequent
clock pulses (meanwhile, counter 1 is still working, A 8 C D
Binary input
therefore signal A Qoes low). word
Three clock pulses later, counter 2 will reach '3',
which matches the binary input word. The magnitud.!' CJ
comparator output goes high (signal B) FF1 resets, a
goes high; counter 2 resets; signal 8 goes low
(counter 2 does not equal binary word) and the circuit Fig. 6.3 Simplified PWM
remains locked in this state until counter 1 produces
its next pulse (signal A). The cycle repeats
indefinitely.
Although complex, this type of circuit is popular
with LSI chip manufacturers since it uses only gates XO X1 X2 X3
and flip-flops, which are fairly simple to manufacture
on chip.
Figure 6.4 shows the magnitude comparator
circuit, which is similar to those shown in previous
books in the series.

YO Y1 Y2 Y3

Fig. 6.4 Magnitude comparator

46
Microproces sor PWM
Micros can be used to provide a PWM output,
dependent upon a binary control word. The arrange-
ment is shown in figure 6.5. The program will
set the output high and then enter a delay loop to
count the period Thigh. The output is then set low
and a second delay loop used to count the period T
low. The process is then continued indefinitely. As
with the hardware version of figure 6.3 the analogue
control voltage may be recovered with a simple filter.
The flowchart (figure 6.6) shows the sequence of
events. In the first block, the number to be converted
is loaded into an index register. Suppose that this
number is, for example, 0011 (binary 3). The action of
step 2 will be to load two registers called R high and R
low, with data previously stored in the ROM (figure
6.7. To get the R high data from the ROM, the
instruction load R high from address (1000 plus
index) would have to be executed. Since index equals
3, R high will be loaded with the contents of address
1003 which is 0100. To get the R low data, the
instruction load R low from address (2000 plus index)
would be executed, ie from address 2003.1fthe
original binary word was say, 0101, then R high
would be loaded with the contents of address 1005
and R low from 2005. With the two registers loaded
the program continues by setting the output high
commencing theperiodThi gh. TheA high register is
now decremented until it finally reaches zero. The
time for this to happen (Thigh) will be proportional to
the number loaded in the R high register. The output
is now set low and the micro commences counting T
low by decrementing the R low register. When this
finally reaches zero, provided the PWM signal is still
required, the whole cycle repeats.
Although simple to implement, this program is
wasteful since it dedicates the micro continuously to
the PWM procedure for as long as the D to A
conversion is required.

•..,..,,,
Thigh

-~- Address Data

de 1000 0001
output 1001 0010
Micro 1002 0011
system 1003 0100

I 1004
1005
1006
0101
0110
01.11

2000 1111
Fig. 6.5 A micro used as a PWM 2001 1110
2002 1101
2003 1100
2004 1011
Start
2005 1010

Set output Set output

port- high port-low Fig. 6.7 Contents of some ROM addresses

Use this number as

an index to 'look up'
in the ROM, the values
of T high and T low.
Load R high register
Load R low register

Fig. 6.6 0-A software (PWM)

47
Microprocessor- PWM using interrupt- figure 6.8
A more efficient way of achieving the same result
would be to use a special port which contains a down
I
counter. The micro regards this counter as a standard CK High Is port 2 Low Load binary word
high or low?
address and can write data into it in the normal System to be converted into
clock Port 1 (i) index register
manner. The system clock is fed to the counter and
the counter counts down from the stored data value J counter/
timer
to zero. One count per clock cycle. Eventually, the r INT Get T low data Get Thigh data
counter reaches zero and at this time it generates an CK INT ' Thigh
from ROM from ROM

interrupt signal for the micro. The micro would Microprocessor Set output Reset output port
normally be executing its main program (figure 6.9). ~ port 21ow 2 high
When the interrupt request from the counter/timer is
received, the micro temporarily suspends operation f1--J
·~
Store T low data Store Thigh data
in counter/timer
of the main program, saves whatever data it was Micro system Port 2
port 1
in counter/timer
port 1
processing and notes where it was up to (by writing ® ®
this information into special RAM addresses known
as the stack) and jumps to the interrupt program.
The last instruction in the interrupt program will
always be 'return from interrupt'. The micro reloads
the data previously stored in the stack and continues
•
RTI@ RTI@

Fig. 6.8 PWM using extended counter timer Fig. 6.10 Interrupt program
with the main program as ifthe interrupt had never
occurred. Step 1 of the interrupt program (figure 6.10)
examines the PWM output and determines which of
two procedures to implement. Assuming that the
answer is 'low' the program has to set the output high
and commence the timing ofT high. Again, the binary
word to be converted is used as an index to look up Main program
the Thigh data in the ROM (steps 2 and 3). After
setting the output port high (step 4) the Thigh data is
written into the counter/timer (step 5).
Step 6 RTI is the instruction for the micro to return
from the interrupt. It recovers the main program data
from the stack RAM and continues from there.
Meanwhile, the counter/timer will be independently
Interrupt
counting down toward zero. When it reaches this program
point, it generates another interrupt request. Again,
the micro stacks away its main program data and
jumps to service the interrupt. This time step 1 gives
the answer high. Since the input binary word is
already known, the micro can load in 'T low data'
(step 7); reset the output port low (step 8) and start
Fig. 6.9 Effect of interrupt signal
the timing ofT low (step9). Mostofthetimethe micro
will be executing its main program. Only occasionally
would it be directly involved in the generation ofthe
PWM output.

48
High speed D to A conversion
All the D to A converters discussed so far are
relatively slow in action. When dealing with binary LT
words, which represent actual signal levels, (as in
figure 5.4), a faster system will be required.
Figure 6.11 shows an often used configuration based
on a resistive ladder. To give a low Impedance drive
the word to be converted is sometimes fed to the Output
resistors by digital buffers. The resistors are binary
weighted. Starting at the most significant bit the
resistor values double for each additional bit. For a Digital
very accurate D to A conversion, these resistors must buffers D·AIC
be of precise value (tolerance better than 0.1% (often
achieved by laser trimming of components) and have
negligible temperature coefficient. It is these
constraints that make the apparently simple circuit Fig. 6.11 High speed D-A converter Fig. 6.12
relatively expensive. Normally the buffers, resistors,
and subsequent analogue buffer amplifier are
purchased as one integrated circuit. For less stringent
applications resistor packs can be obtained, and in
the case of an approximateD to A converter, the
nearest preferred value resistors can be wired up. LT LT
Output= LT x RY
The signal is effectively switching the resistors RX + RY
between ground and L T (outputs from switches RX = 8 X 1 = 8k = LT x RY.,. (RX + RY)
RX 8k
9
either low or high) as shown in figure 6.12. With the
1k 8+1 =LTx.B. ~ ra.+!L)
6 \9 6
correct resistors the output will rapidly settle to a Output Output
=LTx.!!_ ~ 16+24
fraction of L T, which is directly proportional to the 6 18
binary input word. With a 4-bit system, as the word is RY = 2X 4 = 8k
=LT X.!!_ 40
increased from 0, 1, 2 .. 15, the analogue output will be RY 2k 4k 2+4 6 6 18
=LTx_!! x !!!
0/15ths LT, 1/15th LT .. 15/15ths LT. Figure6.13 6 40
shows a worked example in the case of the input being 9. =LTx 9
A low pass filter is normally included after the 15
analogue buffer amplifier. Its response falls from just
above the highest recovered signal frequency, to Fig. 6.13
remove switching transients from the signal. For
video signals a six or eight lineD to A is normally
used, with twelve million plus conversions per
second. For high quality audio, 14 to 16-bit converters
are common with forty to fifty-thousand conversions
per second.
A simple wired resistor version ofthis circuit to
produce an analogue output cheaply and effectively
from a slow digital counter to controllV brightness
can be found in IC5 of the THORN EMI Ferguson
U707 remote control.

49
0 to A chip used in software
Figure 6.8 showed how using a counter/timer port
freed the micro from being constantly tied up with
digital to analogue conversion. Nevertheless, the
micro will still have to be regularly interrupted from
its main task in order to maintain the·analogue
output. Using a resistive D to A chip, as shown in Micro system
figure 6.14, frees the micro almost completely from
the task. The flow chart (figure 6.15) shows that the
micro simply loads in the number and then stores it
in the output port. Since the port is in effect a one-
word memory, the micro may now continue with its
other duties until such time as a new word requires to
be converted. The word memorised in the output
port is automatically converted by the D to A chip.
Assuming the analogue voltage is being used for Fig. 6.14 Micro fed D -A
control purposes, as in figure 5.3 the micro may not
be required to change things for some time. Suppose
that one wanted to change to volume setting once
every ten minutes on average, the micro will be Start
detracted from its main program by up to ten
microseconds per ten minutes, which is of course
negligible. It may well be worth paying for the Dto A 1
Load number
chip to give the micro more room to manoeuvre its to be
main program or to allow other functions to access converted
the micro's interrupt facility. <D

2-101JS

Store number
in output
port
(i)

End of subroutine

Fig. 6.15 Software subroutine

50
 CHAPTER 7 general, for cheaper A to D converters, the more the
number of bits in the system the longer each

ANALOGUE TO
conversion will take.
Number of Levels Accurate S/N Ratio

DIGITAL
bits in to (dB)
*
1 2 Not 6

CONVERSION
Analogue Meaningful
input 2
A-D 4 33.3% 12
converter 3 8 14.29% 18
4 16 6.67% 24
Factors affecting choice of system PTC 5 32 3.23% 30
Often an analogue signal will have to be converted to 6 64 1.50% 36
sensor 7 128 0.79o/o. 42
a digital word for subsequent processing by digital 8 256 0.39% 48
circuitry. Factors affecting the choice of system 9 512 0.19% 54
include the rate at which the analogue signal is likely Fig. 7.1 Low speed system 10 1024 0.09% 60
11 2048 0.04% 66
to be changing. The higher the rate, the more 12 4096 0.02% 72
conversions per second must be made in order to 13 8192 0.01% 78
track the signal. 14 16384 0.006% 84
15 32768 0.003% 90
In figure 7.1, a de voltage proportional to say, the 16 65536 0.001% 96
temperature of a furnace, will change quite slowly.
Ten or more conversions per second will be quite •Accurate to 1 part in (levels- 1)
adequate in this case. = 100 %
Figure 7.2 shows a paddle connected to a TV game. A-D
(levels- 1)
If the conversion rate is too low the control will seem converter
sluggish to the user and the laser gun (or whatever) Fig. 7.4 Some parameters which determine
would seem to jump about the screen rather than choice of system
move smoothly. In this case, one thousand or more
conversions per second are called for.
Figure 7.3 shows an audio signal to be digitalised.
Audio signals go up to about 18kHz and it can be Fig. 7.2 Medium speed system
shown (by a theorem known as Nyquist sampling
theorem) that there should be at least two or
preferably more conversions per second for the
highest probable frequency. Twice 18kHz equals
thirty-six thousand conversions per second, add a bit
for tolerance, and you get forty to fifty thousand
which requires a high speed converter. Video
requires twice 5.5MHz plus a bit for tolerance, equals
about thirteen million conversions per second. Very -I A-D
converter
expensive circuits are required for this purpose. In
addition to the conversion rate, the number of bits in
the subsequent digital word, will determine the
suitability of the conversion from different stand-
points (figure 7 .4). A 4-bit system can never be better
than 6 per cent accurate. 8-bits give better than 0.4 Fig. 7.3 High speed system
per cent accuracy. For hi-fi audio work, 12-bits are
considered a minimum, since the final signal to noise
ratio is also a function of the number of bits used. In

51
 The level comparator
Before looking at some analogue to digital converter'
circuits, it will be necessary to run over the operation
v v of a device known as a comparator, which is always
Supply Supply --- -- -- - - - - - - used as part of an A to D converter_
Vref - - - - - - - - - - -
Figure 7.5 shows the device as it would normally be

/,
connected in circuit In many respects it is similar to
Output
an operational amplifier (op amp). It has two inputs,
marked + (non-inverting) and - (inverting)_ It is a
Output __./
Input >---...._--tl..
very high gain (typically times 100 000) amplifier, but

Time
/-~:~:"'
o~===========L-k=b=
Time
whereas an op amp is designed to give linear signal
amplification (with signal feedback) a comparator is
optimised to have its outputs either at (nearly) the
supply voltage, or at (nearly) ground. When the
output changes, it does so very rapidly from one state
Fig. 7.5 Fig. 7.6 Fig. 7.7 to the other, rather like a Schmitt trigger_ Some
comparators have an open collector output and may
require a collector load resistor to be added
externally. If a reference voltage is applied to the
-input, and a signal applied to the+ input, the circuit
will behave as shown in figures 7.6 and 7.7. As long as
the input is lower than the reference, the output will
be low. As soon as the input goes a few microvolts
above the reference, the output goes high, and stays
there until the inp;,~t is brought down again to a few
microvolts below V ref. This is very similar to a
v v Schmitt trigger, except that in this case the hysteresis
r-------.--Supply Supply---------------------- Supply ---- - - - - - - - - - - -,.--==-=-==-=

0
window is very narrow and the trigger point can be
Output set virtually anywhere by adjusting V ref.
The device can be used as an inverting comparator

Input
>-----.. Output - Input

Input
by connecting as in figure 7.8. Figures 7.9 and 7.10
show the circuit operation for different values of V ref.
Level comparators are used in the THORN EMI
Vref --- - - - - - - - - - - -- -
Ferguson TX90 battery inverter.

0 L__b======,u__ Time

Fig. 7.8 Fig. 7.9 Fig. 7.10

52
Analogue to digital converter (figure 7.11) R

illl
The analogue signal to be converted is fed in as V ref
Counter
to a comparator. A counter is clocked and counts up
A 8 C D
from zero, one count per clock pulse. The counter Clock 41atches
outputs are fed to a set of latches, which are. not yet
DO 00 A
activated and also to a D to A con\1erter. For each
clock pulse to the counter, the output from the D to A 01 01 8 Digital output
converter will rise one step. Over a period oftime a word
staircase waveform will build up. As long as this is
D2 02 c
below the analogue level, the comparator output will 03 03 D
stay low. As soon as the staircase rises to just above
the analogue input, the comparator output switches
high to indicatethatthe counter is giving out a digital
word which is as close a digitalisation of the analogue D-A
signal as is possible with the system. As the converter
comparator output rises, it causes two things to
occur. First, it clocks the latches which accept the v
counter output and stores it and second, after a delay
of a few nano-seconds introduced by two gates (to
ensure that the latches have had time to accept the
Supply

;-lL 0 T

counter output), the counter is reset to zero. The D to

Analogue input (Vref)
A output will fall to zero, so the comparator output
follows. After a few nano seconds, the reset terminal
of the counter also goes low. The counter now PTC
responds to its clock pulses and the circuit
automatically starts the A to D conversion procedure
again. The advantage of this circuit over others is that
it is simple to construct. The main disadvantage is Fig. 7.11 Basic A-D converter
that the conversion time will depend not only on the
clock frequency, but also on the amplitude ofthe
signal to be converted. A small signal will be
converted after a couple of clock cycles. A large signal Clock Number of Levels Maximum Number of
frequency bits in system time per conversions
will require, in this case, up to fifteen clock pulses. We conversion per second
normally allow sixteen for time computations.
1MHz 4 16 161JS 62,500
Also, since there are only sixteen levels, the 1MHz 8 256 2561JS 3,900
conversion is only accurate to about 6% (see figure 1MHz 12 4,096 4_1ms 244
7.4). A more accurate A to D converter can be built 1MHz 16 65,536 65.5ms 1.5
5MHz 12 4,096 8191JS 1220
using an 8-bit counter, latches and D to A converter, 5MHz 16 65,536 13. 1ms 76
but it might now take up to two hundred and fifty-six 50MHz 12 4,096 821JS 12,220
clock pulses to convert. The table (figure 7.12) shows 50MHz 16 65,536 1.3ms 760
that using cheap CMOS devices, running with a clock
at 1 MHz, an 8-bit conversion is practicable for
digitising control signals, but even by running at
5MHz, there is no chance of digitising audio or video. Fig. 7.12 Performance of simple A-D system
Other circuits with improved performance will be
discussed shortly.

53
Microprocessor A to D conversion
Since a micro is very good at counting and
remembering (latching) data, it can be used in a
similar manner to the previous circuit. The output
port digital word is repeatedly incremented
(increased by 1) until a conversion is complete. So the Micro system
D to A converter will again 'ramp-up' in a series of Number Levels Maximum Conversions
of bits conversion per
steps. After each increment, the comparator output is in system time second
checked by examining the input port. Whilstthe ramp
is less than the analogue signal, the micro input will 4 16 208us 4800
'End of conversion' 8 256 30881JS 324
be zero. When the ramp goes just above the reference
analogue, the comparator output rises, and the micro
input will no longer be zero. When the micro senses
this, it notes the current binary word in the output Analogue input Fig. 7.15 Performance data
port, and stores it for future use either in an internal
register or some designated RAM address. This
circuit is very similar to the keyscan circuit of the Fig. 7.13 Micro based A-D system
THORN EMI Ferguson VHS model 8930 machine. In
that circuit, the D to A section consists of four

:
discrete buffers and a resistor pack. The analogue
signal comes from a resistive potential divider, whose
value can be varied by pushbuttons. The timings shown

'
·-------Start
alongside the flowchart are approximate for a typical
micro running with a 1MHz clock. To convert an I
r-~·~~----~ 81JS
analogue of maximum amplitude input will take eight I
microseconds for step 1, plus eight microseconds for I +
step 5, plus N times twelve microseconds (steps 2, 3
and 4) where N is the number of possible voltage levels +I ®
Increment
output port
+
6us
in the system (depending, of course, on whether we I
t
•
are using a 4-bit or 8-bit micro) and hence the I
I
number of times the output word must be incremented. I

•'t
The table in figure 7.15 has been approximated but, I 4us
I
by comparing the results with figure 7 .12, it should be I
clear that the micro-based system is much slower
than its hardware counterpart. In both cases, the !I Yes
21JS
accuracy of the conversion can never be better than I
that outlined in figure 7.4 (page 51) and is almost I
entirely dependent on the quality of the D to A
converter used.
I
I
I
I
I
Load values stored
in output port
and store in
t
81JS
designated register

!
I
® or RAM address
+
I
I
L ___ ,.__ End

Fig. 7.14 A-D software

54
Medium speed A to D conversion 'End of conversion' (EOC)
.
---- • '
An improved A to D converter which always takes a
known time to convert analogue signals, is shown in
v
figure 7.16. The circuit is similar to that shown in
JL 1':, EOC
.
-
07 07 07 H
figure 7.11, except the counter is replaced by a series sc
Start 06 06 06 G
of flip-flops, connected as a Successive Approximation conversion 05 05 05 F
Register (SAR). This circuit works on the half split
method of guessing the analogue level. After first
Successive 04
~pprox.imation 03
04 04 .. E 'Digitalised'
03 03 0 outpUt
clearing 00 .... 07 all low, 07 is set high. The DtoAwill Regtster
c
produce HT times 128 divided by 255; approximately
one half HT which works out to 5V. This will either be
02
01
02
01
02
01 . B
too high (comparator output = 1) or not enough ......-- t>cK 00 DO 00 A-
(comparator output= zero). Dependent on the signal Clock
Latches
received from the comparator, the SAR will either
leave 07 set, or clear it to zero, and then set 06 (worth
one quarter of HT).
The table in figure 7.17 shows that the register Too high
H G F E D C
~r
L
B A
successively tries each 0 in turn, gradually
0-A converter
approximating to the correct bit pattern. The
sequence does not start until a start-conversion Too low
I]_
~
command is received. The following rising clock I
edge is then clock pulse 1. As clock pulse 10 rises, it
sets or clears 00; and as it falls an end of conversion
signal is generated to latch the final result and/or
signal other devices, that the digital ising is complete. Analogue input eg. 6V5
At a clock rate of 1MHz one hundred thousand
conversions per second are possible. A 16-bit SAR Fig. 7.16 SAR A-D converter
will take eighteen clock pulses, fifty-five thousand,
five hundred conversions per second which is
suitable for hi-fi audio signal digitalisation.
The whole of the circuit in figure 7.16 can be v
purchased as a one chip analogue to digital 10
I -
--- -
converter. 8 7V5
~-6V886V57
~ Analo gue input = 6V5
Clock Action
DtoA -
converter 6 -
- - """--
r-=-=-~_:_-6vi1 6V49-6V49
pulse 5V
output
1 Clear register 4
2 Set07
3 Set/clear 07 & Set 06 2
4 Set/clear 06 & Set 05
5 Set/clear 05 & Set 04 0 T
6 Set/clear 04 & Set 03
7 Set/clear 03 & Set 02 CK
8 Set/clear 02 & Set 01
9 Set/clear 01 & Set 00
10 Set/clear OO ..... EOC Comp
11 Wait for 'Start conversion'
EOC

Fig. 7.17 SAR sequence Fig. 7.18 Timingdiagram

55
SARto micro connection - figure 7.19
The output from a Successive Approximation Start
Register (SAR) may be directly connected to a micro
system input port. Often the micro system clock is
used to drive the SAR. Start conversion and end of Set port 4
output high
conversion are connected to ports. Actually, these and then low
could be fed from a combined port, since most port
chips have the ability to switch any port pin to either
an output or an input, but for clarity they are shown as
being separate. check input
port 1
Normally the micro would be executing its main
program. If during that program it needs to know the Processor
present amplitude of the analogue signal, it jumps to
a sub-routine, similar to that shown in figure 7.20, Yes
(before actually jumping, the micro stores its present
program position on to the stack RAM, similar to
when servicing an interrupt). First, output port4 is set Micro system
high, then low. This pulse will start the conversion,
I' Load data
which will be automatically completed after ten Digital inputs from port 2
microseconds (assuming a 1MHz system clock). The
micro now checks input port 1.1fzero, the conversion
is not yet ready, so the micro checks again. On the
second or third check EOC will be high. The data at
port 2 is now ready, so the micro loads in the data and RTS
executes a return from sub-routine, by getting back
the program count from the stack RAM and Fig. 7.19 Interfacing A-D chip to micro Fig. 7.20 Get analogue
continuing with the main program. value subroutine
Multi-channel A to D converters are available for
connection to micro systems. These have say, four
independent analogue input pins and the micro can
ask for the digitalised value of any or all of the inputs.
Further detail on these devices is outside the scope
of this book.

56
Bar graph display
Although not strictly an analogue to digital converter,

*_ _ _ _.,
this circuit outlines principles which will be
developed shortly and is therefore included at this
stage.
+12 -18V r=::c:J 10V

The objective is to illuminate a bar of LEOs in

proportion to the amplitude of say an audio signal, ~D,
for example as a recording level indicator, in place of
a VU (Volume Units) meter. The larger the input +3dB
signal, the more LEOs will light. For no input, all LEOs
will be off. For a small input, onlythe-20dB and 10dB
LEOs will light. For half level, -20dB, -10dB and --6dB OdB
will light and so on. An overload will cause all the
LEOs to come on. : :___: :
~

The HT supply is first stabilised by a reference

-3dB
diode. Using a precision resistor chain, the
comp<;~rators are each fed with a suitable proportion
Signal
of this reference. The analogue signal is first input
amplified to a suitable level to drive the system, a -6dB

pre-set gain control being included for calibration.

The signal is then peak rectified and presented
simultaneously to all the comparators. The rectifier
CR time constant is chosen so that the de will decay in
about one second, so that the display will 'hold' short
transient signal overloads which might not otherwise -20dB
have been easily seen on the display. So the circuit is
really a PPM (peak program meter) rather than a VU
(volume units) meter. If the de is say one volt, only
one comparator output will go high; the -20dB LED
is driven on. Five volts de will cause four comparators
to switch their outputs high, driving four diodes on Analogue
input
and so on. In the case of a severe overload, the
catching diode 02 conducts and clamps the analogue
level to ten volts. The reference diode, precision Fig. 7.21 LED bar graph display
resistor chain, comparators and LED limiting resistors
can all be purchased in one chip, a bar graph display
driver IC. LEOs arranged in a bar format can also be
purchased as a package.

57
 High speed or flash A to D converter- figure 7.22
Again a precision voltage reference and resistor
chain are employed. This time the comparator
reference voltages are in equal steps_ When an
analogue signal is applied (say 6V3) some ofthe
comparator outputs will go high, depending upon the
analogue amplitude. All fifteen comparators are fed
to a priority binary encoder. This performs two tasks.
First, it determines which is the most significant input
which is actually high, the 9 in this case, (nine-
fifteenths of ten volts is 6VO; ten-fifteenths of ten
volts is 6V6), and second, it generates the appropriate
4-bit word via an internal diode ROM. If none of the
inputs are high, the encoder generates 0000. The
whole conversion i~ over in a flash, hence the
15
nickname flash converter. Typical conversion times
are in the order of fifty and one hundred
nanoseconds, making ten to twenty million
A conversions per second possible which is ideal for
15-41ine video digitising. An 8-bit output converter of this kind
B ....0
priority requires two hundred and fifty-five comparators, a
encoder c 0 two hundred and fifty-five to eight line priority
encoder, plus the precision reference source and two
D
hundred and fifty-six resistor chain. It is of course, far
more accurate since it can resolve down to a two
hundred and fifty-fifth often volts as against a
fifteenth of ten volts for the 4-bit version. It is a very
expensive integrated circuit, but mainly confined to
professional rather than domestic use.

Fig. 7.22 High speed or flash A-D converter

58
 CHAPTER 8 many channels are combined by this method for
inter-city links, closely spaced sub-carriers being
repeater amplifier may be used to maintain signal
strength. Should a repeater amplifier be overloaded
by input signal, or have non-linearity in its input/
used for each telephone conversation. All the sub-
ANALOGUE SIGNAL carriers must be accurately maintained in frequency,
and all the filters accurately aligned, in order to
ouput transfer characteristic due to ageing or
maladjustment, then 'cross modulation' might occur,
TIMESHARING keep the channels separate (i.e. to avoid a 'crossed
line' or heterodyne whistles). Every few miles a line
resulting in interaction between channels.

Multisignal systems
When signals or data need to be transmitted from
one place to another, one is often faced with the
problem of having more signal sources/destinations
than available transmission paths. Figure 8.1 shows a
simple example. Three sound sources (for example,

..
sports commentaries in different languages) need to
be routed to their respective destinations. Only one Single transmission path
transmission path (say a telephone pair, or a Sound
source 2
microwave link) is available to a distribution point
which can then relay the signals on.
One of two strategies can be employed to solve the Sound
problem: source 3
1. All three signals can be arranged to exist at the
same time in the transmission path in such a manner
that they can be later separated. Fig. 8.1 Analogue signal timesharing
2. Each sound source destination in turn can be
allowed exclusive use of the 'line' for a period of
time.
If each source destination were allowed say thirty
seconds, then the pair would be 'off line' for one
minute, which would not be satisfactory in the
context of a football commentary. Audio 1
On the other hand, ifthe source destination pairs
are connected to the 'line' by a high speed switching 100kHz
Audio 1
system, 'bursts' of information to each destination 100kHz
can be integrated such that a listener is unaware of
the short breaks in transmission, and assumes that Audio 2
he is receiving a continuous signal. 150kHz
Audio 2
150kHz
Line sharing with sub-carriers
The traditional solution to the multi-signal problem is Audio3
to use a sub-carrier for each signal source. Figure 8.2 £>----"-----,
200kHz
shows a simplified arrangement. Each audio source Audio3
is fed to a modulator. The modulated carriers are 200kHz
combined and the composite signal is either applied
directly to the transmission path, or itself modulated
onto a master carrier. At the distribution point, the Fig. 8.2 Line sharing with sub-carriers
sub-carriers are separated by filters, demodulated,
and the resultant audio signals routed to their
destinations.
In an actual system such as the telephone network,
59
HF signal sampling
An audio signal can be sent down a transmission line
as a series of pulses as shown in figure 8.3. Switching
and other functions will be performed by integrated
circuits. Since the audio goes both positive and
negative the ICs can either be powered from a dual
polarity supply (i.e.+ 5V and- 5V), or use a
conventional signal supply rail (positive HT and OV
chassis), and sit the audio up on a half HT bias as
shown. The audio is normally limited to say 2V peak
so that there will be no chance of driving the ICs with
a signal exceeding the supply rail since this might
damage them.
An electronic switch samples the instantaneous
level ofthe signal for a one microsecond period once
every eight microseconds, and applies this voltage to Transmission path Receiver

~"'
10V
the line. There will therefore be 125 000 (1 000 000-:- by

~5V~
8) samples per second down the transmission path.

o%--J
n:
In between samples, the line voltage returns to zero. 2V peak
To allow the samples to rise and fall quickly, a low
impedance line with minimal capacity will be

=F o~-o%-
required. To drive such a line, a buffer amplifier with a
very low output impedance will actually be fitted
between the sampling switch and the line.
At the receiver, a second switch is driven in exact 1~ y
synchronism with the one at the transmitter. Each 11JS 11JS

time it closes, it charges a reservoir capacitor to IL__jl_ Il__fL

sample voltage level. During the period that the i-BIJs-1 1--BIJs--i
switch is open, the capacitor is allowed to discharge a
little via a load resistor. The resultant waveform is
similar to that found in a conventional am
demodulator circuit. It consists of audio plus hf ripple
plus de. A filter removes the ripple, the de may be Fig. 8.3 HF signal sampling
blocked by a capacitor and the audio recovered.
Both switches are 'open' for seven-eighths ofthe
time. During these periods the transmission line is
not being used for this channel, other switch pairs
may therefore use the line.

60
 Analogue multiplexing
10V Several audio signals can 'timeshare' a line using the
10V sampling technique. In figure 8.4 three audio signals
'synch'
and a synchronising signal are in turn sampled and
SV fed onto the line. This sequential switching is
commonly known as multiplexing.
s The analogue audio signals will have a maximum
value of say two volts peak, so sitting on a five volt
0.;--1
Source 1
level they will never go above seven volts. The 'sync'
signal is chosen as a ten volts level so as to be easily
recognised as different from audio samples.

rv -I
The switches operate sequentially, each in turn
being made for one microsecond, with a one
microsecond gap between samples. The voltage on
Source 2 the line will therefore be: sync (10V) 1 microsecond;
zero 1 microsecond; source 1 (first sample) 1
microsecond; zero 1 microsecond; source 2 (first
flu -I
Source 3
sample) 1 microsecond; zero 1 microsecond; source
3 (first sample) 1 microsecond; zero 1 microsecond;
sync (10V) 1 microsecond; zero 1 microsecond;
source 1 (second sample) 1 microsecond and so on.
+ve The switching is controlled by a shift register which

03 04 05 J.~ is arranged to have a single '1' output which re-

Fig. 8.4 Analogue multiplexing
circulates around it's Q outputs, with a 1MHz oscillator
driving sequence. At switch- on a temporary pulse
enables the PE (parallel enable) terminal ofthe shift
register, so the Q outputs are forced to take up the
levels 'wired' to the parallel inputs: 1 000 0000. Since
Q 1 is high, the 'sync' signal is connected to the line.
Shortly after, the PE pulse dies away, the shift register
returns to the serial mode, and for each clock pulse
the Q output's data moves one position right. Since
as is connected to the serial input, aa- 01 for each
clock pulse. The single '1' on 01 will therefore be
shifted:- 02:- Q3: .. :- aa:- 01: Q2andsoon.
Since 02, 04, 06 and 08 do not enable signal
switches, whenever the '1' is in oneofthese positions
the transmission line will be at zero volts. When in
any other position, the '1' will enable the appropriate
signal source or the 'sync' signal onto the
transmission line.
Figure 8.4 can be described as four channel to one
channel analogue multiplexer. To separate the
signals at the far end ofthe line, a 'demultiplexer'
circuit will be required.

61
Analogue signal demultiplexur - figure 8.5
To separate the audio samples which are
'interleaved' on the signal line, a signal switch will be
required for each channel. Each must be made for
one microsecond at the correct time in an eight
microsecond period. The switches will be controlled
by a shift register which must be clocked at precisely
10V
.5V
1MHz as was the transmitter. Should the transmitter
clock drift slightly, the receiver clock must follow.
Further, the shift register must be 'phased' by the
'sync' signal to ensure that a sample is fed to it's
correct destination.
The demultiplexer shift clock will be derived from
the incoming samples. All samples must have a value
greater than OV5, so a comparator may be used to
sense the presence of a sample on the line. The
output from the comparator will be a squarewave
which is high for one microsecond, (any sample
present), and low for one microsecond, (no samples
present). This 500k Hz signal can be frequency
doubled to provide the shift register clock. Since the
sample periods were accurately determined by the
transmitter multiplexer clock, the 'recovered' clock
signal must be ofthe correct frequency. The doubler
consists of an EXCLUSIVE OR gate whose input and
output waveforms are shown. When the 500kHz
signal rises, one input only is high so the output goes
high. After a short while the capacitor charges, both
inputs to the gate are now high so its output goes low.
When the 500kHz signal falls, the capacitor is still

4)
charged, so since one gate input is high the output
0 3 6 7 8 9us goes high again. Shortly after, the capacitor
discharges leaving both gate inputs low, its output
follows. Thus each cycle of input produces two cycles
of output.
~2 As the shift register is clocked, data at the 0 outputs
moves to the right. Since the serial_input is taken to
ground, all Os will be low and no signal switches are
enabled. In order for a '1' to appear at a shift register
output, its parallel enable (PE) must be pulsed. This
... 3 job will be performed by the transmitted sync pulse.
The incoming samples are examined by a second
comparator, this time the reference is 9V5. Only the
10V sync signal samples are large enough to activate
Clock extractor
the circuit. For each sync pulse the comparator
output goes high, via a differentiator (to reduce the
pulse length) PE is taken high, and 01 goes high; 02 ..
08 stay low. As the sync sample falls, the frequency
doubler produces a clock pulse so the '1' on 01
-t 02 : 0-+ 01. As audio sample arrives the doubler
produces another clock pulse; 03 goes high. Audio
·-t\- f\ -f\- -A- -A · sample 1 is now fed via a signal recovering circuit to
-f- -\{-- ~- -\j-- \d-- -. destination 1. When audio sample 1 falls, 04 goes
IlJ1l1fUlflfU1I 1MHz
high. As audio sample 2 rises, 05 goes high and so
on.
Although digital techniques have been used to
route the audio signals to their respective
Fig. 8.5 Analogue signal demultiplexer destinations, it is as well to remember that the audio
samples themselves are analogue; no A to D or D to
A converters have been used in this simplified
system.

62
Long distance communication
The system of analogue multiplexing outlined in
figures 8.4 and 8.5 might work over short distances,
but as line length is increased capacitance will tend to
'round off' the samples. Since these are analogue
samples which can have any value Schmitt triggers
or comparators cannot be used to square up the
samples again. Also signals will be attenuated in long
lines, repeater amplifiers may be required and we
might encounter a signal to noise ratio problem.
One solution is shown in figure 8.6. The multiplexed
samples from figure 8.4 can be loaded onto a
microwave carrier, a microwave link then being used
to span distances of many miles. At the receiving end,
the multiplexed samples are recovered by a
demodulator, and after amplification to a suitable
level, (if we get the 'sync' back to 10V de the other
samples must be correct!) the demultiplexer offigure
8.5 will recover the independent audio signals.
Two further improvements to the system are
possible:
1. For improved signal to noise ratio, the audio
signal samples could be converted to digital words
for transmission using a A to D converter. At the
receiving end, the digital bits can be 'cleaned up' with
Schmitt triggers before being fed to a D to A
converter which would provide the audio samples
for multiplexing.
2. The analogue transmission described is
inefficient because the samples only occur for half
the transmission time, the other half being zero
transmission. With a digital system continuous
transmission is possible, which we shall shortly see
allows more sources destinations to share the
transmission path.

Sync
Sync

Signal 1
Multi-
Demulti-
plexer
plexer
2 2

Sources 3 3

Attenuate
Dish Dish

Fig. 8.6 Long distance communication

63
Digital audio transmission system
The 'front end' of the system (figure 8.7) will be
similar to that already seen. This time however there
will be eight channels; sync plus seven audio. For
simplicity only four channels are shown. Each sample
will be converted to a digital word, in this case 1O-bits
are used which although not 'hi-fi', would probably
suffice for 'voicegrade' telephone communications.
The digital words are fed to a PISO shift register
where they are converted to serial form. The resultant
data stream is fed to a modulator and the modulated
carrier fed to a microwave link.
The carrier oscillator is divided down to drive the
digital circuitry. A 10M Hz signal is used to clock the
PISO, the serial data stream will therefore consist of
ten million bits per second. A further divide-by-ten
circuit provides a 1 MHz signal, both the rising and
falling edges of which are used for various functions.
Sync~ Ea•t----·-,
Sl
etc.
51234567
64
To follow the sequence, assume that the 1MHz
'clock' signal has just fallen, and that a digitised
sample word is being held in the latches. When the
1MHz next rises, the edge performs two functions:
1. A narrow positive pulse is fed to the PJSO PE
terminal. The digital word currently in the latches is
loaded into the PISO, the PE pulse disappears very
quickly so the PISO reverts to the serial mode. The
digital word will be automatically clocked out from
Q 10, bit-by-bit. by the 1OM Hz.
2. The 1 MHz rising edge clocks the recirculating
shift register. The single '1' (set up at switch on)
moves to the next Q enabling the next channel
sample to be fed to the A to D converter.
The clock stays high for five hundred nanoseconds
which is ample time for the signal switches to change
state (say up to three hundred nanoseconds worst
P1· - - - - - - --P10
_.... 1~s I-
I I
'
I I
.IUl_ 10MHz
1MHz
Fig. 8.7 Digital audio transmission system
case) and for the 'flash' A to D converter outputs to
settle to their new levels (50-100 nanoseconds). As
the clock falls. via an inverter it activates the latches
which will'remember' the digitised sample from the
A to D. The cycle repeats indefinitely.
The recirculating shift register is arranged as in
figure 8.3, but this time all the Q outputs are used to
enable signal switches. The audio samples will again
beset upon a dcbiasofhalfHT, and limited to ensure
thatthey cannot reach HT or OV. The sync is again HT
so the A to D will produce 1111111111 for the sync
reference word.
Dependent on system design the serial data stream
might be made to modulate the carrier in one of a
variety of ways. Narrow band frequency modulation
(NBFM) is popular, as is phase modulation (very
narrow band FM!). Amplitude modulation and pulse
position modulation are also used in some systems.
)--
Multiplexed digital audio receiver- figure 8.6
The modulated carrier is fed to a tuner/IF/ demod-
ulator strip whose output will be the 10Mbs data
stream. After the bits have been 'cleaned up' by a
Schmitt trigger to remove noise, they are fed to a
SIPO shift register which will reconstitute the 10-bit
digital sample words. After being clocked into latches
the words are each converted back tc;> an analogue
sample level which is switched via a signal recovery
circuit to the correct destination (as in figure 8.5).
Since in the transmitter the 1GHz carrier was used
as the reference for all digital functions, it can also be
used in the receiver. The 100M Hz IF which is locked to
the carrier by the AFC loop may be processed to
provide a 10M Hz signal to clock the SIPO, and further
divided to provide a 1MHz clock.
The incoming bits are clocked into the SIPO. When
01 .. 010 are all high, the sync signal must be present
in the shift register. A gating circuit (sync word
detector) recognises this unique condition and it's
output goes high performing two functions:
1. The second shift register is parallel enabled. Only
01 (the 'sync' output) goes high and since this is left
unconnected no signal routing switches are yet
enabled.
2. The 1MHz divider(+ by 10) is reset. As this
happens its output goes high which activates the
latches, they grab the sync word, the DtoA produces
+ 1OV de output but this is not connected anywhere
so is at the moment inconsequential and the second
shift register is clocked but since PE is high (due to the
sync word detector) this clock pulse is ignored.
As the SIPO is clocked at 1OM Hz the sync word is
progressively shifted out (the sync word detector
output returns low), and audio 1 sample shifted in,
the 1MHz (+by 10) circuit automatically recycles to
zero, its output goes high. This 1MHz rising edge will:
(i) activate the latches, they grab the audio 1 sample
word and feed it to the D to A converter; (ii) clock
the second shift register - 02 (the channel 1 enable)
goes high enabling the analogue sample from the D
to A to be fed to destination 1.
The process continues indefinitely; each time a
complete audio sample word is clocked into the SIPO
it is 'frozen' in the latches, converted to an analogue
level and routed to the correct destination.
Periodically a 'sync' sample will arrive and guarantee
that the system is properly phased up.
The operations of the SIPO, latches and sync word
detector are of course very similar to the framing
code detector etc. in a teletext receiver.

.----....._ e + - - - - - Channe11

. . - - - - ; . . . e + - - - - Channel2

1234567

10MHz

Fig. 8.6 Multiplexed digital audio receiver

65
 CHAPTER 9
DIGITAL SYSTEM
TIMESHARING
Digital multi-signals
Another situation in which there are many signal
paths required is shown in figure 9.1. Here we have an
electronic timepiece (clock) which consists of a series
of counters with control logic, and a display system.
Each counter produces a 4-bit BCD output word
which must be fed to a 4-71ine decoder/driver IC,
twenty-four lines will be required to carry this data.
Each decoder drives a seven segment display so a
further forty-two lines are required for this function.
In addition the 'common cathode' for each seven
segment display must be taken low in order for it to
be illuminated.
The total number of interconnection lines can be
greatly reduced by using the 'timesharing' technique
which will be outlined shortly. The following
paragraphs briefly outline the timekeeping counter
sequence.
Digital clock sequence
A 1Hz 'seconds clock' signal is derived either by
dividing down mains 50Hz or by using a crystal
oscillator. This is fed to both the seconds counters.
The 'seconds units' counter will increment by one for
each 1Hz pulse, the 'seconds tens' counter will ignore
its clock input until such times as its 'carry in'
terminal is activated. When the 'units' reach '9'
(1001), the counter 'carry out' will change state
and enable the 'tens' carry in. At the next 1Hz
pulse the 'tens' will increment, the 'units'
automatically recycle to zero and the carry out
resets to the inactive state inhibiting the 'tens'
counter.
1HzC K •
The sequence continues until '59' seconds are
reached (0101: 1001 ). At the next 'seconds' clock
pulse the 'units' recycle to zero and the 'tens' try to go
to the '6'. A gating circuit recognises the '60' seconds,
its output goes high and:
(i) clocks the 'minutes' counters.
(ii) resets the seconds tens to zero.
The minutes counters behave in a similar manner
to the seconds counters cycling from '0':'0', through
'5':'9', to '0':'0'. Each time the minutes 'tens' are
reset by the '60' minutes decoder hours counters are
clocked. The control logic for the hours counters will
depend upon whether a twelve hour or twenty-four
hour display is required. Think about the required
sequences in each case!
In addition to the components shown, further
circuitry will be required to allow a user initially to set
the unit to the correct time of day.

~ (Ir
Hours clock Minutes clock
Secood"lt
BCD CKr
I
~ C~l4
1: c
R CK BCD CK CK BCD CK
Cl CC Cl co
DCBA DCB A DCBA DCBA B A D C B A

f-----t-
Decode
logic
Decode I=
'6' f- l=t--< Decode I= f-
'6'

Hours Hours Minutes Minutes Seconds Seconds

'Tens' 'Units' 'Tens' 'Units' 'Tens' 'Units'

Fig. 9.1 Digital multi-signals

66
Digital multiplexing
To reduce the numberofsignallinesfrom a clock chip
to its display, signal timesharing may be employed as
in figure 9.2. The BCD output data words from the
counters are sequentially switched (multiplexed)
onto a common 4-bit data bus, by six four pole
electronic switch banks. The switches are in turn
enabled by signals K,L..P. A single 4-7 line decoder Hours Hours Minutes Minutes Seconds Seconds
Tens Tens Units

01~1:1~1 OIT1~1
will feed out the segment drive code for each display

fi11 I
00 0 1
digit in turn onto the seven segment drive lines.
These are fed to a six digit display pack within which
0\T\11
r1°1 11
the segment drive code is fed simultaneously to all
digits. It is arranged that only the correct digit is
N- :_IS
1 L
I M
I N 0 p
I
activated by taking its common cathode low. The II
other common cathodes are maintained high so they
will not be illuminated.
Once again a single '1' is recirculated around a shift 'Segment'
register to control the sequence. At switch- on 06~ 1 ; r-- drives '-I
01 .. 05~ 0. With 06 high (signal K), the 'hours tens'
4-7
data is routed to the 4-7 decoder which produces the
correct segment drive code. Since K is high, G1 _Til
~I1_1
[ t1I
output goes low enabling the 'hours tens' digit. All of ~ ~ ~
I I -I I
the other inverters will give a high output so the other
:J.. I 1-
-==-I
digits will be off, effectively ignoring the segment I I
••
drive code.
When the shift register is clocked, the single '1'- l L M N 0 p G1
'Digit'
drives',
...=- .=- '- '--
--
lL~ •
K
01; signal P goes high enabling the 'seconds units'
data, and via G6 turns on the 'seconds units' display
PE 06
05
......
G2 I
digit. Clock pulse by clock pulse the shift register ,____
04 G3 I
sequentially enables each digit and its corresponding
data.
f-
,____
03
02
----<
G4 I
Each digit will be 'flashed' for one three-hundredth f- 01
Sl I - ~G5 I
I
1\
of a second, 50 times per second (300Hz/6 digits).
Due to persistence of vision, all digits will appear to ~~ I [__ G6

be continuously displayed with negligible flicker. By CK 300Hz

using this configuration the number of lines to the
display has been reduced from forty-two (figure 9.1)
to thirteen. In addition six 4-7 decoders have been Fig. 9.2 Digital multiplexing
replaced by a single 4-7 decoder plus six data selector
switch banks which in themselves are much simpler
than decoder/drivers.

67
 Microprocessor controlled display
Micro systems are often used to drive displays which
are connected to output ports, sometimes via buffer
driver ICs. Figure 9.3 shows a 4-bit micro system
supporting a six digit display. Two ports are used to
supply the eight line segment drives (seven
segments and the decimal point). Two ports will be
~ Segment drives
required to provide the digit select drive.
L3~----~~----------~1 The program will turn on any one digit by taking the
L2t-----------------------=- appropriate port pin N3.. P2 low; and keeping the
I-
li
L L1 r---
remainder high. To produce a full display each digit is
LO : Ll 1 I enabled in turn. First the micro sets up the segment
M3t----'llr-------__._: ~J !J LJ drive code for a digit, half in port L, half in port M. The
appropriate port pin N3 .. P2 is then taken low for a
M~~ II
MO~---------'
~---1-----1------- millisecond or so to 'flash' the digit. Ports Nand Pare
then set all high to turn off the display. The segment
code for the next digit is then set up in ports Land M,
Micro system the corresponding digitdrivetaken low inN or Pfora
N3~-----------------------' couple of milliseconds, Nand P set all high, and so
N2~--------------------------~ on.
NN1~--------------------------------~ The micro program is simply emulating the
NO~--------------------------------------~ 'hardware' multiplexing routine outlined in figure 9.1.

P31--------'l I
P2l----------1
Digit drives

p P1-
PO-

T
Fig. 9.3 Microprocessor controlled display

68
Micro display software the next digit continues until X finally equals zero (no current value in the X register to determine which
The micro system shown in figure 9.3 could perform more digits to display), this will take 12- 13 milli- RAM location to interrogate and display. If X equals
various functions in addition to supporting the seconds. If necessary the time data in the RAM is '3', the content of address 0053 ('mins tens') is loaded
display procedure. To keep the software as simple as incremented, the X register reloaded with '6' and the in (leaving 0053 unaltered), converted to a seven
possible the function is limited as follows: whole process repeated. segment drive code and so on. Next time X will be
An a rea of RAM will be reserved to hold the present The 'display' subroutine is arranged such that it is '2',address 0052 supplies the data, 'hours units'.
'time of day' in hours, minutes and seconds. Since six suitable for servicing any ofthe digits. It relies on the
display digits are involved, the simplest method of
storage will be six sequential locations, each holding
a 4-bit BCD number representing the digit data. Any
Main Programme 'Display Digit' Subroutine
six 'free' RAM locations may be chosen by the system
designer, once chosen of course the program will be
written on the assumption that these locations are IF X = '6' then display seconds units
forever reserved for the specified digit data. e.g. IF X = '5' then display seconds tens
address 0051 might contain 'hours tens'; 0052- IF X= '4' then display minutes units
'hours units'; 0053-'minstens'; ..... ; 0056-'secs
units'.
IF X = '3' then display minutes tens
IF X= '2' then display hours units
IF X = '1' then display hours tens
____..._ __
To illuminate the display the m1cro must
systematically interrogate the six RAM locations and
in each case convert the BCD contents to a seven Using X as index
Wait 2 ms-
segment drive code (8-bits including the decimal load in digit to be
gives time to
displayed (in BCD)
point, and since the decimal point is not required for RTS
from RAM illuminate digit
the 'clock' the MSb will always be '0') and store the Decrement
X register
bits in ports Land M. One ofthe port pins Nor Pis
then taken lowfortwo milliseconds, to illuminate the Convert BCD to Set all bits in
display. The display may then be turned off and the 7 segment code ports N & P high
to turn off display
next RAM location data serviced.
No
When all six digits have been 'flashed', the micro
checks if it is yet time to increment the time, i.e. has Store top bits in
a full second elapsed? If so the contents of 0056 are port l
store bottom bits RTS
incremented. If necessary the other RAM locations in portM (return from subroutine)
are updated to maintain a sensible 'time of day', e.g.
the time 25 : 72 : 61 should never occur since it is Update time Set appropriate bit
meaningless (the correct time is 02: 13: 01). data in RAM in port N or port P
The main program (figure 9.4) uses the internal X low to turn on
display
register as a down counter to select each digit for
display in turn, and to keep a record of how many
digits are left to display in the sequence. Starting
from '6' the program branches to a subroutine
'display'. This subroutine will cause one digit (in this
Fig. 9.4 Micro display software
case the 'seconds units') to be illuminated. On
returning from the subroutine the X register is
decremented by one, this time it goes to '5'. Since this
does not equal zero the program branches back and
again jumps to the display subroutine, this time
illuminating the 'seconds tens'. The process of
decrementing X and branching back to the display

69
Display digit subroutine RAM
The display digit subroutine of figure 9.4 is now Present Data
Address contents I stored
dealt with in more detail.
The area of RAM shown in figure 9.5a is reserved for 0050 Spare I RAM
0051 0001 (1) I Hours tens
time and is continuously updated every second. The 0052 0000(0) Hours units
time stored at present is 10 hours 29 minutes 37 0010 (2)
0053 I Mins tens
seconds. This time has to be shown on the display of 0054 1001 (9) Mins units
0055 0011 (3) Sees tens
figure 9.3.
Ports N and P of figure 9.3 are fed with the
0056 0111 (7)
I Sees units

'contents' shown in figures 9.5b and 9.5c to turn on

the required digit. For example, if the contents of Fig. 9.5a
1826 (figure 9.5b) and 1836 (figure 9.5c) are fed to
the ports, only port P2 is at 0 and will activate a
digit (ie the seconds digit). ROM-PortN ROM-PortP

Address Contents Address Contents

N3 N2 N1 NO P3 P2 P1 PO
1 1 1 1 1 0 1 1 1821 0111 1831 1111
1822 1011 1832 1111
Ports Land M of figure 9.3 are fed with the 1823 1101 1833 1111
'contents' shown in figure 9.5d to produce the 1824 1110 1834 1111
1825 1111 1835 0111
display number required. For example, if 7 is 1826 1111 1836 1011
required then ports Land M outputs will be the
contents of memories 1807 and 1817. Fig. 9.5b Fig. 9.5c
L3 L2 L 1 LO M3 M2 M1 MO
0000 0111
ROM-Portl ROM-PortM
So to summarise, this display routine must Contents Address
Digitto be Address I Contents
perform two tasks: displayed
•I 9 I t I e
................
d/c/bJa
1. Place an output on ports L and M to produce
the required number 0 -9. 0 1800 "'o~1~ / "1~1~/ .... 1810
1 1801 0000 0110 .... 1811

...
2. Place an output on ports N and P to activate 2 1802 0101 1011 ....1812
the required digit. + 1813

.........
1803 0100 1111

....
3
4 1804 0110 0110 ...... 1814
5 1805 0110 1101 + 1815
+ 1816

...
6 1806 0111 1101
7 1807 0000 0111 + 1817
8 1808 0111 1111 + 1818
9 1809 0110 1111 + 1819

Fig. 9.5d

Fig. 9.5e

Fig. 9.5

70
EXPLANATION OF SUBROUTINE-fig ure 9.6
Suppose X = '6' = when the routine is entered.
STEP 1
The accumulator is loaded with the information from
memory address 0050 + 6 = 0056. This is the seven
sees information- at present.
STEP2
The value 6 is stored in memory address 0050 for
later use.
memory 1101 are stored in ports P3, P2, P1, PO. STEP10
The outputs on ports N and Pare all 1s except port The accumulator is loaded with ls- 1111.
P2 which is 0 causing the seconds digit to light
displaying the numeral7. Again we have 'looked up STEP 11
data in a ROM table'. 1111 is now stored in ports N and P so the seconds
digit displaying 7 goes out.
STEP9 The whole thing is then repeated for X = 5, X = 4
A delay routine of two milliseconds now allows the etc.
eye to register the 7.

STEP3
0111 (7) is transferred from the accumulator to the X
register.
Load accumulator Load Ace. from
STEP4 from address address (1820 +X)
The accumulator is loaded from memory address (0050 +X) and then store

'
<D (j1 in port N.

'
1800 plus the number stored in the X registerwhich is
7. So the accumulator is loaded with the contents of
memory address 1800 t- 7 = 1807. The contents are Save X for later Load Ace. from
use- store in address (1830 + X)
0000 which are now stored into ports L3, L2, L1 LO. RAM0050 and then store
6'
® in port P

t
•
STEPS
The accumulator is now loaded from address 1810
plus the contents of the X register (7), so the Transfer Ace. Jump to 'short
accumulator is loaded with the contents of memory to X register delay' subroutine
address 1810 + 7 = 1817. The contents are 0111 and ® (@

are stored into ports M3, M2, M1, MO.

Land M ports now contain acombination.of1s and
t
Load Ace. from Load Ace
Os to form the numeral7 on any one of the six display address (1800 +X) with 1111
LEOs. and then store
@
in port L.
We have performed a BCD to 7 segment (.i:
conversion using the data to 'look up' new data in a
ROM table.
STEPS
•
Load Ace. from
address (1810 +X)
and then store
OJ)
Store Ace. in
port N.
Store Ace in
port P
X = 6 is obtained from memory 0050 and stored in in port M.
®
1
the X register.
I
STEP7
The accumulator is then loaded with the contents of Get back old X RTS
memory 1820 + 6 = 1826 and these contents are 1111 load X from

'
RAM 0050
which are stored in ports N3, N2, N1, NO. (6:

STEPS
Similarly the accumulator is now loaded from
memory address 1830 + 6 and the contents of this
Fig. 9.6

71
 CHAPTER 10
DIGITAL DATA
TRANSFER
Two chip operation
A microcomputer chip is a complete subsystem
containing a processor, RAM, ROM, input and output
ports. Often one microchip is used for all time-
keeping and display operations. However, if it is
required to increase the number of functions that the
system will perform, a situation may occur where
because the micro is often busy servicing various
subroutines, it cannot go through the 'display'
routine often enough to maintain a 'continuous'
display. The digits might either tend to 'flicker', or
even worse- go blank temporarily.
Various solutions to the problem are available,
these include:
• Using a micro which can operate at a higher clock
frequency. Each instruction in the various
1Hz
Jill
from
customer
controls
72
subroutines will be performed more quickly,
allowing moretimetosupportthedisp lay. Micros are
now available which can work with 6MHz, 10M Hz or
even higher clocks. In general, the faster the micro,
the greater will be its cost.
e Using a micro with a wide word length capability,
e.g.8-bit instead of 4-bit, will allow more data to be
processed per instruction, often effectively speeding
up the processing of a subroutine.
• Using two or more microchips, designating part of
the work load to each. Some form of communication
between the chips will be necessary so that data can
be passed between them as required.
In figure 10.1, the 'timekeeping' microcomputer is
programmed to be responsible for examining the 1Hz
input and updating the 'latesttime' held in six internal
RAM locations, necessary to maintain the correct
time of day. It also periodically examines an input
port to determine if the user wishes to 'set the time';
or in the case of an alarm facility or some other timed
event enter the data to be stored in other reserved
RAM locations. At regular intervals the chip will
nmedata
Timekeeping Display
microcomputer microcomputer
chip chip
Fig. 10.1 Two chip operation
systematically copy its current time data, digit by
digit into an output port to update the other micro.
The 'display' micro will support the display as
previously described, occasionally loading in the
latest timedata present at its input port digit by digit,
in each case storing the 4-bit BCD word in the correct
one of six internal RAM locations. Some system of
synchronism is required between the chips. lfthe
display chip loads in a '3' (0011 ), it will need to know if
this represents 3 hours or 3 minutes or 3 tens of
seconds etc. Various methods of synchronising the
data transfer between chips are possible. One of
these will be outlined shortly.
Some THORN EMI video recorders such as model
8924 use multiple microcomputer chips in a similar
manner splitting the work load between them. The
same micro could be used for either 'timekeeping' or
'display' provided its internal ROM had been
programmed accordingly.lfoneofthesec hips has to
be replaced it is important to use one containing the
correct program.
D
 Timekeeping chip RAM 1Hz 'clock' Timekeeping micro program
The micro will be required to 'keep the time' in six
RAM Present Data
address contents stored RAM locations, for this example addresses
0001 .. 0006 have been chosen as shown in figure 10.2.
0001 0001 (1) Hours tens The program starts by checking portYto see if the
0002 0000 (0) Hours units A
0003 0010(2) Minstens
user wishes to enter any data into the system. If so,
0004 1001 (9) Mins units the micro jumps to a subroutine which checks which
8 Wait for low to
0005 0011 (3) Sees tens
high transition button(s) have been selected and takes the
0006 0111(7) Sees units
appropriate action.
Time= 10:29:37 C Increment time Having dealt with a possible customer request, the
1Hz signal at port X must be examined to determine if
Fig. 10.2 Fig. 10.3 a full second has yet elapsed, if so the time must be
incremented; if not the micro waits for the correct
conditions to occur. In this case it is waiting for a low
Timekeeping' chip main program
to high transition as the signal to increment the time.
If the 1Hz signal is high, the micro first waits for it to
Check port Y Subroutine go low. Whilst waiting the micro might as well do a
for customer Increase time useful job so it jumps to a subroutine which sends the
request by 1 second
current time data (contents of addresses 0001 .. 0006)
to the display micro. This subroutine will probably
take about 1 microsecond. Eventually the 1Hz signal
Subroutine
Send present goes low and will stay there for 500 milliseconds
time data to before returning high and signalling the micro to
increment the time.
Again the micro enters a delay loop which includes
the 1 microsecond 'send time to other micro'
Check input subroutine. The present contents of addresses
at port X
0001 .. 0006 will therefore be communicated to the
display micro several hundred times per second. As
you will see later this makes collecting of data by the
Subroutine display micro a very straightforward job.
Send present Eventually the 1Hz signal rises, the micro jumps to
time data
to other micro a subroutine which actually increases the time and
after sending the new time to the display micro the
timekeeping chip jumps back to the beginning of the
Recheck input whole procedure.
at port X The program just discussed is by no means the
most efficient possible, but is intended as a general
guide to the process involved. The subroutines
u routine
'increment time' and 'send present time to
Send present other micro' will now be outlined.
time data to
other micro

Fig.10.4

73
Subroutine - increase time Timekeeping chip RAM
The six RAM locations holding the present time data
can each be thought of as a counter. As with the RAM Present Data
address contents
'hardware' time clock (figure 49), each must be stored
incremented in the correct sequence at the correct 0001 0001 (1) Hours tens
time to maintain a sensible 'count'. 0002 0000(0) Hours units
The subroutine starts by loading in the seconds 0003 0010 (2) Minstens
0004 1001 (9) Mins units
units data and adding '1' (0001). For the majority of 0005 0011 (3) Sees tens
occasions that the subroutine is used, this is the only 0006 0111 (7) Sees units
action required. The seconds units will be less than
'10' so after storing the new 'count' in address 0006 Fig. 10.5
the micro can abandon the sequence and return from
the subroutine.lfthe count reaches '10' (1010), this is Subroutine- increase time
a legal binary count but not allowed in a BCD system.
The seconds units must be recycled to zero. This is Load accumulator Load accumulator
achieved by loading the accumulator with 0000 and from address 0006 from 0004
then storing this in the units counter (address 0006). and add 1 and add 1
The 'seconds tens' must now be incremented.
Again, most times that this is done, the result is
valid (below '6'). The new 'seconds tens' count is
stored in 0005 and the micro returns from the
subroutine. The process continues if an invalid result
occurs as shown in the flowchart. As with the
'hardware' timeclock logic, special decisions have to
be made with regard to the correct sequence of Load accumulator Load accumulator
incrementing the hours counts, dependent upon with zero with zero
store in 0006 store in 0004
twelve-hour or twenty-four hour timekeeping modes.
These will not be pursued further at this point since a
full discussion would take several pages and would Load accumulator Load accumulator
only be of value to a professional program writer. from address 0005 from 0003
Whichever branch of the subroutine is taken, it will and add 1 and add 1
always end with an 'RTS' instruction. The subroutine
could last anything from about twenty microseconds
(most times) to about one hundred and fifty
microseconds (once every twelve hours or so).

I Yes
I
Load accumulator
with zero
store in 0005
l And so
on
I

Fig. 10.6 Subroutine- increase time

•
RTS

74
Subroutine - send time to second micro
The timekeeping chip must periodically Timekeeping micro RAM
communicate the current contents of its 'time'
registers (address 0001 .. 0006) to the display chip via RAM Present Data
address contents stored
a port. The data must be coded in some maoner so
that the display chip will know which digit is to be 0001 0001 (1) Hours tens
represented by the 4-bit data word currently being 0002 0000 (0) Hours units
0003 0010 (2) Minstens
put out by the timekeeping chip. Some systems use a 0004 1001 (9) Mins units
start code followed by the data words in a prescribed 0005 0011 (3) Sees tens
sequence at set intervals. This program uses a unique 0006 0111 (7) Sees units
codeword for each digit followed by the digit data
itself. Although a little inefficient in terms of Fig. 10.7
processing time, this system will make the
probability of data being used for the wrong digit in
the display so low as to be insignificant.

'
Subroutine- send time to other micro
Since valid BCD codes are '0' ..'9', the invalid
numbers '10'to '15' can be used as codes to announce Load index
Decrement
which data actually follows. By good fortune there register X ,--

No0
X register
with '6'
are six codewords available, and six data words to
transmit! The codes will therefore be allocated: '15'
followed by 'seconds units' data; '14' followed by
'seconds tens' data; ..... '10'followed by 'hours tens'
t
Copy X into the
accumulator and Zero?
data. add '9'
Again the index register X is used as a
downcounterto determine how many data words are
left to transmit, and as an index to look up the t Yes

relevant data in the RAM. Starting with X at '6', by Store accumulator

in output port
copying this into the accumulator (leaving X RTS
unaltered) and adding '9', the accumulator will hold
'15' this time round. '15' is stored in the output port
and left there for seventy-five microseconds. The
t
Subroutine
accumulator is then loaded with the contents of Short delay
address 0006 (leaving 0006 contents unaltered). The 75~s

data (this time '7') is then stored in the output port for
seventy-five microseconds. X is decremented (goes T
Load accumulator
to '5'), since this is not zero the subroutine branches from address
back around the loop. '14' is stored in the output port (0000 + X) then
for seventy-five microseconds, followed by the store in output jJ_Ort
contents of address 0005 (seconds tens data) for
seventy-five microseconds.
T
Subroutine
The loop is repeated until X= '0'. At this time the Short delay
micro returns from the subroutine to its main 75~s
program. Note that on leaving the subroutine the
output port is holding the 'hours tens' data which is a I
valid BCD code. This data will remain in the port until
the subroutine is called next time.
Fig. 10.8 Subroutines -send time to second micro

75
Subroutine - get latest time data their correct internal RAM locations. codeword '10' ..'15'. Suppose we start looking at a
The display micro of figure 10.1 (page 72) must We saw earlier that the display chip might use time when the other micro is not going through its
collect the latest time data from the timekeeping addresses 0051':>.0056 to store 'hours tens' .. 'sees transmitting sequence. The data found will be the
chip digit by digit. The subroutine which follows, units' and that address 0050 was unallocated. In this 'hours tens' data which will be a BCD number less
forms the block 'update time data in RAM' in subroutine address 0050 will be used as a down- than '10'. The subroutine loops back and continues
figure 9.4 (page 69). As previously outlined, each counter to keep check of the number of digits which searching for a codeword. Eventually the
digit data word will be preceded by a unique have been received. The program starts by loading '6' timekeeping chip starts its transmitting sequence
codeword; '10' .• '15' to identify which digit is (0110) and storing digits, 0050- '0' signaling the end and sends '15'to indicate 'seconds units follow
actually available for transfer between the chips. of the subroutine. shortly'. This will cause the X register to be loaded
The subroutine is designed so that accurate synchron- Having set the count in 0050, the routine continues with '6' ('15'- '9'= '6'). The input port is now
isation between chips will not be necessary. It will by examining the input port, searching for a rechecked, this time for a BCD data word. On the first
simply identify six digit data words and store them in few rechecks '15' will be obtained since the
transmitting routine contains a seventy-five
Subroutine- Get latest time data microseconds delay on each output word. Eventually
Display chip RAM
the actual data is received and will be stored in
Load accumulator address 0056 (0050 + X which has previously been
RAM Present Data Store accumulator
address contents stored with '6' and
in address
loaded with '6'). A digit has been received so 0050 is
(0050 +X) decremented (to '5'). Since it is not yet zero it
0050 xxxx Spare RAM branches back and commences searching for the
0051 0001 (1) Hours tens
0052 0000(0) Hours units
next codeword. This when it arrives will be '14'; X is
0053 0010(2) Minstens Decrease the loaded with '14'- '9' = '5', and the subsequent data
0054 1001 (9) Mins units contents of word will be stored in RAM address 0050 + 5 = 0055.
0011 (3) Sees tens address 0050
0055
0111 (7) Sees units
The process continues until all six digits have been
0056
received and address 0050~0'. The micro will then
'return from subroutine'. The entire transfer of six
Fig. 10.9 digits will take about five hundred microseconds (6 x
No
75 microseconds + delay for transmitting to start).
In practice it is unlikely that the routine will be
entered at exactly the time that the timekeeping chip
Yes was not transmitting; it is more likely to break into
the middle of a transmission. This subroutine will
Subtract '9'
then copy into RTS
correctly identify and load in six digits no matter
X register where it breaks into the transmission sequence. At
some point there will be a short delay with the display
loop locked in a loop waiting for transmission to
Load accumulator recommence. Since there will be hundreds of
from input port identical transmissions per second there will be no
noticeable effect on the display itself. If however the
timekeeping chip were faulty and not transmitting,
the display micro would be forever locked in the loop
Yes awaiting data .... since it cannot escape to service the
display routine, the display will be permanently
blanked.
The routines outlined are not those used in the
8924 video recorder, but have been designed to show
in basic terms how two chips can be made
interdependent by software.
Fig. 10.11 Subroutine -get latest time data

76
Serial data transfer concepts When the last word has been transmitted, micro 1 Multi-processor systems
In many digital systems data words aretransmitted in takes its signal line output low to indicate the end of Some complex systems use multiple microcomputer
serial form. In effect the many bits of the word are transmission, (the data line will of course stay high as subsystems, each performing dedicated tasks as
multiplexed onto a single data line. The received bits previously outlined). Micro 2 responds by taking its shown in figure 10.14. Micro 0 is the 'management'
are built up to form the original word- signal line low to break the communication link. micro which co-ordinates the operation ofthe others
demultiplexed! Figure 10.12 shows a possible By the same means micro 2 can transmit to micro 1. which might have the functions listed. The serial data
arrangement. In most systems the micros each
'listen' to their input line awaiting data. When it
arrives, the micro clocks in the data bit by bit, rather
like a shift register. When a complete word is
available, the micro stores it into a suitable register or
RAM address. To assist in the process the data line is
normally kept at logic 1 (high) when no transmission
is taking place.
The actual bits of the data word (message bits) are Serial data line
preceded by a 'start bit' logic 0 to signal that a stream
of bits will shortly follow. Figure 67 shows the - - - - - - - - - - - - -i:>- - -
sequence for an 8-bit word transmission .. start bit; Signal line
message bit 1; message bit 2; .. message bit 8; stop bit
= logic 1. The stop bit terminates the one word Micro 1 Micro2
transmission. The duration of each bit will be
identical and is set by a delay loop in the transmission I
program. 300-bits per second; 1200-bits per second;
2400-bits per second are all commonly used data
rates. The receiving micro program waits for a start
I
I
1 Signalline
v
1
I_------------- - -- - --<::1-- - - - - - - - - - - - - - - - - - - - - - - - _I
bit, and then times each bit and clocks it in. Obviously
the receiver must know the transmission data rate in Serial data line
order to getthings right. Some systems use two 'stop
bits' (a logic 1 to time the duration) between
successive word transmissions. Fig. 10.12
The system works well if the receiving circuit has
no other functions to perform. If on the other hand the
receiving micro has to service various functions and
occasionally check if data is arriving, there is a
v

------1
possibility that it will look at its serial date input Start
after a transmission has started and they lose some
of the data. To overcome this problem additional M1
lines may be used as 'signals' to indicate that a M2 M3 M4 M5 M6 M7 M8 Stop
micro is ready to transmit and or receive data.
A system of 'handshaking' is often used, a typical
T
sequence might be: micro 1 wishes to send data to
micro 2 which may have various tasks to perform.
Mirco 1 takes its signal line high to 'flag' or signal Fig. 10.13 Serial data transfer concepts
micro 2 that it has data ready. Micro 1 does not yet
commence transmission. Occasionally micro 2
checks its signal input awaiting this 'flag'. On receipt
of the flag micro 2 signals (flags) micro 1 to indicate
that it is ready to receive the data. It responds
by sending the serial data at the agreed data rate.
77
bus is connected to a single port pin on each micro.
The micros each have the ability to configure any port
pin as either an input or an output. This change can be
made at any time during a program. (See Part 1.)
Normally all micros will have the pin configured as
an input, and whilst servicing their independent
functions will occasionally 'listen in' to see if any data
is present on the serial bus which would otherwise be
resting high. If necessary a micro can call up one of
the others by (i) making its port pin into an output
pin and (ii) putting out a serial codeword onto the
data bus.
For example micro 0 calls micro 2 by putting out
'000101'.1gnoring the '0' start bit and the '1' stop bit
we are left with 0010 = '2'. Micro 0 now listens for a
suitable response codeword from micro 2 to indicate
that it is ready to receive instructions/data. The other
micros will have noted thatthis is data for micro 2 and
will therefore ignore the following transmission. If
micro 2 missed its cue it will not respond. Micro 1
waits a short while and then tries again for as many
times as are necessary to catch micro 2s attention.
To save embarrassment of several micros trying to
call each other at the same time resulting in
pandemonium on the serial bus, all messages are
either routed via micro 0; or passed directly between
the slave micros with micro Os permission.
The complete system might be part of a
'supersystem' with micro 0 being slave to micro 11
(say) in the larger scheme. An intersystem bus will
allow a large controlling computer access to
interrogate or command each local system as
necessary. By this means 'head office' can be
constantly in touch with precisely what is happening
at various branches, plants, depots etc.

+
100k
Inter-system serial data bus

+
--------!:> 100k
4
System serial data bus

0
land 11
on inter-
system bus) ·

Micro 0. System management

& user inputs
Micro 1 . Timekeeping 3
Micro 2. Display
Micro 3. Motor control
etc.

Fig. 10.14 Multi-processor systems

78
 GLOSSARY
Accumulator General purpose register used in con-
junction with the ALU. When adding two numbers
together, for example, the ALU will expect to find one
of them in the accumulator and this register will also
be over-written by the resulting sum.
Active high/low A statement referring to the logic
level of a signal that is required to activate a digital
device.
Address A character or group of characters that
identify a register, a particular location in memory or
some other data source or destination.
Addressing mode The component of the instruction
op code that specifies how the operand may be located.
ALU See Arithmetic/Logic Unit.
Architecture The functional capabilities provided by
the manufacturer in the design of the device; including
such specification as the number and type of registers,
internal and external control lines etc.
Arithmetic logic unit (ALU) The digital logic within
the processor which performs all arithmetic and
logical functions called for by the program.
Assembly language Code written using the
processor's instruction set mnemonics, labels and
comments in order to produce an understandable
program from which object code may be produced.
BCD (Binary Coded Decimal) A type of positional
value code in which each decimal digit is binary coded
into 4-bit words.
Bi-directional Generally refers to interface ports or
bus lines that can be used to transfer data in either
direction, for example, to or from the microprocessor.
BIT Contracted form of Binary digiT. May be one or
zero. Smallest element of data that may be stored,
manipulated or retrieved by a digital computer.
Branch To depart from the normal sequence of
executing instructions in a computer; synonymous
with jump.
Branching A method of selecting, on the basis of the
computer results, the next operation to be executed
while a program is in progress.
Buffer A device designed to be inserted between
devices to match impedances or equipment speeds, to
prevent mixed interactions, to supply additional drive
capability, or simply to delay the rate of information
flow, classified as inverting or non-inverting.
Bug A program defect or error; also refers to any
circuit fault due to improper design or construction.
Bus One or more conductors used as a path over
which information is transmitted.
Byte An IBM - developed term used to indicate a
specific number of bits treated as a single entity; most
often considered to consist of eight bits.
Clock The basic source of synchronising signals in
most electronic equipment, including computers; a
specific device or unit designed to time events.
Conditional jump/branch A specific instruction
which, depending basically upon the result of some
arithmetical or logical operation or the state of some
flag or indicator, will or will not cause a jump to an
instruction in another area of the program.
Condition codes Single flip-flop type elements
within a computer which are set or resetto indicate the
result of an operation carried out by the ALU or
indicate the status of various functional areas within
the processor. Also referred to as flags or status bits.
Control bus Microprocessor bus carrying input and
output control signals for synchronisation, external
condition sensing, memory management, etc.
CS Abbreviation for chip select
Data A general term used to denote any or all facts,
numbers, letters, symbols, etc. which can be
processed or produced by a computer.
Data bus A group of bidirectional lines capable of
transferring data to and from the MPU, storage and
peripheral devices.
Data port Physical point at which data enters or
leaves a device or system.
Fetch The period of a computer cycle during which
the location of the next instruction is determined, the
instruction taken from memory and then entered into
the instruction register.
Flags See condition codes.
Flowchart A graphical method employed by pro-
grammers to indicate the stepped procedures of a
computer operation; a chart containing all the logical
steps in a particular computer program; also called a
flow diagram.
Hardware The metallic or 'hard' components of a
computer system in contrast to the 'soft' or pro-
gramming components; the components of hardware
may be active, passive, or both.
Hexadecimal notation A system of number repre-
sentation using the base of sixteen. Decimal
characters are used for 0-9, after which the
characters A to F represent decimal10 -15. May be
abbrieviated to 'hex'.
Input/output devices Computer hardware capable
of entering data into a computer or transferring data
from a compl!ter; abbrieviated to 1/0.
Instruction Information which, when properly coded
and introduced as a unit into a computer, causes the
computer to perform one or more of its operations.
Instruction cycle That sequence of operations or set
of machine cycles which effects one complete
instruction.
Instruction set The total group of characters which,
when presented to the computer in their binary form,
will result in a pre-determined action or series of
actions occurring within the processor.
79
Interface Device or circuit which allows two or more
systems using different protecols of data
representation to communicate accurately.
Interrupt The suspension of normal operations or
programing routines of computers; most often
designed to handle sudden requests for service or
change; the process of causing the microprocessor to
discontinue its present operation and branch to an
alternative program routine; also the physical pin-
connection line input to the processor.
1/0 Input/Output.
Large-Scale Integration (LSI) A term describing the
level of complexity of gates on a single semiconductor
chip. LSI chips usually exceed a size of 100 x 100 mils
and may contain more than 100,000 transistors.
Loop A self-contained series of instructions in which
the last instruction can modify and repeat itself until a
terminal condition is reached.
Machine code or language The basic binary code
used by computers; it may be written in hexadecimal
notation.
Memory Stores information for future use; accepts
and holds binary numbers or images.
Memory map A table showing which addresses in
the machine's addressable range have been allocated
and to which devices.
Memory mapped input/output Describes the design
practice of assigning a particular memory address or
group of addresses to an input/output port or device.
Microcomputer A general term referring to a
complete computing system, consisting of hardware
and software and whose main processing blocks have
been implemented using semiconductor integrated
circuits.
Microprocessor A principle component of the micro-
computer. An integrated circuit capable of performing
the major processing tasks associated 111tith the central
processing unit (CPU) of larger computers.
80
Mnemonics The system of letters adopted by a
manufacturer to represent the abbrieviated form ofthe
instruction in the instruction set ofthe computer.
MPU Microprocessor unit
Non-volatile A memory type that retains data even if
power has been disconnected.
Object code The basic program in the form of
executable machine code in the language of the
particular processor.
Operating code (opcode) The specific code relating
to the instruction set which selects the required
processor operation.
PIO Parallel input/output circuit. A device containing
latches, buffers, flip-flops and other logic circuits
needed for versatile input/output between a micro-
computer and external circuits. Usually a member of
the 'family' of devices associated with the micro-
processor in use. May be called Peripheral Interface
Adaptor (PIA) or Versatile Interface Adaptor (VIA).
Program A set of instructions arranged in sequence
which direct a computer to perform a desired
operation or series of operations.
Programming model Pictorial representation of the
internal register set of the processor which may be
diractly affected by programmed instructions or which
may directly affect program execution.
RAM Memory in which any individual location may
be accessed directly. In relation to semiconductor
memory devices, it has become synonymous with
read and write memory.
Read The process of copying data from an external
device to an internal memory location with respect to
the processor.
Register A flip-flop or group of flip-flops capable of
containing one or more data bits or words.
ROM Read-only memory; programmed by a mask
pattern as part ofthe final manufacturing stage.
Information is stored permanently or semi-
permanently and is read out, but not altered in
operation.
Routine A set of computer instructions arranged in a
correct sequence and used to direct a computer in
performing one or more desired operations.
Scratchpad A 'nickname' for an area of ram memory
used by the program. It is memory containing sub-
totals, for example, or various unknowns that are
needed for final results.
Signed binary numbers A binary representation of a
real number in which the most significant bit is
reserved for the sign of the number, (MSB = '1' =
negative: MSB = 0 = positive).
Software Programs, languages and procedures of a
computer system.
Stack A block of successive memory locations that
is accessible from one end on a last-in-first-out (LIFO)
basis.
Stack pointer A register within the processor which
contains the address of the next available unused
location in the stack. It is automatically adjusted each
time a value is added to, or removed from the stack.
Subroutine A self-contained program that may be
'called' from the main program. Execution passes
from the main program to the subroutine and then
back to main program at the instruction immediately
following the subroutine call.
System clock See clock.
Truth table Mathematical table showing the Boolean
algebraic relationships of variables.
Vector A software routine's entry address; also the
address that points to the beginning of a service
routine as it applies to interrupting devices.
Volatile Storage medium in which data cannot be
retained without continuous power dissipation.
Word A group of binary digits which together
represent an element of information, e.g. a number, an
ASC11 character etc.
Write The process of copying data from an internal
memory location to an external device with respect to
the processor.
 APPENDIX
called the variables. X has been used here to denote AND operator in this manner, they are referred to as
the output. In all cases, the boolean expression states product terms.
the condition of the variables that must exist to cause Further examples are:
Boolean algebra and expressioos the output to be true, i.e. X goes to logic 1. A . B . C, X . Y . Z, T. S . X . Y etc.
Boolean algebra is a means of expressing a logic The negating overbar of the NOT function should
function. It offers a shorthand system to define logic always be used to modify the variable or the variable
conditions which is both concise and unambiguous. expression rather than the output.
Three logic operations are used as the basis for all For example, th~NOT function is equally true when
expressions. These are: expressed as A = X but it is not accepted practice to
negate the output in this fashion. The expression X + Y describes the OR gate above.
1. The AND operator Variables linked by the OR operator are referred to as
Example: Example:
sum terms.
To express the logic function ofthe gate below, the
Further examples are: X+ Y + Z, A+ B + C + D,
AND operator would be used.
T + S +X etc.

:=O-x
When expressing the logic function of a more
complex gating system, the use of parentheses, as in
standard algebra, becomes important. For example, in
This is the NAND gate which is formed by the AND gate the gating system drawn below, the AND gate
followed by an inverter, i.e. produces the product term A . B. This term then forms
A AND B = X i.e. A. B = X a variable in its own right for the following OR gate.

2. The OR operator
Example: :vA.B
The logic function of the gate below would be
expressed as follows: The input requirement of the gate has not been C--------------~
changed, therefore the variable expression is still
A . B. However, as the output has been negated, the
whole input expression must carry the overbar to lfthe expression for the complete gating structure is
reflect the condition when X is true, i.e. A . B [NOT (A now expressed as A . B+C, it is no longer clear that
AND B~. Similarly, the NOR gate below follows the A . B is a product term produced by an earlier AND
same rules. function.
A OR B =X i.e. A+ B =X The expression is only unambiguous when
parentheses are incorporated, i.e. (A . B)+ C. Without
3. The NOT operator A~. A~~B~ them, the expression may be misinterpreted to
Example: B~X= B~~-A+B produce the expression A . (B+C) which would be
The inverter below performs the NOT function and satisfied by the gating structure below.
is expressed as follows:
Here, again, the variable expression for the basic
gate remains as A+ B but i~t be negated as a result

A --{>o-x of the inverted output, i.e. A + B [NOT (A OR B)]. A.(B+ C)

SUM AND PRODUCT TERMS AND PARENTHESES

NOT A =X i.e. A =X
Note A is pronounced 'not A' or 'bar A'.

VARIABLES AND OUTPUTS The expression of the AND gate function above is
In the foregoing examples, the inputs A and Bare A . B. When two or more variables are related by the
81
The logic of this structure is completely different from Binary arithmetic Expressed in boolean terms, this becomes:
the earlier example as is proved by the truth table for
each below: BINARY ADDITION (A. 8) +(A. B)= SUM which is the Exclusive OR
The rules of binary addition are as follows: expression and A. B = Carry which is the AND
(A. B)+C A. (B+C) expression.
0+0=0
A B c X A B c X 0+ 1= 1
Therefore, the half adder may be configured as drawn
0 0 0 below.
0 0 0 0 0 1+0= 1
1 0 0 0 1 0 0 0 1 + 1 = 0 carry 1
0 1 0 0 0 1 0 0
1
0
1
0
0
1
1
1
1
0
1
0
0
1
1
0
When adding two binary numbers of more than one
bit, the carry 1 must be added to the next column left as :---.~~~Sum
1 0 1 1 1 1 in decimal addition.
0 1
0 1 1 1 0 1 1 Example:
0 Carry
1 1 1 1 1 1 1 1 0510 01012
SUM OF PRODUCTS 0910 10012
-
14
--
1110 Multi-bit adder When adding two multi-bit binary
A IV ---.::::; numbers, except for the least significant bit, some
Carry Carry
provision must be included in the adder to accept a
B carry IN from the previous column. The adder which is
(A . B) + (C . D) Example: capable ofthis is called a full adder. One method of
c configuring a full adder is with two half adders and an
0 0 0 1 1 1 0 12 OR gate as shown belo'!'f.
D
1 1 0 1 0 1 1 02
Carry in
1 1 1 10 0 1 1
In the example above, the two AND gates yield the
product terms A . Band C . D. As they form the Carry
variable inputs for the following OR gate, the final
expression becomes: (A. B)+(C. D). Binary addition using digital electronics To perform
This type of expression is called a Sum-Of-Products the addition oftwo one-bit numbers requires a circuit
(SOP) term. called a half adder.

PRODUCT OF SUMS
A ------r-::-1- Sum

A
B~Carry
B Half adder 1 is performing the basic binary addition
(A + B). (C + D) By the addition rules, the truth table for the two to yield the half sum. Half adder 2 adds the half sum to
c outputs is as follows: the carry in from the previous bit to produce the full
sum out.
D
A B Sum output Carry output The following circuit will perform the addition oftwo
0 0 0 0 2-bit binary numbers:
A..s-o 1 0
In this example, the sum terms produced by the two A.B-1 0 1 0
OR gates, A+ Band C + D, form the variables for the A.B-1 1~1
final AND gate. This yields the Product-Of-Su ms (POS)
term (A+ B).(C + D).
82
 For example:
- - - - - - - - - - - - - - O B i t 1 sum
+510 = 000001012
-510 = 100001012

r----t--fD---o
Carry to bit 2
However, by adopting the procedure of representi~g
Bit 2 sum all negative numbers in 2's complement form, the s1gn
is handled automatically.
The 2's complement form of -5 is found by the
method described, i.e.
5 = 00000101
1's complement = 11111010
Add 1 +1
2's complement = 11111011

Microprocessor addition The arithmetic logic unit
(ALU) of most microprocessors is capable of adding
two 8-bit binary values and producing an 8-bit result.
The carry out of the final bit will set or clear the carry
flag in the status register.
Binary subtraction The rules for binary subtraction are
as follows:
binary subtractor using standard digital techniques.
However to include both an 8-bit adder and an 8-bit
subtract~r into a microprocessor ALU would require a
complex gating structure. To avoid this complex.ity,.
the ALU is only given the ability to add. Subtraction IS
carried out by a method called 2's complement
addition.
If this convention is adopted, all addition and sub-
traction operations will result in positive numbers
being in true binary form and negative numbers being
in 2's complement form with the MSB automatically
assuming the proper sign.
Examples:
Add+ 710 and +5 10

0-0=0 1's Complement numbers The 1's complement of a 7 00000111 true form
0 - 1 = 1 borrow 1 binary number can be obtained simply by 5 00000101 true form
1-0 = 1 complementing (i.e. inverting) each bit. 12 00001100 true form
1- 1 = 0 For example: '\
Sign bit +ve
Binary number 100110
Example:
1's complement 011001 Subtract 5 11) from + 710 is the same as:
1010 10102
-610 -01102 2's Complement numbers The 2's complement form of Add -5 10 to + 710
a binary number is found by adding '1' to the least
410 01002 significant bit ofthe complement form. 7 00000111 true form
v
For example: +(-5) 1 1 1 1 1 0 1 1 2's complement
Borrow
+2 00000010 true form
Binary number 01101
'\
Example: 1's complement 10010 Sign bit +ve
Add 1 +1
110110012 21710 2's complement 10011
0 1 1 1 0 1 0 12 = -11710 Subtract+ 710 from +5 10 is the same as:
0~~
1 1 0 0......1 0 02 10010 Signed binary numbers The 2's complement ~ddition Add -710 to +5 10
method has distinct advantages when used w1th
Borrow Borrow computers in the handling of signed numbers. When -7 11111001 2's complement
handling signed numbers, the most significant bit +5 00000101 true form
BINARY SUBTRACTION USING DIGITAL (MSB) is the sign bit. A '0' in the MSB position indicates -2 1 1 11 11 10 2's complement
TECHNIQUES a positive number and a '1' indicates a negative '\
As in the addition problem, it is possible to configure a number. Sign bit- ve
83
OVERFLOW ERRORS In the previous example, C7 and C6 are 0 and the result If we list the conditions of C7 and C6 along with the
When the MSB of a data word is being interpreted as a is correct. truth of the result from the preceding examples, the
sign bit, any carry out of the preceding bit will true form following table results:
6910 01000101
represent an overflow. C7 C6 Overflow error
+ 10310 01100111 true form
For example: 0 0 No
-8410? 10101100 2's complement
Sign bit Data bit 6 0 1 Yes
/--
01011010 true form
~--
C7=0 C6=1
1
1
0
1
Yes
No
01101011 true form -11 010 10 0 10 0 10 2's complement
11000101 2's complement +(-92)10 10100100 2's complement Expressed as a boolean function, this becomes:
-~ 00110110 true form (C7. C6) + (C7 . C6) which is the Exclusive OR
Carry condition.
C7=1 C6=0 When performing binary arithmetic, therefore, the
Here there has been a carry from the data bit 6 into the
sign bit. This, when interpreted as a 2's complement ALU checks for a carry from bit 6 to bit 7 and the status
In the two examples above, only one carry has been ofthe carry flag (which will have been set if a carry had
number, represents -59 10 which is obviously generated. In the top example C6= 1 and C7=0. In the
incorrect. A strategy must be devised in order to been generated out of bit 7) and performs the
next C6=0 and C7= 1. In both cases, the answer is exclusive OR operation upon them. The result will set
identify erroneous results of signed binary addition. incorrect.
Consider the following example: or clear the overflow (V) flag, i.e.
In these final two examples, both C6 and C7 are '1'.
-2 1 1 1 1 1 1 1 0 2's complement
-40 10 1 10 1 10 0 0 2's complement
+(- 2) 1 1 1 1 1 1 1 0 2's complement
+89 10 0 10 1 10 0 1 true form
~ 11111100 2's complement Carry from bit 6 = J D -
+49 0 0 1 100 0 1 true form To overflow flag
llt.i'C From carry (C) flag
Carry
C7=1 C6=1
Here again, there has been a carry from bit 6 to bit 7
but, in this case, the answer is correct. -57 11000111 2's complement
The problem may be resolved by looking atthe carry +(-26) 11100110 2's complement
into the sign bit position and the carry out of the sign -83 10101101 2's complement
bit position. If we call these C6 and C7 respectively, the ~

following examples will show how an erroneous result C7=1 C6=1

may be detected.
And in both cases the answers are correct.
+410 00000100
+610 00 00 0 1 10
10 00001010
..........................
" -----
C7=0
-
C6=0

84
Index

Analogue signal timesharing timekeeping micro program 73 interrupt request (IRQ) 21

analogue multiplexing 61 two chip operation 72 master reset input (RES) 20
analogue signal demultiplexer 62 Digital system timesharing negative (N) flag 26
digital audio transmission system 64 digital multiplexing 67 Non-Maskable Interrupt input (NMI) 21
HF signal sampling 60 digital multi-signals 66 non-overlapping clock signals 21
line sharing with sub-carriers 59 microprocessor controlled display 68; display digit overflow error detection 25-6
long distance communication 63 subroutine 70-1; software 69 overflow (V) flag 25
multiplexed digital audio receiver 65 Digital to analogue conversion •p• register-Bit 5 25
multisignal systems 59 converter 45 pin assignments 20
Analogue to digital conversion D to A chip use 50 processor status register 24
- converter 53 high speed 49 program counter register 22
bar graph display 57 pulse width modulator 45: circuit 46; micro using programming see separate entry
factors affecting choice of system 51 interrupt 48; microprocessor as 47; waveforms 45 Read/Write line (R/W) 21
high speed 51 Ready (RDY) line 21
high speed or flash 58 Hexadecimal notation 10, 28 reset sequence 27
level comparator 52 Set Overflow (SO) input 21
low speed 51 stack pointer 26
Microprocessor 6502 20
medium speed 51,55 Sync pin 21
accumulation 23
micro based system 54 Zero (Z) flag 25
address buffers 22
Successive Approximation Register (SAR) use 55-6 Microprocessor controlled systems 43
address bus 20
Arithmetic/logic unit (ALU) 3, 4, 6 Microprocessor see Processor
addressing modes 30
of 6502 microprocessor 24 MOS Technology 20
ALU 24
MCS6500 programming manual 32
break command (B) flag 25
Binary arithmetic 82-4 carry (C) flag 24, 25
Bits, 2, 4 control bus 20 Program, the 15
Boolean algebra 81-2 data bus 20 examples 15-19
Bytes 4 data register buffers 22 flowcharts 15, 16: symbols 15
decimal mode (D) flag 25 infinite loop 15
Data processing 3, 14 double precision arithmetic 24 look-up table 18
NAND and NOR 3 index registers X andY 26 segment code 18, 19
Digital and analogue interfacing 44 instruction codes 30 Programming
Digital data transfer instruction decoder 23 addressing: absolute 31; absolute indexed 32; immediate
multi-processor systems 77-8 instruction fetch cycle 22 30, 31; implied 30; modes 29-30; relative 31-2; zero
serial data transfer concepts 77 instruction register 23 page 31; zero page indexed 32
subroutines: get latest time data 76; increase time 74; internal architecture 22 coding the program 37-40: 'assembler' form 37, 38;
send time to second micro 75 interrupt mask (I) flag 25 steps in 38-40

85
Programming contin. addresses in hexadecimal notation 10 internal registers 5: accumulator 5; data buffer 5
instruction format 28: opcode 28; operand 28, 37; binary to hexadecimal to binary conversion 11 memory map 14
types of instruction 28 bits, bytes and words 4 microcomputer chip 13
instruction set 28, 29: machine or object code 28, 37, control bus 9 minimum configuration system 13
38; use of hexadecimal notation 28; use of mnemonics data bus 5 parallel input/output device (PIO) 12, 13
28,37 data direction register (DDR) 12 practical memory storage 9
simple techniques: count loop 32-4; delay loops 35; data 0/P and 1/P registers (DOR and Dl R) 13 random access memory (RAM) 9, 11-14 passim
looping program with counter 34; program loop 33; data port 5 read-only-memory (ROM) 11-12,13,14
subroutines 36 data processing 3, 14 read/write control 8-9, 21
'soft' model 28 decimal to hexadecimal conversion 10 reset 7
Processor, the 3 hexadecimal to decimal conversion 10 system clock 5
address bus 9 input/output 12, 13 system program 11-12
address decoding 11, 13 instructions and program 6 3-bus system 9
address pagination 11 memory address 8 6502 microprocessor see Microprocessor 6502

86