54-5
Low-Latency BCH-CRC Decoder for 3D CT NAND Flash Memory Applications
Hongyang Hu"', Haiyang Liu', Kai Xi', Kun Zhang-", Junyu Zhang', Eng Liu':"
'Key Laboratory of Microelectronics Devices andIntegrated Technology, Institute of Microelectronics, Chinese Academy of
Sciences, China
'University of Chinese Academy of Sciences, Beijing, China
.Email:liujing@ime.ac.cn
Abstract - This paper presents a low-latency
BCH-CRC decoder for 3D CT NAND flash memory,
The presented decoder uses the hard-decision
values as the input, which can avoid the energy-
consuming sensing operations for generating the
soft-decision values and hence extend the life time
of flash memory, In order to improve the error
correction performance, a BCH-CRC concatenated
coding scheme is developed, Moreover, the BCH
decoding algorithm is optimized to reduce the over-
all cost of the decoder, We implement the proposed
decoder targeting at 3D CT NAND flash memory
applications, The user data length is 512 bytes,
which is divided into four segments, A 16-bit CRC
is appended to each segment, and then the message
sequence is encoded by a BCH code with 9-bit error
correction capacity, The decoder is realized in a
65nm CMOS process, which can achieve a decoding
throughput of 191MB/s with latency 2,795Jls,
I. INTRODUCTION
Nowadays, the three dimensional (3D) Charge
Trap (CT) NAND flash memories have attracted
much attention, as they provide a much larger storage
capacity than the planar NAND flash memories with-
out increasing the equivalent area occupation [1],
However, reliability issues [2] in the 3D CT NAND
flash memories evoke high raw bit error rates,
making the error correcting coding (ECC) techniques
mand-atory to guarantee the data safety of the
memory chip,
Hard-decision schemes are an important class of
ECC schemes, which use hard-decision values as the
input of the decoder and avoid multiple sensing oper-
ations. Moreover, these schemes usually have low
complexity merits, which make them suitable for the
applications where the decoding latency is stringent.
In this paper, we develop a BCH-CRC conca-
tenated coding scheme to improve the error correction
performance of HI) decoder. In order to reduce the
overall cost of the decoder, we optimize the key steps
of BCH decoding. The proposed decoder is imple-
mented targeting at 3D CT NAND flash memory
applications. The synthesis results suggest that the pre-
sented decoder is superior to the comparable decoder
implementations in the literature.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY SILCHAR. Downloaded on November 09,2022 at 07:59:31 UTC from IEEE Xplore. Restrictions apply.
II. DESIGN AND RESULTS
Fig, 1 illustrates the designed ECC scheme for 3D
CT NAND flash memory applications, The user data,
which is of length 512 bytes, is divided into four
segments, A 16-bit CRC with generator polynomial
g(x) = X16+X15+X'+ 1 is appended to each segment
for the data integrity check, which leads to a message
sequence of length 4160 bits, Then the message
sequence is encoded with a (4277,4160) BCH code
whose error correction capacity t = 9,
A. Decoder Design
Fig, 2 describes the flowchart of the presented de-
coder. Fig. 3 represents the block configuration of the
decoder. The BCH decoding is the main part of the
decoder, whose key steps include the syndrome cal-
culation, the error locator polynomial calculation, and
the error location search etc. In order to reduce the
overall cost of the decoder, these key steps are opti-
mized. For instance, a parallel syndrome calculation
structure is developed to enhance efficiency. As an-
other example, the inverse-less Berlekamp-Massey al-
gorithm is applied for calculating the error locator
polynomial. Fig. 4 depicts the timing diagram of the
presented decoder.
B Results
We synthesize the presented decoder using a 65mn
CMOS process. The synthesis results are summarized
in Table L We know from the table that the presented
decoder has higher throughput and lower latency com-
pared with other comparable decoder implementations.
ACKNOWLEDGMENT: This work is supported by China
Key Research and Development Program
(20 16YFA020 1804).
REFERENCES
[1] J. Cho, D. Kang, J. Park, et al, (ISSCC), 2021, pp.
426-428.
[2] Y. Kong, M. Zhang, X. Zhan, et al, vol, 39, 2020,
pp. 4042-405 L
[3] T-H Chen, Y-Y Hsiao, Y-T Hsing, et al. 200927'h
IEEE VLSI Test Symposium, pp.53-58.
[4] 1. Crippa, G. D. Martino, 1. D'Onofrio, et al,
IEEE ISSCC, 2006, pp. 497-506.
 User Data

D CRC Encoding

'- Uscr Data --J~

D BCH Encoding

User Data

4096

Fig. 1. Proposed BCH-CRC concatenated coding scheme.

TABLE 1 Performance comparisons
Parameters [3] [4] Our work
Data size(Byte) 512 512 512 All Segments
Successful ? N
BCH error correction
9 5 9
capacity (t)
Decoding
4.22 96.8 2.795
Latency/us)
Gate count 158.9K 325K 125.8K
Frequency(MHz) 125 25 200
Throughput(MB/s) 119 N/A 191
Fig. 2. The flowchart of the presented decoder.
1------ 1
Barrel I Syndorme I
Syndr_ Gen Erro r Calc
Shift-Regs I Shi ft-Regs I
i_ app_ wr i_ syn - h 0_ syndr_ 0 I Ii synd_xin 1 - - -xS---1
i app sof
RO 1 i serial din
I GF-Mul 11 syndr 1 I' RO I
-
I I
i app eof
R1 1 I GF-Mul_2 1 0

0 syndr 2 I
R1 I
I
I I GF-Mul_1 1 I
i app din
t R2 I
I
: I GF-Mul_2 1 :
Rn 1 I GF -Mul_B I
I
I I t I
I
I

-
0 syndr 16 I
R16
I I
I GF-Mul 91II
I

syndr_ 17
I I
i app_rd (J 0_
0 R17 I L ______ ~

:::0 I
app_dou t I
0

app info
~
0
CRC-16 I I I
0
I--' I- - - - - - -I
I--'
0 app hs kd (l)
I-j
- Error
B-bit Location Polynomial
Calculation

Fig. 3. The block configuration of the presented decoder.

~ _ a p _ so f i _ app_eof Syndrome El e ment Co ff oes
In i t i al i za t i o n I ni t i a li za ti o n
4... /
/
<,
<, 1
I I /
<,
<, 1
1
I /
i a p p_ wr B-b i t Da ta I npu t ...........1 1/
I
i _ a p p _ d in 1 / B - b i t Decode
Syndrome c al culati o n
1
I ... ~
/
Ou t p u t i _app_rd
I o_a p p_ do u t
I Er r o r
I
L o c at i on Po lynomi al

:.
I

I
Ca l c u l a t ion
•
I Er r o r
I L o c a t i on S e a rch
535t I lBt I 5t 5 35 t
I I

I I To tal L a tency 559 t

I I
I I
I I
Fig. 4. The timing diagram of he presented decoder.

Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY SILCHAR. Downloaded on November 09,2022 at 07:59:31 UTC from IEEE Xplore. Restrictions apply.