Williams CPU 1.

This is the basic design of the CPU board used in the Williams 360, 40S or 550 series of games. Reel or
Video, the CPU is much the same design. The processor used is an 80C188 by Intel (or others). This is an
8-bit machine with 20 address lines (1 M Byte capability). Running from a 40 MHz clock it still takes this
puppy a serious part of a microsecond to do anything. This 40 MHz clock is divided down to make
Processor clock cycles, and it may take many clock cycles to complete an instruction. Memory speed is up
over 120 ns, so we can say we still only get about two instructions per microsecond, and it can only do
things 8-bits at a time. "Oh no!" he said. "It's an IBM PC XT!" Well, close.
Not wanting to duplicate the entire circuit of the schematic, if you have the schematics available to you,
you may follow along. If you have the games you should have the books. If you don't, this article won't
mean a lot to you anyway. So grab your Williams 550 Drawing Set and fill your coffee cup. Here comes
the lesson.

PAGE 1 of A-17677-03
This is a drawing of what the filter capacitors are. These capacitors are spread throughout the board and
keep noise off of the power lines that run to every IC on the board. Most of these are Ceramic 0.1 uF
(microfarad) guys. Real cheap, and can fail, shorting out, and taking down the +5 Volt line. Finding a
shorted one among the many can be done easily using the Freeze Spray approach mentioned in earlier
articles. The "Upper Lip" method woks fine if you do not like the freeze spray approach, but has limitations
if you have facial hair between lip and nose and the board is all surface mount devices. A word in support
of the upper lip method, it does get the nose and eyes closer to the board, both of these are good
troubleshooting tools also.

PAGE 2
These are the two main board connectors. You see more than two? These are Eurocard design. Each
connector is three rows of 32 pins. The pins are labeled A01 to A32, B01 to B32, and C01 to C32. The two
connectors are labeled P1 and P2. Each pin is given the name according to connector and pin number, like
P1-A01. J1 and J2 are where a Daughter board may be plugged in for extra features.
To simplify (did I say simplify?) the drawing a bus line is used to avoid having the drawing use two
hundred line on this page. Leaving the plug, each line is given another name describing its function. That
line goes elsewhere on the board. You can follow the line by matching the name exactly. In many cases
multiple wires are going off in the same direction so that feed all these into a Bus Line, or trunk. The trunk
is given a name as it leaves the page. Following the bus you can find the line as it leaves the bus by
matching the name of the signal.

PAGE 3
On the left-hand side we see the 80C188 processor. Starting from the top, the first eight lines are the
multiplexed 8-bits of the Data Bus and the lower 8-lines of the Address Bus. During Address Latch Enable
time these lines are the lower eight address bits which get latched in an external latch by the ALE signal.
During Not-ALE times this is the 8-bit Data Bus taking data In or Out of the processor. A8 through A19 are
the upper address lines. When an instruction begins the address lines are set up by the 80C188 to select
some external device the microprocessor is going to talk to.
S0, S1 and S2 are the three status lines that tell external device what kind of operation the CPU (the
80C188) is presently performing. These signals start earlier in the machine cycle than the next few lines we
are going to cover. DEN\, DT/R, ALE, RD\ and WR\ are the strobe lines that also work to tell external
devices what the current instruction is performing and also provide timing pulses for when things should
happen. This is a typical Synchronous Bus design. The timing of the bus operations is set, and the bus can
not run any faster than the slowest device. (That is a lie we will get around to correcting in a minute.)
ALE is Address Latch Enable and is used to latch the address lines into an external latches, U21, U22 and
U23.
RD\ is the Read strobe. When it is low the 80C188 is reading data into the processor on the Data Bus.
WR\ is the Write strobe. When the 80C188 is putting data out on the data bus this line is low.
Any time ALE, RD\ and WR\ are not being asserted the Address and Data lines are tri-stated (not being
pulled high or low).
RFSH (Refresh) is a timing pulse for dynamic memory devices, of which we use none on this board.
LOCK and HOLDA (Hold Acknowledge) are part of a DMA (Direct Memory Access) feature the 80C188
has. We do not use this either. Associated with these lines are DRQ0, DRQ1, and Hold, just opposite on the
other side of the 880C188 drawing. These are all tied to ground and these functions are not used.
UCS and LCS are strobes for Upper Chip Select and Lower Chip Select. The 80C188 is a 16-bit processor
on the inside. In our case, this function is also not used and the 80C188 just runs as an 8-bit machine.
The next 11 lines are a programmable port built inside the 80C188 for us to use as we will. We apparently
will only to use four of them that leave the chip named PCS0\ through PCS3\. The "\" following the name
means the signals are active low, low when this function is happening. The over score on the names in the
schematic has the same meaning, we just can't easily do that here.
Next we find two Interrupt Acknowledge lines (INTA0 and INTA1). The 80C188 puts these out in
response to recognizing an Interrupt Request line being High (INT0 and INT1). We only use INT0. INT1 is
disabled.
The 80C188 has two built-in Timer / Counters. The inputs to these two circuits are TMRIN0 and TMRIN1,
the outputs are TMROUT0 and TMROUT1, none of which is used in this design.
RESET is the reset output of the 80C188. This may occur as a result of the 80C188 executing a Reset
instruction, or something pulling the RES\ input line low.
CLKOUT is the 40 MHz clock signal. I think it is divided by two in the 80C188 before it leaves the chip.
This provides that Synchronous Timing I talk so much about.
Going around to the other side of the IC we will cover signals we have not yet mentioned. X1 is the Clock
Input pin. In this case we apply a 40 MHz clock signal here. We can get the processor to run at slower
speeds by applying a slower clock. We would do this if we designed the circuit around slower memory
devices, for instance. We must adjust the operating speed of the 80C188 to the speed of the slowest device
in the system.
TEST\ is a testable pin we can deliberately sense from a special instruction. This is a Polling operation. The
80C188 reference this pin and essentially asks, "are you High?" Contrast this with the Interrupt process we
will describe next.
INT0 is an Interrupt Request line. The external circuits inform the processor that some expected event has
happened by pulling on this Interrupt Request line. The processor then stops its present process, puts it
aside and performs the operation required by the interrupt. When that operation is completed it goes back to
what it was doing. This kind of Interrupt is Maskable. The processor can decide to not recognize the
interrupt if what it is currently doing is of higher priority, such as doing a Power-Up or Power-Down
routine.
NMI\ is a Non-Maskable Interrupt. This is a more urgent operation than general operations of the
processor. In the case of Gaming Devices, this is almost always used exclusively for Power Failure
Warning. This interrupt may not be masked out. When NMI\ goes low the next operation to be done will be
to perform whatever function is called for in the NMI routine. The only thing more important is Reset.
We have here in the previous few paragraphs a description of how the 80C188 assigns priority of tasks to
be performed. Other than Reset, the tasks are prioritized as; NMI, INT0 and INT1. If none of these are
pending the processor executes the next instruction in program memory. TEST is done under program
control so it has the lowest priority of all.
There are other operations considered in the Priority scheme, but this is a lesson on the Williams game, not
the 80C188, so we will keep it simple.
The Ready lines (SRDY and ARDY) are used to add an extra Processor clock cycle when slower devices
are selected. This is the means of slowing down the processor when certain devices are selected. Other wise
we would have to slow the processor down to a crawl. These lines come from XU12, which we will get to
in a minute.
The ICs along the top and middle of Page 3 are the Address and Data buffers. The 80C188 is a CMOS
device and can not drive more than a milliamp or so. To drive all the circuits connected to the 80C188 we
need drivers to provide, well... more drive capability.
XU12, MACH110-15, is a large programmable logic device designed specifically for Williams and the
CPU 1.5 design. This circuit performs many functions such as Address Decoding and Wait - ready
functions. When certain devices are referenced by Address Decoding the MACH110 recognizes these as
slower devices and pulls on the 80C188's Ready lines (SRDY and ARDY). The 80C188 then adds an extra
clock cycle in the present Read or Write operation. Most of the outputs of the MACH110 are active low
signals, and if you learn to read the Williams Codex, you can understand what they mean.
I see PROM0RD\ as being low when EPROM 0 Read (XU3 on page 4). PROM1RD as EPROM 1 Read
(XU2 on Page 4). The "4" by the off-page connector symbol means the other end goes to Page 4. SRAM\ is
a timing pulse for U11 on Page 4. SRAM0RD\ and SRAM0WR\ are the Read and Write strobes for Static
RAM 0 (U5). SRAM1RD\ and SRAM1WR\ do the same for RAM 1 (U4).
XRAMR\ and XRAMW\ are read and write RAM strobes for whatever is plugged into the Daughter Board.
XIOR\ and XIOW\ are the I/O Read and Write strobes for the Daughter Board.
LIOEN\ enable the devices on the CPU board onto the 80C188's data bus. XIOEN\ enable data from the
Daughter Board.
The Upper Address lines A10 through A19 are decoded to determine which of the above mentioned strobes
will be activated. Each function has its own unique address. Only one of these outputs should be low at any
given time.

PAGE 4
Starting along the bottom, because we already covered most of this, we have the RAMs and EPROMs.
What we didn't cover is the RTC (Real Time Clock). U10 is a 72421 (by gum, this really is an XT!).
Just above that we have two CAT35C704 EEPROMs. If you have ever set one of these games up, you
know what the EEPROMs do.
U11 is a MAX791CPE. This is our Reset Supervisor chip. Built into it we have the circuit for handling
battery power when the game is turned off. It gets its input from +5 Volts. Senses the level of the +5 Volt
line and gives a warning if the +5 Volt line is low (LOWLINE\). It monitors battery voltage and gives a
warning if battery voltage is low (BATTLOW\). It controls our Watchdog timer we will get to when we
cover page 5. It also generates MRST\, Master reset if +5 Volts is low or the reset Button (SW1) is pushed,
or on Power Up.

PAGE 5
U24 and U25 are Programmable Logic Arrays. XU24 controls Interrupt functions of Power Reset,
Watchdog, and NMI. XU25 controls decoding of the lower three address lines when it is selected by the
PSC0 output from the 80C188. These things we will cover as the circuits they drive are discussed.
U6 is an 8259, Interrupt Controller. Since we use only one Interrupt Request line of the 80C188 and have
many (8) interrupts to handle, we have an 8259 to prioritize the Interrupt operations. The 8259 allows the
80C188 to dynamically assign priorities to the 8 possible interrupt sources.
XU20 is a single channel UART. Its inputs and outputs are TTL levels. These TTL levels are converted to
+ and - voltage levels by U32, the MAX232CPE. The MAX232 generates its own RS232 + and - voltages
for the serial I/O channel.

PAGE 6
U15 is an 8-bit latch that interface to the EEPROMs on page 4. This is readable by selecting U16 to read
both U15 and the data from the EEPROMs.
U14 is an 8-bit latch that drives the 7-segment status LED on the board. U7 is an 8-bit buffer to read the
status of the MAX791 and the EEPROMs.
U8 and U9 read and write to eight of the Sound Section data bits (SD08 through SD15). U29 performs
Sound Interrupt operations.

PAGE 7
U17, U18, U30 and U31 are EPROMs that contain patterns that generate our Sounds. U38, U39 and U40
are RAMS that contain the sounds presently being executed. To present a sound the patterns from the
EPROMs (that have an access time of around 120 ns) are moved to the SRAMs (which have an access time
of 35 ns). These come out of XU35 (ADSP-2105KP-40) as digitized analog signals, DACDAT (DAC
Data), DACTRB (DAC Strobe) and DACCLK (DAC Clock). and feed to the I/O board, U39 on page 11 of
drawing A18886-01, where they are converted to analog signals and amplified.

Video signals come from the Daughter Board. That, like the I/O board, is another article in itself.

Herschel