UNIT III ANALOG MULTIPLIER AND PLL

Analog Multiplier using Emitter Coupled Transistor Pair - Gilbert Multiplier

cell – Variable Trans conductance technique, analog multiplier ICs and their
applications, Operation of the basic PLL, Closed loop analysis, Voltage controlled
oscillator, Monolithic PLL IC 565, application of PLL for AM detection, FM
detection, FSK modulation and demodulation and Frequency synthesizing.

UNIT- III
LINEAR INTEGRATED CIRCUITS SCE/DEPT.OF ECE/II YEAR Page 1
 ANALOG MULTIPLIER AND PLL

1. Define capture range of PLL [April/MAY 2008], [May/June 2010], [April/May 2011]
The range of frequencies over which the PLL can acquire lock with an input signal
is called the capture range. It is expressed as a percentage of the VCO free running
frequency.

2. Define lock-in range of a PLL. [April/MAY 2008],[Nov/Dec 2007] , [Nov/Dec 2008]

The range of frequencies over which the PLL can maintain lock with the incoming signal
is called the lock-in range or tracking range. It is expressed as a percentage of theVCO free
running frequency.

3. Mention some typical applications of PLL? [Nov/Dec 2008], [April/May 2011]

• Frequency multiplication/division
• Frequency translation
• AM detection
• FM demodulation
• FSK demodulation.
3. What is analog multiplier? [MAY 2007]
A multiplier produces an output v0, which is proportional to the product of two inputs vx
and vy
V0= kvxvy

4. List out the various methods available for performing for analog multiplier.
[May/June 2010]
• Logarithmic summing technique
• Pulse height /width modulation technique
• Variable transconductance technique
• Multiplication using gilbert cell
• Multiplication technique using transconductance technique

5. What is Frequency synthesizer? [April/MAY 2008], [April/MAY 2011]

Frequency generators are of two types:

(i) Free running, in which the output can be tuned continuously, over a frequency range, by
mechanical or electronic methods.
(ii) Synthesizer, which has its output derived from a fixed frequency, highly stable oscillator,
and covers the range in a series of steps. Synthesizers are of two types:
(i) Direct type
(ii) Indirect Type
The direct synthesizer uses a stable crystal oscillator, followed by a series of harmonic
multipliers and mixers, to provide the range of different output

6. Draw the circuit of Am detector Using PLL? [April/MAY 2008]

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 Demodulation or detection is the process of recovering a modulating signal Em from
the modulated output voltage V0.

7. List the application of analog multipliers? [Nov/Dec 2007]

There are a number of applications of analog multiplier such as,

(i) Frequency doubling
(ii) Frequency shifting
(iii) Phase angle detection
(iv) Multiplying two signals
(v) Dividing and squaring of signals.
(vi) Power measurement
(vii) Taking the square root of a signal
(viii) Designing non linear signal conditioning circuits

8. What is phase locked loop PLL? [Nov/Dec 2006]

Phased locked loop is one of the fundamental building blocks in electronic technology. These
arc used in FM, motor speed controls, filters, FM demodulators, etc. Examples of single
package PLL are Signctics SE/NE 560 scries,
9. What is a compander Ic ?enlist the features? [Nov/Dec 2006]

The term companding means compressing and expanding. In a communication system,

the audio signal is compressed in the transmitter and expanded in the receiver. Examples : LM
2704- LM 2707 ; NE 570/571.

10. Define Pull-in time. [April/May 2011]

The total time taken by the PLL to establish lok is called pull-in time.It depends on
the
initial phase and frequency difference between the two signals as well as on the overall loop gain
and loop filter characteristics

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20.What is a two quadrant Multiplies? [Nov/Dec 2006]

If one of the inputs is held positive and the other is allowed to swing both positive and negative it
is called two quadrant multiplies.

21. What are the three stages through which PLL operates? [Nov/Dec 2010]

1. Free running
2. Capture
3. Locked/ tracking

22. Define FSK modulation? [Nov/Dec 2011]

FSK is a type of frequency modulation, in which the binary data or code is transmitted
by means of a carrier frequency that is shifted between two fixed frequency namely mark
(logic1) and space frequency (logic 0).

23. What is the purpose of having a low pass filter in PLL? [Nov/Dec 2010]
*It removes the high frequency components and noise.
*Controls the dynamic characteristics of the PLL such as capture range, lock-in range,
band- width and transient response.
*The charge on the filter capacitor gives a short- time memory to the PLL

24. What is a filter? [April/May 2011]

Filter is a frequency selective circuit that passes signal of specified band of frequencies
and attenuates the signals of frequencies outside the band

25. List the basic building blocks of PLL:

1. Phase detector/comparator
2. Low pass filter
3. Error amplifier
4. Voltage controlled oscillator

26. List out the various methods available for performing for analog multiplier.
• Logarithmic summing technique
• Pulse height /width modulation technique
• Variable transconductance technique
• Multiplication using gilbert cell
• Multiplication technique using transconductance technique

27. Mention some areas where PLL is widely used. (DEC 2009)
1. Radar synchronizations
2. Satellite communication systems
3. Air borne navigational systems
4. FM communication systems
5. Computers.

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28. Write the expression for FSK modulation.(MAY 2010)
Pvf=f2-f1/k0

29. Define free running mode. (MAY 2010)

An interactive computer mode that allows more than one user to have simultaneous
use of a program.

30. for perfect lock, what should be the phase relation between the incoming signals
and VC Output signal?
The VCO output should be 90 degrees out of phase with respect to the input signal.

31. Give the classification of phase detector:

1. Analog phase detector.

2. Digital phase detector

32.What is a voltage controlled oscillator?

Voltage controlled oscillator is a free running multivibrator operating at a set frequency
called the free running frequency.This frequency can be shifted to either side by applying a dc
control voltage and the frequency deviation is proportional to the dc control voltage.

33. Define Voltage to Frequency conversion factor.

Voltage to Frequency conversion factor is defined as,
Kv = fo / Vc= 8fo /Vcc
Vc is the modulation voltage
fo frequency shift

34. What are the merits of companding?

*The compression process reduces the dynamic range of the signal before it is
transmitted.
*Companding preserves the signal to noise ratio of the original signal and avoids non
linear distortion of the signal when the input amplitude is large.
*It also reduces buzz,bias and low level audio tones caused by mild interference.

35. Mention some areas where PLL is widely used.

* Radar synchronization
* Satellite communication systems
* Air borne navigational systems
* FM communication systems
* Computers.
36. What is a voltage controlled oscillator
Voltage controlled oscillator is a free running multivibrator operating at a set
frequency called the free running frequency. This frequency can be shifted to either side by
applying a dc control voltage and the frequency deviation is proportional to the dc

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control voltage.
37. On what parameters does the free running frequency of VCO depend on?
*External timing resistor, RT
*External timing capacitor, CT
*The dc control voltage Vc.

38. Define Voltage to Frequency conversion factor.

Voltage to Frequency conversion factor is defined as,
.Y Io9c= 8fo /Vcc
9c is the modulation voltage required to pro

39. List the applications of OTA:

OTA can be used in
 Programmable gain voltage amplifier
 sample and hold circuits
 Voltage controlled state variable filter
 Current controlled relaxation oscillator.

40. A PLL has free running frequency of 500 kHz and bandwidth of LPF is 10 kHz.
Will the lop acquire lock for an input signal of 600 kHz. Justify Assume that phase
detector produces and difference frequency components.

Solution: Phase detector output,

⇒ f i +f c
= 600 kHz + 500 kHz

= 1100 kHz.

⇒ f i−f c =600 kHz−500 kHz=100 kHz

As both the components are outside the pass band of low pass filter, the loop will to
acquire lock.

41. Draw the circuit diagram of a squaring circuit using multiplier? [Nov/Dec 2006]

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 UNIT-III

1. Explain the operation of a four quadrant multiplier? [NOV/DEC-2006] (16m)

The four quadrant variable transconductane multiplies uses tow linearised

transconductance pairs with bases driven in antiphase. The emitters are driven by V-I
converters.

For a linearised transconductance multiplier circuit,

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 ( I 1 − I 2 )( I 3 + I 4 )
( I 3 −I 4 ) =
( I 1+ I 2) (1)

The output of the V-I converter is given by

2
( I 1−I 2) = R ( X 1 −X 2 )
X (2)

Substituting (2) in (1)

2 ( X 1− X 2 )
( I 1−I 2 ) = R X ( I 1+ I 2) ( 3 4 )
I +I
(3)

I 3 +I 4 =I 9 (5)

Substituting equation (4) & (5) in (3)

I 9 ( X 1 −X 2 )
( I 3 −I 4 ) = I X.RX
 (6)

Similarly,

I 5 +I 6=I 10
I 10 ( X 1 −X 2 )
I 6 −I 5 =
 I X . RX (7)

Transistors Q9 and Q10 form another V – I converter for which we can write,

2
I 10 −I 9 = ( Y −Y )
. RY 1 2 (8)

Subtracting (6) from (7) i,e (6) (7)

( I 10−I 9 )( X 1 −X 2 )
( I 4 + I 6 ) −( I 3 + I 5 ) = I X.RX
 (9)

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Substituting equation (8) in (9)

2 ( X 1− X 2 )( Y 1−Y 2 )
( I 4 + I 6 ) −( I 3 + I 5 ) = I X . R X . RY
 (10)

The Op-Amp A1 along with the third V-I converter of transistors Q 11 and Q12,
from the output I-V converter. The V – I converter of Q11 and Q12 si in the feedback path
of Op-amp Ai

Applying KVL we can write

V B =V CC −R L ( I 3 + I 5 + I 12)
(11)

V A =V CC −R L ( I 4 +I 6 +I 11 )
(12)

But for an Op-amp the two input terminals are always at same potential i.e. (V A = VB)

V CC −R L ( I 3 + I 5 + I 12 ) =V CC −R L ( I 4 + I 6 + I 11 )


I 3 + I 5 +I 12=I 4 + I 6 +I 11

 ( I 4 + I 6 ) −( I 3 + I 5 ) =I 12−I 11 (13)

As Q11 and Q12 form an another V-I converter.

2
I 12−I 11= ( Z −Z )
Rz 1 2 (14)

Substituting equations (10) & (14) in (13)

2 ( Z 1−Z 2 ) 2 ( X 1 − X 2 )( Y 1 −Y 2 )
=
Rz I X R X RY

Rz
Z 1 −Z2 =
I X R X RY ( X 1− X 2 )( Y 1−Y 2 )


 ( Z 1−Z 2 ) =K ( X 1 −X 2 )( Y 1 −Y 2 ) (15)

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 where,

Rz
K=
IX RX RY

( 1
)
generally K is selected as 10 . Equation (15) shows that the circuit worked as
Four Quadrant Multiplies.

So let,

V 1 =X 1 −X 2

V 2 =Y 1−Y 2

V 0 =Z 1 −Z 2

V 0=K .V 1 .V 2

2. Explain the working of phase locked loop?

[NOV/DEC-2006] , [APR/MAY-2008], [APR/MAY-2011]
or
Draw the block diagram of a PLL and derive its transfer function? [MAY/JUNE-2007]
[MAY/JUNE-2012]

A phase Locked Loop (PLL) is a frequency selective circuit designed to synchronise (lock) with
an incoming signal and maintain the synchronization (locked state ) inspite of noise or variations
in the input signals. The basic PLL system comprises a phase detector, Loop filter, error
amplifier and voltage controlled oscillator (VCO)

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 The phase detector compares the phase of input frequency (f s) and feedback
frequency (f0) and generates output signal which is a function of difference between the two
phase values.

The output of phase detector is filtered to remove the high frequency noise from d.c
voltage

The output of the filter, called the error voltage or control voltage for VCO is fed into the
VCO. When control voltage is zero, VCO is in free –running mode and its output is called
center frequency, f0

Non – zero control voltage results in a shift in VCO frequency from f 0 to a frequency f ,
given by

f =f 0 +K v V c
where

KV  Voltage to frequency transfer coefficient of VCO.

The error voltage, VE forces the VCO to change its output frequency in the direction that
reduces the difference between the i/p and o/p frequency of VCO.

This action is called capture process it continues till the output frequency of VCO is
same as i/p signal frequency i.e

Fs = f0

When fs = f0, the system is said to be locked. In locked condition, phase detector
generates a d.c signal which is required to shift the output frequency of VCO from centre
frequency to input frequency.

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 Once locked, PLL tracks the frequency changes of input signal. Thus PLL goes through
three stages of operation free running, capture and lock in or tracking range.

Capture range.

The range of frequencies over which the PLL can maintain lock with the incoming signal is
o the VCO
called as lock – I range or tracking range. It is expressed as a percentage of f
f0
Δf L =±7 .8
frequency V

Lock In Range.

The range of frequencies over which the PLL can acquire lock with an input signal is called
capture range of the PLL

Δf c≈±√ f 1 . Δf L

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 The vertical axis is the error voltage and horizontal axis is the input frequency varied
over broad frequency range.

As input frequency is increased, the PLL responds only when frequency reaches f1,
which is the lower edge of the capture range.

Now PLL locks the input frequency and causes negative jump of error voltage is shift the
output frequency of VCO.

As input frequency is further increased, at fs = f0, the error voltage is zero.

If f s is increased f2 which is the upper edge of lock range.

After that PLL loses lock and error voltage drops to zero. If input frequency is reduced
slowly the cycle repeats as shown in fig.

(ii)Now PLL recaptures at f3 and tracks it up to f4 where f3 is the upper edge of capture range
and f4 is lower edge of lock range.

The frequency range between f1 and f3 is called capture range (2fc) and frequency range
between f2 and f4 is called lock or tracking range (2fL) generally lock range is greater than
capture range.

3. Draw and Explain FM Demodulation using PLL?

[MAY/JUNE 2007], [Nov/Dec 2006]

FM Demodulation using PLL:

 The three main components of the FM detection system are voltage controlled oscillator
(VCO) , Loop filter and phase detector.

 In most PLL ICS, VCO and phase comparator are on chip and external terminals are
provided for connecting loop filter.
φ
 Assume that input signal contains modulated angel function i (t), which represents
some intelligence signal to be extracted by PLL.
 This input signal and output of VCO are both applied as inputs to the phase comparator.
 Sine function is assumed for input and cosine function for VCO output 90 0 phase
difference is assumed between these two inputs of phase detector.

 Initially, assume that there is no modulation i.e,

φi ( t )=0 . Assume VCO frequency
with no input voltage is c

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  Now the input and VCO output are sinusoids of frequency c, but with phase difference

of 90o. The phase comparator and lop filter outputs are

v e ( t )=0 and
v 0 (t )=0 .
Thus loop is locked in equilibrium state.

 Next assume some intelligence signal

φi ( t ) appear in input. Thus the two inputs of

phase comparator have different frequencies and phases and an error voltage
ve ( t )
appears.

 This voltage is smoothed by loop filter to produce e

v ( t ) and then applied as VCO
input.
 This control signal causes the VCO frequency to shift in a direction that causes VCO
frequency to match that of input, thus reducing loop “error” towards zero.
 Feedback structure of the loop forces VCO to generate same FM signal that was
generated back at the transmitter.

 Thus VC control voltage e

v ( t ) assume the same form as at the transmitter and the
intelligence“ has been extracted.

 This loop coupled with FM process offers significant reduction in noise, so a “clean”
version of modulating signal is extracted.

4. With the block diagram discuss the principle of operation of NE 565 PLL circuit?
[NOV/DEC-2006] (8m)

BLOCK DIAGRAM FO IC 565 PLL

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  As shown in block diagram, the PLL is not internally connected so output of VCO (pin
4) and phase comparator input (pin 5) are connected externally.
 The centre frequency of PLL is determined free running frequency of VCO given by

1. 2 0.3
f 0= Hz= Hz
ΔR 1 C 1 R 1C 1 (4)

where R1 & C1 are external components connected to pi 8 and 9 respectively.

 The value of R1 and C1 are adjusted such that the free running frequency will be at the
center of input frequency range.
 The capacitor C2 controlled between pin 7 and 10 appears as a portion of loop filter. It s
value should be large to eliminate oscillations in VCO output.
 The lock range f2 is given by

±8 f 0
f L= Hz . ……………………… (B)
V
where

V =( +V )−(−V ) in volts.

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 And the capture range fc is given by

[ ]
1/ 2
fL
f c=±
2 π ( 3 . 6 ) ( 103 ) ( C2 )
……………………… (C)

 The lock range increases with an increase in input voltage but decreases with increase in
supply voltage.
 The two inputs, to phase detector (pin 2 and 3) allows direct coupling of an input signal,
provided there is no dc voltage difference between the pins
 A reference voltage at pin 6 is approximately equal to dc. Voltage of demodulated output
at pin 7
 This reference voltage may be used as comparator input in FSK demodulator application.

PIN DIAGRAM

5. Explain PLL as a Frequency synthesizer?

[NOV/DEC-2006], [APR/MAY-2008], [APR/MAY-2011]
or
Write notes on frequency synthesizer?
[NOV/DEC-2011], [APR/MAY-2008], [NOV/DEC-2008], [APR/MAY-2012]

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  Reference Oscillator uses a crystal to generate a frequency of suitable accuracy and
stability (fosc). Reference counter reduces the fosc to the value needed for fR
 A “Frequency Synthesizer” is a device that generates a large number of precise
frequencies from a single frequency. The principle of indirect frequency synthesizer is as
follows.
 When a PLL is working properly, the two phase detector input frequencies are equal.
Hence
f R =f D (1)

 The frequency, fD is obtained by dividing VCO output frequency by N. Hence

f0
f D=
N (2)

Equating (1) & (2)

f0
f R =f D=
N (A)


f 0=Nf R

 Thus frequency divides in the loop thus provides a method for obtaining a large number
of frequencies form a single frequency.
 Frequency synthesis can also be obtained by using PLL in its harmonic locking mode.

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 If the input is rich in harmonic then VCO can be locked to the n th - harmonic of input directly
without connecting any frequency divider.
 Effective locking may not lake place for higher values of n, as their amplitude decreases as ‘n’
increases. Typically n is less than 10
 If the divider ratio N is realized using a programmable divider,, it is possible to easily change
the output frequency is increments of fR.

6. With neat circuit diagram Explain the working of a NE/SE 566 voltage controlled
oscillator? [NOV/DEC-2006]
or
Explain the voltage controlled oscillator with its block diagram and connection diagram using VCO
IC 566? [Apr/May-2008], [NOV/DEC-2011]
or
Explain the VCO with suitable waveforms? [Nov/Dec-2008]

 A voltage controlled oscillator is a oscillator ckt in which the frequency of oscillation is

controlled by externally applied voltage called control voltage.
 This ckt is also called voltage to frequency converter
 From block diagram, timing capacitor, CT is changed and discharged linearly by a constant
current source.
 The current value can be controlled by either by changing the control voltage given at the
modulating input (pin 5) or by changing the timing resistor (RT) connected to pin 6.
 If control voltage at pin 5 in increased, the voltage at pin 6 also increases resulting in less
voltage across RT and thereby decreasing the changing current.
 The voltage across capacitor CT is applied to (-) terminal of schemit trigger (A z ) via buffer
(A1)

Block diagram:

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  The output of schemit trigger is designed to swing between 0.5Vcc and Vcc . The
voltage at (+) terminal of schemit trigger swings between 0.25 Vcc and 0.5 Vcc.
 When capacitor voltage exceeds 0.5 Vcc, output of schemitt trigger goes LOW (0.5Vcc)
and capacitor starts discharging.
 When capacitor voltage discharges to 0.25 Vcc, the output of Schmitt trigger goes H/GH
(+Vcc)
 Since source and sink currents are equal, capacitor charging and discharging time are
equal so the output at pin 3 is a triangular waveform.

TYPICAL CONNECTION DIAGRAM:

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Waveform for VCO:

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  The square wave output of Schmitt trigger is inverted by A3 and available at pin 3.
 Total voltage on capacitor changes from 0.25 Vcc to 0.5 Vcc. Hence
ΔV =0 .25V cc . The capacitor changes with constant current source

Δv i
=

Δt CT

0. 25 V cc i
=

Δt CT
T
0 . 25V cc . C
Δt=
 i (1)

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 The frequency of oscillation (f0) is

1 1 1 i
f 0= = =
T 2 Δt 2 0. 25 V cc .C T from (1)

i
f 0=

0 . 5V cc . CT (2)

V cc−v c
i=
but
RT (3)

( V cc−v c )
f 0=

0 . 5V cc RT C T using (3) in (2)


2 ( V cc −v c )
f 0=
V cc R T C T
(4)

The control voltage (v1) is varied by voltage divider R1 & R2 . With no modulating signal if pin 5 is
biased at (7/8 Vcc), the frequency of oscillation is

0. 25
f 0=
RT C T
Voltage to freque3ncyconversion factor K v is defined as

Δf 0 8.f 0
KV= =
ΔV c V cc

Where

Δf 0 ⇒ f 1−f 0 , frequency shift produced by change in modulating voltage ΔV c

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 APPLICATIONS:

Signal generation, FM modulation, FSK demodulator. Frequency multipliers.

7. With neat circuit diagram Explain the working of variable transconductance multiplier? What is
limitation? [MAY/JUNE-2011], [APR/MAY-2008]
or
Write short notes on variable transconductance multiplier? [APR/MAY-2007]
or
Explain the working principle of variable transconductance multiplier?
[MAY/JUNE -2009] [NOV/DEC-2010]

The differential output voltage Vz is given as

V z=g m . R L .V X (1)

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 I EE
gm=
i.e, VT (2)

where

gm  transconductance of the stage

VT  Thermal voltage

By applying second input Vy to reference source, gm can be varied.

V Y =I EE . R E (3) Sine
I CE R E >> V BE
Substituting (3) in (2)

V Y =R E ( g m V T )
 (4)

Substituting (4) in (1)

VY
REV T (
V z= RL V x )



V z=V X ;V Y
( )RL
REV T
(5)

Total current IEE varies as the function of VY

The disadvantage of the above circuit is common – mode shift which can be overcome
by using two differential stages in parallel and coupling their output as shown below

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 The two inputs Vx and VY determine the division of total current IEE among different
branches of the circuit.

Assume all the transistors are well matched, therefore

I 1 +I 2 =I 5

I 3 +I 4 =I 6 (6)

I 5 +I 6=I EE

Assuming
|V X|<<V T , the current imbalance in T - T2 & T3 - T4 can be given by,
1

1
I 1 −I 2 =g m V x (7)

11
&
I 3 −I 4 =−g m V x (8)

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where,

1 11
gm and
gm are transconductance of transistor pairs (T2 - T1) and (T3 – T4)
respectively.

Also,

I5 I6
g1m= ∧¿ ¿ g11
m=
VT VT (9)

The total differential output voltage, Vz is,

V z=R L [ ( I 1 −I 2 ) + ( I 3 −I 4 ) ]
(10)

Substituting (7) & (8) in (10)

V z=R L [ g1m .V X −g11

m .V X ]

V z=R L V X [ g1m .−g11

m]
 (11)

Substituting (9) in (11)


Vz=R L V X
[ I5
VT
−
I6
VT ]
RLV X
=
VT
[ I5−I 6 ]
(12)

If RE is chosen very large, such that

I 6 R E >> V T and
I 5 R E >>V T

VY
( I 5 −I 6 )= RE
Hence (13)

Substitute (13) in (12)

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 
V Z =V X . V Y
( )
RL
VT
(A)

DISADVANTAGE:

This circuit is limited for linear applications,. This is because V Z equation is valid only

for limited values of Vx i.e,

|V X|<V T . Thus VX cannot be more than several millivolts.

However, if VX is comparable to VT then the ckt worked in non-linear range and this is
useful in switching applications like balanced modulator

FEATURES:

It is cheaper and ahs good accuracy.

It is easy to integrate into chip.

It is available in four – quadrant operation.

High speed of operation

Bandwidth of 10 MHz and higher are available.

8. Draw the circuit of a FM demodulator using PLL?

[MAY/JUNE-2007],[MAY/JUNE-2012]

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  The three main components of the FM detection system are voltage controlled oscillator
(VCO) , Loop filter and phase detector.
 In most PLL ICS, VCO and phase comparator are on chip and external terminals are
provided for connecting loop filter.
φ
 Assume that input signal contains modulated angel function i (t), which represents
some intelligence signal to be extracted by PLL.
 This input signal and output of VCO are both applied as inputs to the phase comparator.
 Sine function is assumed for input and cosine function for VCO output 90 0 phase
differences is assumed between these two inputs of phase detector.

 Initially, assume that there is no modulation i.e, i φ ( t )=0

. Assume VCO frequency
with no input voltage is c
 Now the input and VCO output are sinusoids of frequency c, but with phase difference

of 90o. The phase comparator and lop filter outputs are

v e ( t )=0 v (t )=0 .
and 0
Thus loop is locked in equilibrium state.

 Next assume some intelligence signal

φi ( t ) appear in input. Thus the two inputs of

phase comparator have different frequencies and phases and an error voltage
ve ( t )
appears.

 This voltage is smoothed by loop filter to produce e

v ( t ) and then applied as VCO
input.
 This control signal causes the VCO frequency to shift in a direction that causes VCO
frequency to match that of input, thus reducing loop “error” towards zero.

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  Feedback structure of the loop forces VCO to generate same FM signal that was
generated back at the transmitter.

 Thus VC control voltage e

v ( t ) assume the same form as at the transmitter and the
intelligence“ has been extracted.
 This loop coupled with FM process offers significant reduction in noise, so a “clean”
version of modulating signal is extracted.

9. Explain PLL used as an AM detection?

[MAY/JUNE-2008], [MAY/JUNE-2011], [MAY/JUNE-2012]

BLOCK DIAGRAM OF AM DETECTOR:

 The PLL can be used a coherent detector for demodulating AM signal.

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  Consider a AM signal given by
S ( t )=V [ 1+m ( t ) ] Sin ωc t
 This scan be demodulated by multiplying the signal by a local oscillator signal of same
carries frequency. The multiplies output is

V ( t )=V [ 1+m ( t ) ] Sin ωc t . ASin ( ω c t +θ )

V ( t )=V [ 1+m ( t ) ]
[ Cosθ−Cos ( 2 ωc t +θ ) ]
2 (1)

 Thus the multiplies output consists of low frequency modulating signal.

V [ 1+m ( t ) ] Cos θ and modulating signal centered about twice the carrier frequency , i.e

V [1+ m ( t ) ] Cos ( 2 ω c t +θ )

 The high frequency term is removed by LPF, whose output is

V 0 ( t )=V [ 1+m ( t ) ] . Cos θ

V 0 ( t )=V [ 1+ m ( t ) ] . Cos θ
(A)

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 Te local oscillator signal, phase locked to input carrier can be generated by a PLL. A
complete AM demodulator is shown below

 The PLL locks with carrier of AM input signal so that output of VCO has same
frequency as that of carrier but no amplitude modulation.
 When the VCO signal is multiplied with AM signal, the demodulated output is obtained
after filtering the high frequency components using a LPF.
 The VCO output signal is 90o out of phase with input signal under lock condition. So 90o
phase shift is repaired before applying the input signal to the multiplier.

 The average value of

V (t )
0 is directly proportional to the amplitude of the input
signal.
 Since PLL responds only to carrier frequency vary close to VCO frequency the phase
locked AM detector provides high degree of selectivity.
 Also this system provider high degree of noise immunity.

10. Write a short notes on FSK Modulator and Demodulator?[ APR/MAY-2008]

or
Explain the working of PLL as FSK demodulator? [NOV/DEC-2007]

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  Frequency shift keying (FSK) is a type of frequency modulation in which the
frequency of the FM signal is varied between tow fixed levels.
 This is similar to binary data transmission system in which one of the frequency level
represents a ‘o’ and other frequency level f2 represents a 1‘
 The ‘O’ to - ‘1’ frequency deviation f being
Δf =f 2−f 1 (1)

BLOCK DIAGRAM:

FSK/AFSK Modulator:

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 Audio frequency-shift keying (AFSK) is a modulation technique by which digital data is
represented by changes in the frequency (pitch) of an audio tone, yielding an encoded signal
suitable for transmission via radio or telephone.

Normally, the transmitted audio alternates between two tones: one, the “mark”,
represents a binary one; the other, the “space”, represents a binary zero.

The need for a compact telemetry system represents a challenge design for a small,
lightweight, low component count.

Connection to serial data is of the microprocessor also difficult because most Low-cost
RF transmitters do not accept dc levels at the entrance.Commercial FSK (frequency-Shift-
keying) modulators are bulky and need many Passive components.

The circuit uses a single NOT gate (inverter), On Semiconductor NL27WZ14 into a
surface mount Package, to generate continuous FSK data from the TTL level signals.

The Spending of this range are compatible with the available channels. If the TTL input
is low, the circuit is a continuous execution of the oscillator output about 2400 Hz (adjustable
with R1).

If the input assumes a high level of the oscillator frequency reduces by half with the
Introduction of a capacitor in the circuit over time Q1.

Converter IC provides space for surgical Frequency of approximately 80 kHz. You can
easily Operation of the FSK modulator at higher frequencies e.g., 4800 and 9600 Hz, by
reducing the values of the timing capacitors C1 and C2.

BLOCK DIAGRAM:

 FSK demodulator shown above is similar to FM demodulator except for the addition of a
comparator (comp) to produce a reconstructed digital output signal.

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  If the PLL remains locked into the FSK signal at both f 1 and f2 the VCO control voltage
which is also supplied to the comparator will be given by,
f 1 −f 0
V f 1=
Kv (2)

f 2 −f 0
V f 2=
Kv (3)

where,

KV - Voltage to frequency transfer coefficient of VCO.

 The difference between two control voltage levels will be

ΔV f =V f 2−V f 1 (2) - (3)

( f 2 −f 0 ) ( f 1−f 0 )
= −
Kv Kv


f 2−f 1
ΔV f = (A)
Kv

Δf
ΔV f = (B) Using (1)
Kv

 The reference voltage for comparator is received from VCO control voltage applied
through a Low pass filter (LPF2)
 The LPF 2 has very long time constant compared to FSK pulse period such that an
essentially dc voltage is obtained.
 This d.c voltage will have level that is midway between Vf 1 and Vf2, thus producing
minimum bit error rate.

LINEAR INTEGRATED CIRCUITS SCE/DEPT.OF ECE/II YEAR Page 34

 11. Explain how a frequency multiplication is done using PLL? [MAY/JUNE-2008]

or
With block diagram explain how PLL can be used as frequency multiplier circuit?
[MAY/JUNE-2009]

Frequency Multiplier:

Working Of The System:

For the working of Frequency multiplier circuit the frequency divider is inserted between
the VCO and phase comparator.

Since the output of the divider is locked into the input frequency fIN, the VCO is actually
running at a multiple of the input frequency.

The desired amount of multiplication can be obtained by selecting a proper divide-by-N

network, where N is an integer. For example, to obtain the output frequency f OUT = 5fIN, a divide-
by-N = 5 network is needed.

Figure 1-1 shows the function performed by a 7490 (4-bit binary counter) configured as a
divide-by-5 circuit. In this figure, transistor Q1 is used as a driver stage to increase the driving
capability of the NE565.

Circuit Description of frequency multiplier:

To verify the operation of the circuit frequency multiplier, one must determine the input
frequency range and then adjust the free-running frequency f OUT of the VCO by mean of R 1 and
C1 so that the output frequency of the 7490 divider is midway within the predetermined input
frequency range. The output of the VCO now should be 5fIN.

The output frequency fOUT can be adjusted from 1.5 KHz to 15 KHz by varying
potentiometer R1 (fOUT = 1.2/4R1C1).

This means that the input frequency f IN range has to be within 300 Hz to 3 KHz. In
addition, the input waveform can either be sine or square wave and may be applied to input pin 2
or 3.

Even though supply voltages of ±10 V are used in figure 1-1, the NE565 can be operated
on ±5 supply voltage instead.

A small capacitor C3 typically 1000pF, is connected between pins 7 and 8 to eliminate

possible oscillations. Also, capacitor C2 should be large enough to stabilize the VCO frequency.

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Frequency multiplier:

In electronics, a frequency multiplier is an electronic circuit that generates an output

signal whose output frequency is a harmonic (multiple) of its input frequency.

Frequency multipliers consist of a nonlinear circuit that distorts the input signal and
consequently generates harmonics of the input signal.

A subsequent band pass filter selects the desired harmonic frequency and removes the
unwanted fundamental and other harmonics from the output.

Frequency multipliers are often used in frequency synthesizers and communications

circuits.

It can be more economical to develop a lower frequency signal with lower power and
less expensive devices, and then use a frequency multiplier chain to generate an output
frequency in the microwave or millimeter wave range.

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 Some modulation schemes, such as frequency modulation, survive the nonlinear
distortion without ill effect (but schemes such as amplitude modulation do not).

Frequency multiplication is also used in nonlinear optics. The nonlinear distortion in

crystals can be used to generate harmonics of laser light.

THEORY:

A pure sine wave at frequency f has no harmonics. If it goes through a linear amplifier,
the result continues to be pure (but may acquire a phase shift).

If the sine wave is run through a stateless nonlinear circuit (transcribing function), the
resulting distortion creates harmonics. The distorted signal can be described by a Fourier series
in f.

The nonzero ck represent the generated harmonics. The Fourier coefficients are given by
integrating over the fundamental period T:

These harmonics can be selected by a band pass filter.

The power in the distorted signal is spread across all the resulting harmonics. An ideal
half wave rectifier, for example, has all nonzero coefficients. An approximate circuit could use a
diode.

From a conversion efficiency standpoint, the nonlinear circuit should maximize the
coefficient for the desired harmonic and minimize the others. Consequently, the transcribing
function is often specially chosen.

Easy choices are to use an even function to generate even harmonics or an odd function
to for odd harmonics.

See Even and odd functions Harmonics. A full wave rectifier, for example, is good for
making a doubler.

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 To produce a times-3 multiplier, the original signal may be input to an amplifier that is
over driven to produce nearly a square wave.

This signal is high in 3rd order harmonics and can be filtered to produce the desired x3
outcome.

YIG multipliers often want to select an arbitrary harmonic, so they use a stateful
distortion circuit that converts the input sine wave into an approximate impulse train.

The ideal (but impractical) impulse train generates an infinite number of (weak)
harmonics.

In practice, an impulse train generated by a monostable circuit will have many usable
harmonics.

YIG multipliers using step recovery diodes may, for example, take an input frequency of
1 to 2 GHz and produce outputs up to 18 GHz.

Sometimes the frequency multiplier circuit will adjust the width of the impulses to
improve conversion efficiency for a specific harmonic.

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