Reloj 24 Hrs VHDL 6 displays con alarma configurable

Código VHDL

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-- Company:
-- Engineer:
--
-- Create Date: 23:51:23 11/14/2020
-- Design Name:
-- Module Name: reloj - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity reloj is
Port ( clk : in STD_LOGIC;
resetT: in STD_LOGIC;
resetm: in STD_LOGIC;
 reseth: in STD_LOGIC;
configh: in STD_LOGIC;
configm: in STD_LOGIC;
aceptar: in STD_LOGIC;

alm1: out STD_LOGIC;

alm2: out STD_LOGIC;
alm3: out STD_LOGIC;
alm4: out STD_LOGIC;
alm5: out STD_LOGIC;
alm6: out STD_LOGIC;
alm7: out STD_LOGIC;

almh1: out STD_LOGIC;

almh2: out STD_LOGIC;
almh3: out STD_LOGIC;
almh4: out STD_LOGIC;
almh5: out STD_LOGIC;
almh6: out STD_LOGIC;
ALARMA: out STD_LOGIC;

q1 : out STD_LOGIC;
q2 : out STD_LOGIC;
q3 : out STD_LOGIC;
q4 : out STD_LOGIC;
j1 : out STD_LOGIC;
j2 : out STD_LOGIC;
j3 : out STD_LOGIC;
m1 : out STD_LOGIC;
m2 : out STD_LOGIC;
m3 : out STD_LOGIC;
m4 : out STD_LOGIC;
f1 : out STD_LOGIC;
f2 : out STD_LOGIC;
f3 : out STD_LOGIC;
g1 : out STD_LOGIC;
g2 : out STD_LOGIC;
g3 : out STD_LOGIC;
g4 : out STD_LOGIC;
h1 : out STD_LOGIC;
h2 : out STD_LOGIC);
end reloj;

architecture Behavioral of reloj is

signal salida : STD_LOGIC_VECTOR(3 downto 0);
signal Bout : STD_LOGIC_VECTOR(2 downto 0);
signal Cout : STD_LOGIC_VECTOR(3 downto 0);
signal Dout : STD_LOGIC_VECTOR(2 downto 0);
signal Eout : STD_LOGIC_VECTOR(3 downto 0);
signal Fout : STD_LOGIC_VECTOR(1 downto 0);
signal Gout : STD_LOGIC_VECTOR(3 downto 0);
signal Hout : STD_LOGIC_VECTOR(2 downto 0);
signal Iout : STD_LOGIC_VECTOR(3 downto 0);
signal Jout : STD_LOGIC_VECTOR(1 downto 0);

signal contador : integer range 0 to 15 :=0;

signal cont : integer range 0 to 7 :=0;
signal cont2 : integer range 0 to 15 :=0;
signal cont3 : integer range 0 to 7 :=0;
signal cont4 : integer range 0 to 15 :=0;
signal cont5 : integer range 0 to 3 :=0;
signal cont6 : integer range 0 to 15 :=0;
signal cont7 : integer range 0 to 7 :=0;
signal cont8 : integer range 0 to 15 :=0;
signal cont9 : integer range 0 to 3 :=0;

begin

process (clk)
begin

if resetT = '1' then

contador <= 0;
cont <= 0;
cont2 <= 0;
cont3 <= 0;
cont4 <= 0;
cont5 <= 0;
end if;

if resetm = '1' then

cont2 <= 0;
cont3 <= 0;
end if;

if reseth = '1' then

cont4 <= 0;
cont5 <= 0;
end if;

if configm = '1' then

cont7 <= cont7 + 1;
if cont7 = 5 then
cont7 <= 0;
end if;
end if;

if configh = '1' then

cont8 <= cont8 + 1;

if cont9 = 2 and cont8 = 3 then
cont8 <= 0;
cont9 <= 0;
end if;
if cont8 = 9 then
cont8 <= 0;
cont9 <=cont9 + 1;
end if;

end if;

If cont7 = cont3 and cont8 = cont4 and cont9 = cont5 and configh=
'0' and configm= '0' and aceptar= '1' then
ALARMA <= '1';
end if;

if aceptar = '0' then

ALARMA <= '0';
end if;

if rising_edge(clk) then
 contador <= contador + 1;
if contador = 9 then
contador <= 0;
cont <= cont + 1;
if cont = 5 then
cont <= 0;
If cont = 5 and contador = 9 then
cont2<= cont2 + 1;
if cont2 = 9 then
cont2 <= 0;
cont3 <= cont3 + 1;
if cont3 = 5 then
cont3 <= 0;

if cont3 = 5 and cont2 = 9 then

cont4 <= cont4 + 1;

if cont5 = 2 and cont4 = 3 then

cont4 <= 0;
cont5 <= 0;
end if;

if cont4 = 9 then
cont5<= cont5 + 1;
cont4 <= 0;
end if;

end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
salida <= CONV_STD_LOGIC_VECTOR(contador,4);
Bout <= CONV_STD_LOGIC_VECTOR(cont,3);
Cout<= CONV_STD_LOGIC_VECTOR(cont2,4);
Dout<= CONV_STD_LOGIC_VECTOR(cont3,3);
Eout<= CONV_STD_LOGIC_VECTOR(cont4,4);
Fout<= CONV_STD_LOGIC_VECTOR(cont5,2);
Gout<= CONV_STD_LOGIC_VECTOR(cont6,4);
Hout<= CONV_STD_LOGIC_VECTOR(cont7,3);
Iout<= CONV_STD_LOGIC_VECTOR(cont8,4);
Jout<= CONV_STD_LOGIC_VECTOR(cont9,2);

q1<= salida(0);
q2<= salida(1);
q3<= salida(2);
q4<= salida(3);

j1<= Bout(0);
j2<= Bout(1);
j3<= Bout(2);

m1<= Cout(0);
m2<= Cout(1);
m3<= Cout(2);
m4<= Cout(3);

f1<= Dout(0);
f2<= Dout(1);
f3<= Dout(2);

g1<= Eout(0);
g2<= Eout(1);
g3<= Eout(2);
g4<= Eout(3);

h1<= Fout(0);
h2<= Fout(1);

alm1<= Gout(0);
alm2<= Gout(1);
alm3<= Gout(2);
alm4<= Gout(3);
alm5<= Hout(0);
alm6<= Hout(1);
alm7<= Hout(2);

almh1<= Iout(0);
almh2<= Iout(1);
almh3<= Iout(2);
almh4<= Iout(3);

almh5<= Jout(0);
almh6<= Jout(1);

end Behavioral;