SRM INTERNATIONAL JOURNAL Vol-4 Number-1 Sep-2016 Page No-01-05
6-BIT ARRAY MULTIPLIER FOR HIGH SPEED
COMPUTATION USING VHDL
J. P. N. Verma, Aditya Agarwal, Ajay Kumar
Jpnverma2@gmail.com, aditya.electrobond@gmail.com, ajayku87@gmail.com
Assistant Professor, Department of Electronics & Communication Engineerng
SRM University, NCR Campus, Ghaziabad, India.
Abstract
High speed multiplication has always been
a fundamental requirement of high
performance processors and
systems.Multiplier is one of the basic
functional units in Microprocessors and
DSPs and also a major source of power
dissipation. Most high performance DSP
systems rely on hardware multiplication to
achieve high data rates. With technological
advances there is a need for design and
development of high speed data path
operators such as adders and multipliers to
perform signal processing operations at
very high speed supporting higher data
rates. In many applications, multiplication
is one of the most utilized arithmetic
operations as part of filters and transforms
processors[5]. In this paper a low power
and low area multiplier is proposed.
Reducing the power dissipation of
multipliers is a key to satisfy the overall
power budget of various digital circuits and
systems. The fundamental units to design a
multiplier are adders. Improving multipliers
design directly benefits the high
performance embedded processors used in
consumer and industrial electronic
products. Hence there is a need for design
and development of high-speed
architectures for N-bit multipliers
supporting high speed and power. Our
research efforts have been devoted to
reducing the power dissipation of different
multipliers. Here we review the architecture
reported in the literature for multipliers and
critical issues degrading the speed and
power of these multiplier. Based on this
review suitable modifications are suggested
in the design for high speed and low power
multipliers[6].
The multipliers presented in this paper were
all modelled using VHDL (Very High
Speed Integration Hardware Description
Language)
Keywords: — CPA, DSP, microprocessor,
multiplier.
Introduction
Multipliers play an important role in
today’s digital signal processing and
various other applications. With advances
in technology, many researchers have tried
and are trying to design multipliers which
offer either of the following design targets –
high speed, low power consumption,
regularity of layout and hence less area or
even combination of them in one multiplier
thus making them suitable for various high
speed, low power and compact VLSI
implementation.
Array multiplier is well known due to its
regular structure. Multiplier circuit is based
on add and shift algorithm. Each partial
product is generated by the multiplication
of the multiplicand with one multiplier bit.
The partial product are shifted according to
their bit orders and then added. The
addition can be performed with normal
carry propagate adder. N-1 adders are
required where N is the multiplier length.
Although the method is simple as it can be
seen from this example, the addition is done
serially as well as in parallel. To improve
on the delay and area the CRAs are
replaced with Carry Save Adders, in which
every carry and sum signal is passed to the
adders of the next stage. Final product is
obtained in a final adder by any fast adder
(usually carry ripple adder). In array
multiplication we need to add, as many
partial products as there are multiplier
bits[2]. This arrangement is shown in the
figure below.
The VHDL design
We have generated parametric description
for both the array to array multiplier and the
array multiplier and we have used these
description to synthesis 6 bit array
multiplier .For the VHDL moulding we
have used modalism for simulation.
The characteristics of VHDL description
are the following
denoted by A and B respectively, where A=
(a0,a1,a2,a3,a4,a5) and B=(b0,b1,b2,b3,b4,b5)
are chosen for convenience.
Although the architecture shown in fig.-1 is
that of a 6 by 6 bit multiplier. The
regulatory of the architecture enable one to
draw larger multiplier quite easily. The
architecture is very regular, it consist of a
leaf cells, And gate and carry save adder.
The final adder often employ some form of
fast carry propagation scheme and are
implemented differently than the carry-save
adder (FA) used in the array.
However, both of these adders perform the
same logical function in therefore maybe be
regarded to be the same from the point of
view of logical functionality.
Firstly, y1 is multiplied with all digits of
A=(a0,a1,a2,a3,a4,a5)and B=(b0,b1,b2,b3,b4,b5)
using AND gate to give us

1. Can generate 2’s compliment
multiplier
2. Can generate any bit size multiplier
Like 4*6 multiplier
3. The VHDL modal can be synthesis
with the Philips synthesis package
LOCAM_V.
a5b0 a4b0 a3b0 a2b0 a1b0 a0b0
Similar multiplication is performed with all
terms of multiplier and multiplicand as
shown in figure and we get
a5b1 a4b1 a3b1 a2b1 a1b1 a0b1

Theoretical analysis show that for 6 bits a5b2 a4b2 a3b2 a2b2 a1b2 a0b2
array multiplier use carry select addition for
the final adder stage. The array multiplier is
faster than normal multiplier. a5b3 a4b3 a3b3 a2b3 a1b3 a0b3

ARCHITECTURE
The architecture of the 6 bit multiplier is a5b4 a4b4 a3b4 a2b4 a1b4 a0b4
shown in figure given below. It is based on
algorithm.
a5b5 a4b5 a3b5 a2b5 a1b5 a0b5
The algorithm consists of 6*6 operands and
gives the product output and gives the 12
bit product output. In the architecture in
figure of figure 1, the explicit sign
extension circuity has been eliminated by
recoding the most complement number. The
multiplication and the multiplier are
 Carry save adder is used to compute sum of
three or more n-bit binary numbers. Carry
save adder is mostly same as a full
adder.Carry save adder (CSA) is the design
Diagram of a high speed multi operand adder. A
carry save adder consists of a ladder of
stand-alone full adders. The n-bits CSA
consists of n disjoint full adders (FAs)
where each of which computes single sum
and carry bit based on the corresponding
bits of the three input numbers. It consumes
three n-bit carry. Unlike the normal adders
such as ripple carry adder, a CSA consists
of multiple one bit full adders without any
carry chaining.
Si = Ai xor Bi
Ci = Ai and Bi
The final addition is then computed as:
1. Shifting the carry sequence C left by one
place.
2. Placing a 0 to the front (MSB) of the
partial sum sequence S.
3. Finally, a ripple carry adder is used to
add these two together and computing the
resulting sum.

Fig. _1
A 6 bit array multiplier has a delay TABLE I. CARRY SAVE ADDER
proportional to n plus the delay of CSA. COMPUTATION
There are two items we can attack to A: 1 0 0 1 1
improve the performance of a multiplier:
the number of partial products and the B: 1 1 0 0 1
addition of the partial products. Z: + 0 1 0 1 1
Suppose we wish to multiply an 6-bit S: 0 0 0 0 1
binary number A=111000 to by B= 000111.
It is easier to multiply A by B and the result C: + 1 1 0 1 1
gives P = 0000110001000.
Sum: 1 1 0 1 1 1
This helps in saving a lot of time and makes
the circuit to perform at high speed [9].

CARRY SAVE ADDER (CSA) ALGORITHM FOR ARRAY

MULTIPLIER
In Array multiplier, almost identical calls
array is used for generation of the bit-
products and accumulation. All bit-products
are generated in parallel and collected
through an array of full adders or any other
type of adders and final adder. Array
multiplier has a regular structure that
simplifies the wiring and the layout.
Therefore, among other multiplier
structures, array multiplier takes up the
least amount of area. Table II gives an
algorithm steps and shows complete
multiplication process with the help of an
example. In this algorithm, S (i) represents
sum of each product term, B(i)A represents
each product term and P(i) represents
individual bit-term of final product
ModelSim
Mentor Graphics was the first to combine
single kernel simulator (SKS) technology
with a unified debug environment for
Verilog, VHDL, and System C. The
combination of industry-leading, native
SKS performance with the best integrated
debug and analysis environment
make ModelSim the simulator of choice for
both ASIC and FPGA designs. The best
standards and platform support in the
industry make it easy to adopt in the
majority of process and tool flows.
Features
Advanced Code Coverage
ModelSim’s advanced code coverage
capabilities and ease of use lower the
barriers for leveraging this valuable
verification resource.
The ModelSim advanced code coverage
capabilities provide valuable metrics for
systematic verification. All coverage
information is stored in the Unified
Coverage Data Base (UCDB), which is
used to collect and manage all coverage
information in a highly efficient database.
Coverage utilities that analyse code
coverage data, such as merging and test
ranking, are available. Coverage results can
be viewed interactively, post-simulation, or
after a merge of multiple simulation runs.
Code coverage metrics can be reported by
instance or by design unit, providing
flexibility in managing coverage data.
Mixed HDL Simulation
ModelSim combines simulation
performance and capacity with the code
coverage and debugging capabilities
required to simulate multiple blocks and
systems and attain ASIC gate-level sign-off.
Comprehensive support of Verilog, System
Verilog for Design, VHDL, and System C
provide a solid foundation for single and
multi-language design verification
environments. ModelSim easy to use and
unified debug and simulation environment
provide today’s FPGA designers both the
advanced capabilities that they are growing
to need and the environment that makes
their work productive.
Effective Debug Environment
The ModelSim debug environment’s broad
set of intuitive capabilities for Verilog,
VHDL, and SystemC make it the choice for RESOURCES SUMMARY
ASIC and FPGA design.
Macrocell Paterns Registers Pins Functionl
ModelSim eases the process of finding Used Used Used Used Block
inputs
design defects with an intelligently Used
engineered debug environment. The 26/0
ModelSim debug environment efficiently 69/144 277/72 0/144 (- 136/432
(48%) 0 (0%) 2147 (32%)
displays design data for analysis and debug (39%) 4836
of all languages. 47%
)
SIMULATION RESULT
POWER DATA
The VHDL simulation of two 6 bit numbers
is presented in this paper. Macrocells in high
performance mode 0
(MCHP)
Macrocells in low power 69
mode (MCHP)
Total macrocells 69
used(MC)

Advantage of Array Multiplier

1. An array multiplier─ a multiplication
method in which an array of identical cells
generates new partial product and
accumulation of it at the same time
2. We can use pipelines at each level •
Result from the adder can be latched at each
level and used as input for next level adder
circuit
3.The delay is logarithmically proportional
to the bit size of multiplicand and multiplier
if we use the high speed array multiplier
circuit.
Large number of logic gates required to
design an array multiplier.

Summary REFERENCE

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