Sådhanå (2022)47:222 Ó Indian Academy of Sciences

https://doi.org/10.1007/s12046-022-02012-z Sadhana(0123456789().,-volV)FT3
](0123456789().,-volV)

A PID control scheme with enhanced non-dominated sorting genetic

algorithm applied to a non-inverting buck-boost converter
M P E RAJAMANI1,* , R RAJESH2 and M WILLJUICE IRUTHAYARAJAN1
1
Department of Electrical and Electronics Engineering, National Engineering College, Kovilpatti 628503, India
2
Department of Engineering Design, Indian Institute of Technology Madras, Chennai 600036, India
e-mail: mpe.rajamani@gmail.com; ra.rajeshkrishna@gmail.com; m.willjuice@gmail.com

MS received 17 March 2022; revised 23 September 2022; accepted 6 October 2022

Abstract. The non-inverting buck-boost converter is designed to regulate the output voltage of the non-linear
converter in real-time applications. Numerous studies have been carried out in recent years to improve the
dynamic behavior of converters using intelligent control techniques; still, the occurrence of large overshoots in
transient and reduction of ripple over voltage has not been effectively discussed. This can be efficiently handled
by selecting filter capacitance values effectively. This article proposes a design of a Proportional-integral-
derivative controller optimized by a non-dominated sorting genetic algorithm (NSGA) and enhanced non-
dominated sorting genetic algorithm (ENSGA) to choose the filter capacitance value and to maintain the
converter output voltage at the desired level. A dynamic crowding distance-based ENSGA has been employed to
attain the homogenous distribution of non-dominated solutions. The stability of the buck-boost mode is analyzed
using frequency response. Based on the simulation results obtained for various load conditions, the ENSGA
controller outperformed the NSGA controller in terms of better output voltage regulation, lesser transients, and
minimizing the ripple voltage.

Keywords. Non-inverting buck-boost converter; PID controller; NSGA; ISE; Performance specifications.

1. Introduction BBC’s output voltage regulation operating in the open loop

For the past few decades, the field of power electronics has
been developed enormously, more consciously in power
generation, conversion, and power regulation. This is due to
the massive requirement for electrical and electronic
applications that need components to carry out the work.
Among the different kinds of power electronic devices, DC
to DC converters is predominantly studied by engineers and
scientists. It is used with various input and output voltage
ranges, as in the charging and discharging of lithium-ion
batteries [1]. Similarly, the non-linear nature of solar irra-
diance results in non-linearly generated power which
requires efficient converters to regulate the output voltage.
Some well-known topologies are proposed to satisfy the
above requirement, such as conventional Bidirectional
Buck-Boost Converter (BBC), Cuk converter, and single-
ended primary-inductor converter (SEPIC) converter. In
1998, a non-inverting buck-boost converter was designed
[2] to increase and decrease the output voltage without
changing its polarization from that of the input voltage.
This article introduced additional switches and diodes in
the proposed NIBBC with a controller to address the power
quality issues. For its non-minimum characteristics, the
*For correspondence
is undesirable. The transient takes a long time to settle in
the steady-state value [3], and better performance can be
achieved with an appropriate feedback controller.
In this context, researchers have made several milestone
contributions to control techniques and design aspects of
the BBC, and some of the contributions are reviewed
herein. The small-signal modeling for KY BBC is pre-
sented in [4]; the current and voltage modes controller are
also proposed to overcome the switching losses and
improve power conversion efficiency. A conventional lin-
ear controller for the multi-port BBC has been presented in
[5] to handle nonlinear uncertainty and external distur-
bances under different operating conditions. The multi-loop
controller has been proposed for the NIBBC to address
unmodeled system parameters and predict the voltage
transients caused by a step change [6]. Similarly, a cas-
caded controller is presented [7] for the boost converter’s
non-minimum phases, and the different operational range
of the reference voltage has been studied. But sometimes,
the extra loop may lead to system instability and compli-
cations. The switching capacitor-based BBC for the load
applications is presented in [8], demonstrating a seamless
shift from buck and boost mode of operation experimen-
tally. Similarly, predictive control with optimization tech-
nique has been shown in the [9] to handle smooth load
222 Page 2 of 18
transfer in the BBC. The PWM control method has been
addressed in [10] to operate the controller at operation
mode switching when the output voltage falls near the input
voltage range.
In the works of literature, various control approaches for
converters have been developed [11–14]. Still, many
researchers concentrated on PID controllers with opti-
mization techniques for the output voltage regulation,
components values optimization, and performance
improvement of the BBC. The PID controller is the stan-
dard control technique for many industrial applications [15]
due to its simple structure with stable operating conditions
[16–19]. The particle swarm optimization algorithm has
been presented in [20] with the PID controller for the
interleaved BBC converter; the simulation results are
demonstrated a fast and stable response under varying load
conditions. A similar algorithm has been proposed in [21]
for handling uncertain parameters in converters. The solu-
tion also relies on a particle swarm optimization algorithm
that minimizes an error, allowing better results than the
conventional fixed gain PID controller. A proportional-in-
tegral controller with an artificial fish swarm optimization
algorithm is proposed for a BBC for voltage regulation
[22]. The PID controller with the Levy flight distribution
algorithm has been presented for the buck converter [23],
and the effectiveness of the algorithm is proved through
disturbance rejection, robustness, and transient response. A
cuckoo search algorithm was introduced to find the optimal
PID controller parameters for the BBC of the light-emitting
diode circuit; the time-domain specifications are presented
[24]. A hunger games search algorithm has been proposed
to optimize converters parameters and controller gains [25].
In [26], the genetic algorithm optimized by a pre-calculated
duty cycle is presented for a Non-Inverting Buck-Boost
Converter (NIBBC). A solar-powered battery charging
application, a genetic algorithm-based PID controller, has
been used for the BBC [27]. The outcomes showed a better
system stability response and low steady-state error. Simi-
larly, a modified real-coded genetic algorithm has been
proposed for interleaved boost converter for efficiency
improvement [28]. In a similar contribution, [29] have
developed the design procedure for an isolated DC to DC
power electronic converter. The stable and robust control
scheme in [30, 31] manages transients and the steady-state
performance of DC to DC converters. In [32], the NSGA II
optimization algorithm has been proposed for power con-
version and controller stages of interleaved boost convert-
ers in electric vehicle trains. Even though many
optimization controllers have been proposed for the BBC
control purpose and parameters optimization, a genetic
algorithm-based optimization technique is prevalently
compared to other methods. Because most search opti-
mization issues are constrained in nature, this approach is
best suited for unconstrained optimization problems. Also,
many newly proposed modified genetic algorithms [33, 34]
have improved searching capacity, low computation time,
Sådhanå (2022)47:222
better convergence, and robustness. This article uses NSGA
and ENSGA to optimize the PID controller parameters.
NSGA-based algorithms are preferred because of their less
computational effort and more independent distribution
over the Pareto front.
The appropriate selection of filter capacitance can reduce
the ripple voltage in DC to DC converters; the very high
value of the DC filtering capacitor may lead to poor
dynamic performance, and the small value of the DC link
capacitor may increase the ripple voltage across the load.
So, it is essential to select the optimal value of the filter
capacitor. In this paper, two objectives are considered, such
as tuning the parameters of the PID controller and choosing
filter capacitance which can be solved by framing a multi-
objective strategy. The two objectives of the algorithm are
to find optimal values for kp , ki and kd are selected to
achieve minimal ISE of the output voltage to the reference
DC output voltage and the mitigation of ripple in the DC
voltage output. The NSGA algorithm has been proved to be
a versatile multi-objective optimization algorithm in
numerous works of literature. The NSGA algorithm has
been employed to optimize the economic reactive power
dispatch problem [35]. The combined economic dispatch
and emission minimization have been optimized in [36].
This strategy in [37] has solved the reactive support plan-
ning problem. In [38], the NSGA algorithm is adopted for
the speed regulation and minimization of torque ripple that
arises in the switched reluctance motor. The proposed
article addresses the following objectives:
1. To select optimal filter capacitance value, the NSGA and
ENSGA have been realized in simulation and real-time
environments for tuning PID controller parameters.
2. To control the output voltage of the converter by
minimizing the ISE of desired and the actual output
voltage.
3. To compare the performance of the proposed NSGA and
ENSGA and to identify the better strategy to design the
converter.
The article is presented as follows. The average state-
space modeling of energizing mode and de-energizing
mode of the NIBBC is presented in section 2. The
PID controller gains for NIBBC, multi-objective
function, review of optimization algorithms, and the
proposed structure model are presented in section 3.
Simulink model implementation for NIBBC, param-
eters for algorithm development, and statistical per-
formance of the NSGA and ENSGA are discussed in
section 4. Section 5 presented the simulation results
for various source voltage, load conditions, statistical
performance, and stability analyses of the NIBBC.
The experimental validation is described in section 6.
The conclussins are provided in section 7.
Sådhanå (2022)47:222 Page 3 of 18 222

2. Averaged state-space model of the NIBBC

Establishing the mathematical modeling of the dynamic

system for each mode of operation of the converter is the
first step in analyzing and controlling the converter. The
switching table and operation mode of the NIBBC are given
in table 1. If the converter output voltage is less than the
input voltage, it will be operated in buck mode. In this
Figure 1. Topology of the NIBBC.
instance, the S1 switches between ON and OFF states while
the S2 switch turns off during the switching interval.
Similarly, if the output voltage is higher than the input
voltage, the converter operates in boost mode, in which S1
remains in the ON state and S2 in switching. The NIBBC is
equivalent to operating the converter in buck-boost mode if
both S1 and S2 are switched simultaneously with the same
duty cycle. At the same time, continuous switching will
increase the switching loss and decrease the model per-
formance. In this mode, the S1 and S2 are continuously in
switching mode; hence, switch loss is higher than in the
other modes, which decreases the operation efficiency. The
topology of the NIBBC is given in figure 1, which has two
N-channel MOSFET switches, S1 and S2, two power diodes
D1 and D2, and an inductor L and filtering capacitor C.
The NIBBC converted operated in the energizing and de-
energizing modes. The S1 and S2 are ON in the energizing
mode, and D1 and D2 are OFF. The inductor L carries the
input current and gets charged with energy, and this state is
shown in figure 2(a).
A voltage equation of energizing mode is given in (1). Figure 2. (a) S1 and S2 ON (Energizing Mode) and (b) S1 and
S2 OFF (De-energizing mode).
diL
Vs  L  iL rL ¼ 0 ð1Þ
dt
1
The standard form (1) is given in (2). x_2 ¼  x2 ð5Þ
C ðrC þ R Þ
diL i L rL V s The final energizing mode state-space equation of the
¼ x_1 ¼  þ ð2Þ
dt L L NIBBC is given in (6) and (7)
The current equation of the energizing mode is given in 0 r 1
  
L
0   !
(3) 1
x_1 B L C x1
¼@ 1 A þ L Vs ð6Þ
iC þ iO ¼ 0 ð3Þ x_2 0 x2 0
C ðrC þ RÞ
The iC and iO can be written as   
R x1
ð V0 Þ ¼ r ð7Þ
dVC R Vo VC þ C dVdtC rC R þ rL x2
iC ¼ C ¼ and io ¼ ¼ ð4Þ
dt ð r C þ RÞ R R In the de-energizing state, S1 and S2 are turned OFF, and
The standard form (4) is given in (5). D1 and D2 are in the ON state; the inductor L delivers
power to the load, as shown in figure 2(b). A de-energizing
mode interval is considered as ð1  kT Þ, where k is the duty
Table 1. Operation Mode of a NIBBC. cycle. The voltage equation of this mode is given by (8).
Mode S1 S2 diL dVC
L þ iL rL þ VC þ C rC ¼ 0 ð8Þ
Buck Switching OFF dt dt
Boost ON Switching
The standard form of the voltage equation (9) can be
Buck-Boost Switching Switching
obtained by rearranging the (8).
222 Page 4 of 18 Sådhanå (2022)47:222

diL iL rL x2 CrC x_2 comparator, where it is compared with a high-frequency

¼ x_1 ¼    ð9Þ carrier. The output of the second comparator is a train of
dt L L L
switching pulses with the appropriate duty cycle that reg-
The current equation of the de-energizing state is given ulates the output voltage. In the proposed structure, the
in (10), (11), (12), and (13). NSGA has been employed to optimize the PID controller to
iL ¼ iC þ iO ð10Þ attain the optimal gain and to identify the filter capacitance
value such that the output voltage is effectively regulated.
dVC R figure 4 shows a schematic of switching pulses from the
iC ¼ C ¼ ð11Þ
dt ðrC þ R Þ controller output. The two triangular carrier waveforms are
compared to the controller output to identify the buck and
Vo VC þ C dVdtC rC boost switching stages. The VH1 and VL1 represent the high
io ¼ ¼ ð12Þ and low levels of carrier voltage waveform in the buck
R R
region; also at the boost region, VH2 and VL2 represents the
dVC VC þ C dVdtC rC voltage level. The control pulses generated for S1 and S2 to
iL ¼ C þ ð13Þ
dt R operate in buck and boost state of operation are represented
by G1 and G2, respectively.
The standard form of the current equation is given in (14)
and (15).
1 1 3.1 PID controller gains for NIBBC
x_2 ¼ rC  x1    x2 ð14Þ
C R þ1 RC rRC þ 1 The error voltage produced by the PID controller when the
! NIBBC is activated in a closed-loop is,
rC 1 1 1
x_1 ¼  rL þ rC  x1  r C  x2 ð15Þ eðtÞ ¼ Vref  Vactual ð19Þ
R þ1 R þ1
L L
The PID controller output voltage [39, 40] is (20).
The final state equation is given (16) by considering the
duration of the OFF period ð1  kT Þ of the switching cycle. Z
d
2 0 1 3 cðtÞ ¼ Kp eðtÞ þ Ki eðtÞdt þ Kd eðtÞ ð20Þ
dt
6 B rC 1 1 1
  6 @rL þ rC C
A r 7 7 The controller gains are (21), (22), and (23).
x_1 6 þ1 L C
þ1 L 7
¼6
6 R R 7 ð16Þ
7 R1 C1 þ R2 C2
x_2 6 1 1 7 Kp ¼ ð21Þ
4 r r 5 R1 C 2
C C
C þ1 RC þ1
R R 1
Ki ¼ ð22Þ
The output voltage of the buck-boost converter is written R1 C2
by (17).
Kd ¼ R1 C2 ð23Þ
Vo ¼ iO R ¼ ðiL  iC ÞR ð17Þ
The Kp , Ki and Kd are the controller gains, R1 , and R2 are
The output voltage is (18) obtained by substituting the the values of resistors, and C1 , and C2 signifies the PID
expression for inductor and capacitor currents (17). controller capacitance.
  
RrC R x1
Vo ¼ ð18Þ
ðR þ rC Þ ðR þ rC Þ x2 3.2 Objective functions
The cost function of the proposed multi-objective problem
is given as follows:
3. Control of the NIBBC with PID controller tuned
f ¼ min ðf1 ; f2 Þ; subjected to xl \x\xu ð24Þ
by NSGA
Zt
The NSGA controller employed with the buck converter is  2
f1 ¼ ISE desired output voltage ¼ Vref  Vactual dt
shown in figure 3, where the error signal generated from the
0
comparator by comparing the load voltage with reference is
fed into the PID controller. The comparator circuit com- ð25Þ
pares the voltage across the load and the reference voltage,
and this error signal is fed to the input of the PID controller.
The PID controller gives the control output to another
Sådhanå (2022)47:222 Page 5 of 18 222

Figure 3. Block Diagram of the proposed NIBBC with the PID controller tuned by NSGA.

Figure 4. PWM generated strategy for the buck and boost switches.
222 Page 6 of 18 Sådhanå (2022)47:222

Zt more cost functions is identified as Multi-Objective Opti-

f2 ¼ ISE ripple output voltage ¼ ðVmax  Vmin Þ2 dt mization (MOO) problem [41]. To achieve one optimal
solution, it is sometimes necessary to sacrifice one or more
0
of the various application’s objectives. Thus, MOO offers a
ð26Þ variety of Pareto-optimal fronts, also known as non-domi-
where xl and xu represents
the lower and upper limit of nated solutions, unless when there are no conflicts between
 the objectives in which case there is only one single solu-
controller parameters; x ¼ Kp ; Ki ; Kd , and C ; the ISE of
tion. Traditional optimization methods proceed by chang-
the controller output is given by f1 ; the ISE of ripple output
ing the MOO problem into a single-objective problem by
voltage f2 ; the simulation time ‘t’.The PID controller
signifying a specific Pareto-optimal solution at a time. It is
parameters ranges are Kp [ [0, 10], Ki [ [0, 100], and Kd [ [0,
necessary to repeat these traditional approaches numerous
5] and C[[100 to 1000] in microfarad.
times to identify various solutions for every simulation run
when there are multiple solutions to be found. For finding
numerous Pareto-optimal solutions in a single simulation
3.3 Overview of NSGA and ENSGA algorithms
run, several MOO evolutionary algorithms have been pro-
Optimizing systematically and simultaneously to find a posed over the past decade. In the last few decades,
decision variable that corresponds to an optimum of two or

Table 2. Specification of the NIBBC. Table 3. Parameter used for the optimization.

Specifications Values Parameters Values

Input Voltage (Vs) 6-24 V No. of variables (n) 4
Output voltage (Vo) 12 V Cross over probability (Pc) 1
Maximum load Current (Io) 0.24 A Mutation probability (Pm) 1/n
Switching Frequency 40 kHz SBX crossover constants (gC) 2
Resistance of Inductor (rL) 0.5 X Mutation constants (gm) 20
Resistance of Capacitor (rC) 0.2 X Population size 100
Inductor (L) 2.17 mH No. of runs 20
Load Resistor (R) 50 X Maximum No. of functional evaluations 10,000

Switch 1
g m L
D S

D2
g
D

Vs
Switch 2 + v
D1 C R -
m
S

Vo

Sawtooth
vo
Generator
Gain To Workspace
PID Controller
1/setpoint
PID(s)

Constant

Figure 5. MATLAB/Simulink model for NSGA controller.

Sådhanå (2022)47:222 Page 7 of 18 222

Table 4. Statistical performance comparison.

Parameters Best value Mean value Worst value Std. optimal value
NSGA
ISE desired output voltage (V) 43.52 47.53 55.65 6.75
ISE ripple output voltage (V) 0.218 0.352 0.581 0.318
ENSGA
ISE desired output voltage (V) 39.17 43.15 49.62 5.231
ISE ripple output voltage (V) 0.193 0.291 0.55 0.213

Table 5. Optimal parameters.

Best optimal parameters

Method Kp Ki Kd Capacitor (lF)

NSGA 1.84 57.3 0.0034 220
ENSGA 1.32 63.42 0.0023 470

numerous MOO algorithms based on evolutionary concepts

Figure 6. ISE profile with NSGA for NIBBC.
have been developed [42–47].
The NSGA algorithm is one of the modified versions of
the classical GA, where only the operation of the selection
operator is changed. In NSGA, a shared fitness is used for
the selection operator [48]. To maintain diversity and uni-
formity, an enhanced version of NSGA [48], a classical
algorithm named NSGA-II, efficiently integrates the elitist
preserving approach and the crowding distance (CD)
function [38]. It mainly focuses on avoiding more
exploitation than exploration, lateral diversity must be
prominent to better converge with the search algorithm. To
bay the full Pareto-front, the non-dominated solutions are
required to be distributed equally. Dynamic crowding dis-
tance (DCD) [49] is employed to handle the limitation of
NSGA
The same-rank solutions in NSGA are ranked according
to CD (27).

1X r 
f k  f k 

CDi ¼ iþ1 i1 ð27Þ
r k¼1

where DC of the ith solution is given by CDi ; the number of

the objective is given by r; fik represents the ith solution of
kth value.
Where the crowding distance is CDi ; the number of
objectives is represented by r; fik is the kth objective value
of the ith solution. However, the crowding distance faces a
poor uniform diversity issue that makes it difficult to
choose the optimum solution. DCD (28) methods are
included in the ENSGA algorithm to prevent this issue.
Figure 7. ISE Profile for ENSGA NIBBC.
222 Page 8 of 18 Sådhanå (2022)47:222

Figure 8. Simulation result of NIBBC (boost mode, Vs =6V) for output voltage Vo = 12V and current Io=0.24A (a) NSGA and
(b) ENSGA.

Figure 9. Simulation result of NIBBC (boost mode, Vs = 24 V) for output voltage Vo = 12 V and current Io=0.24 A (a) NSGA and
(b) ENSGA.

CDi The information of various degrees of CD in the ith

DCDi ¼ ð28Þ
logð1=Vi Þ solution with information on the neighbors is given by the
variance (29).
Sådhanå (2022)47:222 Page 9 of 18 222

Figure 10. Ripple voltage of NIBBC (a) NSGA and (b) ENSGA.

Figure 11. Dynamic response of NIBBC in boost operation for line variation (Vs changes from 6 V to 12 V) (a) NSGA and (b) ENSGA.

1X r    Step 5: If the sorting set, jQðtÞj  N, break population

Vi ¼ f k  f k   CDi 2 ð29Þ
iþ1 i1
r k¼1
Additionally, the inclusion of DCD methods modifies the
non-dominated sorting algorithm. Where N represents the
population of particles, the ith generation of non-dominated
sorting set is QðtÞ[50].
The algorithmic steps are presented as follows:
Step 1: Check for the condition of the sorting set,
jQðtÞj  N, then proceed with Step 5; else continue.
Step 2: Evaluate the solution for all the conditions of the
sorting set for DCD QðtÞ based on (7).
Step 3: Perform sorting on the non-dominated sorting set,
QðtÞ based on solutions from Step 2.
Step 4: Make a clean sweep of the solutions with the
lowest DCD in the sorting set, QðtÞ.
maintenance; else jump to Step 2 and Proceed.
As can be seen, one solution is always removed and all
DCD solutions QðtÞ are regenerated.
It is observed that at each iteration one solution is
rejected and other DCD solutions are recalculated. As a
result, a Pareto front with high uniformity can be attained as
well as the diversity of altered non-dominated sorting.
4. Design of optimized PID controller
for the NIBBC
Table 2 contains a list of the NIBBC converter’s circuit
design specifications. The MATLAB/Simulink R2019a
software is used throughout the entire simulation process,
which is implemented in a pc with an Intel i5 processor
222 Page 10 of 18 Sådhanå (2022)47:222

Figure 12. Dynamic response of NIBBC in buck operation for line variation (Vs changes from 12 V to 24 V) (a) NSGA and
(b) ENSGA.

Figure 13. Dynamic response of NIBBC in boost (Vs = 6V) operation for load variation (Io changes from 0.24A to 0.16A) (a) NSGA
and (b) ENSGA.

running at 3.90 GHz and 32 GB of RAM. figure 5 shows
the NIBBC’s MATLAB/Simulink model.
The NSGA and ENSGA optimization algorithms are
applied to NIBBC for the PID controller’s parameters
tuning and to select optimum filter capacitance value by
minimizing ISE, the optimal parameters listed in table 3. To
ensure the optimum result, each trial made 10 independent
runs and average values are reported. The statistical per-
formance of the proposed PID controller tuning is tabulated
in table 4. Figures 6 and 7 represent the Pareto-optimal
Sådhanå (2022)47:222 Page 11 of 18 222

Figure 14. Dynamic response of NIBBC in boost (Vs = 24 V) operation for load variation (Io changes from 0.24A to 0.16 A) (a) NSGA
and (b) ENSGA.

Figure 15. The control signal of the PID controller for NIBBC.

front of the NSGA and ENSGA. The obtained optimal
parameters using the optimization algorithm are presented
in table 5, the optimal controller parameters of the PID
controller optimized by conventional ENSGA are Kp is
1.32, Ki is 63.42 and Kd is 0.0023, the filter capacitance is
470 lF.
5. Simulation results and analysis of NIBBC
The NIBBC has been tested under various conditions with
the proposed optimization strategies with the PID controller
to analyze the proposed methodology’s performance. The
simulation result for the PID controller tuned for boost
222 Page 12 of 18 Sådhanå (2022)47:222

Figure 16. PWM generated signal for NIBBC.

Table 6. Performance Comparisons Proposed ENSGA controllers for NIBBC with Existing Works of Literature.

Settling time Steady-state error Peak overshoot Output ripple voltage

Method Kp Ki Kd (ms) (V) (V) (V)
Conventional PID Controller 3.02 41.29 0.012 10 1.02 3.9 1.85
[15]
PSO-FOPID Controller [17] 1.07 59.89 0.0052 5.2 0.42 2.09 0.79
NSGA-PID Controller [38] 1.59 60.31 0.0041 4.82 0.82 1.90 0.95
NSGA-PID Controller [38] 1.84 57.3 0.0034 6.0 0.9 1.6 0.74
Proposed ENSGA-PID 1.32 63.42 0.0023 3.5 0.01 0.02 0.32
Controller

Figure 17. Performance Comparisons of NSGA and ENSGA-based controllers for NIBBC.
Sådhanå (2022)47:222 Page 13 of 18 222

Figure 18. Frequency response of NIBBC in buck mode. Figure 20. Computational analysis of the proposed controller.

are shown in figure 9 for the input voltage of 24 V. The

output voltage and output current are observed as 12 V and
0.24 A, respectively. On comparing the performance of the
NSGA algorithm the performance of ENSGA outperformed
with PID controller tuning in both buck and boost modes,
the transients decreased in ENSGA controller than to
NSGA based controller. A similar performance is shown in
the output current also.
The ripple voltage of NIBBC is presented in figure 10. In
the NSGA-based controller tuning strategy, the output
voltage fluctuates between 11.96 V to 12.7 V with a peak-
to-peak ripple voltage of 0.74 V, whereas in the case of
ENSGAbased PID controller, the output voltage varies
between12.2 V and 11.88 V, with a peak to peak ripple
voltage of 0.32 V. From the obtained results it is observed
that the voltage obtained at the output of the NIBBC is
Figure 19. Frequency response of NIBBC in boost mode. much reduced with the NSGA tuned PID controller than
that obtained with the PID controller tuned with the NSGA
algorithm.
The system has been tested for its dynamic response to the
Table 7. Frequency response Comparisons of NSGA and disturbance given at the source and load side. The response of
ENSGA-based controllers for NIBBC. the NIBBC with the source side disturbances is shown in
Mode of Phase Margin Gain Margin Bandwidth figure 11 for the boost converter. As for the source side, the
operation (deg.) (dB) (Hz) input voltage was changed from an initial value of 6 V to 12 V
at time instant t = 2 seconds. Further, at time instant at t = 4
NSGA seconds, the input voltage was changed back to 6 V. Simi-
Buck mode 89.1 ? 1.89E?04
larly, experimentation was carried out in the buck mode, as
Boost mode 78.5 ? 1.65 E?03
shown in figure 12. At time t = 2 seconds, the source voltage
ENSGA
Buck mode 100.2 ? 1.92 E?04 was changed from an initial value of 12 V to 24 V at time
Boost mode 89.5 ? 1.45 E?03 instant t = 2 seconds. At time instant t = 4 seconds, the input
voltage is changed back to 12 V. On comparing the perfor-
mance of NSGA and ENSGA controllers during buck and
mode operation with an input of 6V is presented in figure 8. boost modes the ENSGA controller shows lesser transients
The output voltage and output current are observed as 12 V than the NSGA controller.
and 0.24 A, respectively. Similarly, simulation results of The dynamic system response of NIBBC is analyzed for
NIBBC using the proposed NSGA strategy for buck mode load variation for both boost and buck modes. The
222 Page 14 of 18 Sådhanå (2022)47:222

Figure 21. Circuit diagram of NIBBC with PID controller.

Figure 22. Hardware prototype of NIBBC using NSGA-based

controller.

resistance is varied in the range of 50 X to 75 X at t= 2 Figure 23. Experimental result of NIBBC (boost mode, Vs = 6
seconds and is restored at t= 4 seconds, and the input V) using ENSGA-based controller.
voltage is maintained at 6V for the boost converter. The
observed output current varies from 0.24 A to 0.16 A, as
shown in figure 13 the proposed controllers. Similarly,
been compared with existing works of literature and pre-
during buck mode, the load is varied at an input voltage of
sented in table 6. It is identified that the proposed ENGSA-
24 V, and the output current is varied load variations are
PID controller outperformed other techniques in literatures
also given to the buck mode, as shown in figure 14, with an
with better time domain specifications, also the bar
input voltage of 24 V the output current varies from 0.24 A
chart representation given in figure 17.
to 0.16 A. The input voltage to the PID controller and
For a dc-dc converter system to be stable and properly
output voltage from the PID controller is represented in
regulated, the frequency response tries to ensure the fol-
figure 15, and PWM generated signal for NIBBC is given in
lowing criteria. [51, 52].
figure 16. The performance of the proposed controller has
Sådhanå (2022)47:222
Figure 24. Experimental result of NIBBC (boost mode, Vs = 6
V) using ENSGA-based controller.
Figure 25. Experimental dynamic response of NIBBC (boost
mode) using ENSGA for line variation.
1. To minimize steady-state error, the gain in the low-
frequency band is supposed to be high. Preferably,
frequency response should have a -20dB/decade slope at
low frequency.
2. To guarantee near loop stability, the phase margin must
be higher than 45°. The Greater phase margin decreases
the transient response and lowers the peak overshoots
due to supply flections.
3. The 1/10 to of the converter switching frequency
should be the system’s bandwidth.
The frequency response comparison of the buck and
boost mode converter with the proposed optimal PID con-
troller is given in figures 18 and 19. The observed fre-
quency domain performance criteria are tabulated in table 7
using buck mode and boost mode with an ESR of 30 mX. It
indicates the ENSGA-based controller has performed better
than NSGA based controller in terms of stability. The PID
controller’s pole is located at the origin, which enhances the
phase margin and eliminates closed-loop steady-state error
Page 15 of 18 222
Figure 26. Experimental dynamic response of NIBBC (buck
mode) using ENSGA for line variation.
for step input disturbance. But, a closed-loop system is
more vulnerable to high-frequency noise and output voltage
ripples due to the ?20 dB/decade increase in the high-
frequency area. The residual ESR affects the derivative
gain and it has considerable impedance at a typical
switching frequency.
The computational time of the proposed algorithm is
compared with the conventional PID controller and the
controller [15] tuned by the conventional NGSA opti-
mization strategy [38], and presented in figure 20, where
the conventional PID controller reported 152 s of average
executed time, and the NGDA PID controller reported 85s,
whereas the ENGSA PID reported 83s of execution time.
The simulation has been iterated for 10 iterations and the
average computational time has been reported (figure 21).
6. Real-time experimental evaluation of NIBBC
Concerning the simulation results obtained for the proposed
controller strategy, the ENSGA has been implemented in
hardware evaluation. The experimental setup of the
ENSGA tuned NIBBC, as shown in figure 22 is assembled
as per the circuit shown in figure 21. The real-time results
of ENSGAbased NIBBC are shown in figures 23, 24, 25,
26, 27. Figure 23 depicts the input and output voltage of the
ENSGA-based controller for NIBBC without any distur-
bance input and in load resistance of 50 Ohms. For given
input of 6 V, the output obtained is 12 V in the ENSGA-
based NIBBC. In this experimental result, there are lesser
transients in line with simulated results. Similarly, the
output load current recorded is 0.24 A, shown in figure 24.
The efficiency of the controller is evaluated by the varying
input voltage and load resistance, and the results are pre-
sented in figures 25, 26, 27. The output voltage remains
constant irrespective of the change in input voltage during
buck and boost modes. In boost mode, the input voltage is
222 Page 16 of 18 Sådhanå (2022)47:222

diversity and maintain the homogeneous dispersion of non-

Figure 27. Experimental dynamic response of NIBBC using
ENSGA for load variation.
dominated solutions. The proposed control methodology
has been tested in a simulation MATLAB/Simulink 2019a
environment and validated in real-time under various line
and load conditions. The performance of the proposed
multi-objective framework has been compared in terms of
time domain specifications. It is observed that the proposed
ENSGA algorithm-based optimal controller has reported
better time domain specifications than the conventional
NSGA-based converter. Also, it is demonstrated that the
proposed converter design outperformed the line and load
disturbances with lesser transient and better stability mar-
gins. To test the algorithm under RL load or DC motor, the
proper modification in the objective function and design in
the circuit is required, which is our future scope of this
research.

List of symbols
PID Proportional-Integral-Derivative Controller
MOO Multi-objective optimization
NSGA Non-dominated Sorting Genetic Algorithms
ENSGA Enhanced Non-dominated Sorting Genetic
Algorithms
ISE Integral Squared Error
NIBBC Non-Inverting Buck Boost Converter
BBC Buck Boost Converter
MOSFET Metal Oxide Semi-Conductor Field Effect
Transistor
PWM Pulse Width Modulation
GA Genetic Algorithm
CD Crowding Distance
DCD Dynamic crowding distance
Figure 28. Ripple voltage of ENSGA controller-based NIBBC. D1 and Power Diodes
D2
L Inductor
C filtering capacitor
varied from 6 V to 12 V, whereas, for buck mode, the line R Load Resistor
variation is done by varying from 24 V to 12 V. Similarly, S1 Buck switch of N-channel MOSFET
on varying the load resistance the proposed converter S2 Boost switch of N-channel MOSFE
illustrated better performance with less ripple voltage. fig- VH1 Maximum voltages of the carrier waveform of
ure 28 illustrates the ripple produced in NIBBC with a filter the buck region
capacitance of 470 microfarads. The proposed ENSGA VL1 Minimum voltages of the carrier waveform of
approach produces a ripple voltage of 0.4 whereas in sim- the buck region
ulation the produced ripple voltage is 0.32 V as a ripple VH2 Maximum voltages of the carrier waveform of
value. the boost region
VL2 Minimum voltages of the carrier waveform of
the boost region
7. Conclusion G1 Gate pulses for buck switch
G2 Gate pulses for boost switch
In this article, a multi-objective optimization strategy such Vs Source Voltage
as ENSGA has been proposed to optimize the performance V0 Output Voltage
of the PID controller by tuning its parameters to optimal fs Switching Frequency
value and identifying the filter capacitance so that the rL equivalent resistance of inductor
performance of the NIBBC is improved. The ENSGA rC equivalent resistance of capacitor
combines the NSGA algorithm with DCD to handle lateral
Sådhanå (2022)47:222 Page 17 of 18 222

iL Inductor current [7] Chen Z, Gao W, Hu J and Ye X 2010 Closed-loop analysis

iC Capacitor current and cascade control of a nonminimum phase boost converter.
IEEE Trans. Power Electron. 26(4): 1237–1252
i0 Output current
[8] Veerachary M and Khubchandani V 2018 Analysis, design,
VC Capacitor voltage
and control of switching capacitor based buck–boost con-
VL Inductor voltage verter. IEEE Trans. Ind. Appl. 55(3): 2845–2857
x1 State variables for the current flowing through [9] Weng X, Zhao Z, Chen K, Yuan L and Jiang Y 2020 A
the inductor nonlinear control method for bumpless mode transition in
x2 State variables for the voltage across the noninverting buck–boost converter. IEEE Trans. Power
capacitor Electr. 36(2): 2166–2178
1 - kT OFF state period [10] Li X, Liu Y and Xue Y 2020 Four-switch buck-boost
kT ON state period converter based on model predictive control with smooth
Vsp Instantaneous set point voltage mode transition capability. IEEE Trans. Ind. Electr. 68(10):
Vact Instantaneous actual voltage 9058–9069
[11] Markkassery S, Saradagi A, Mahindrakar A D, Lakshmi-
e(t) Instantaneous error voltage
narasamma N and Pasumarthy R 2020 Modeling, design and
yu Upper bounds of capacitance value
control of non-isolated single-input multi-output zeta–buck–
xu Upper bounds of PID controller gains boost converter. IEEE Trans. Ind. Appl. 56(4): 3904–3918
yl Lower bounds of capacitance value [12] Ghanghro A, Sahito A, Memon M and Soomro A 2020
xl Lower bounds of PID controller gains Nonlinear controller for buck boost converter for photo-
Vmax Maximum output voltage voltaic system. Int. J. Electri. Eng. Emerg. Technol. 3(2):
Vmin Minimum output voltage 59–63
f1 function for minimization of desired output [13] Linares-Flores J, Juárez-Abad J A, Hernandez-Mendez A,
voltage Castro-Heredia O, Guerrero-Castellanos J F, Heredia-Barba
f2 function for minimization of ripple voltage R and Curiel-Olivares G 2021 Sliding mode control based on
Kp Proportional gain linear extended state observer for DC-to-DC buck-boost
power converter system with mismatched disturbances. IEEE
Ki Integral gain
Trans. Ind. Appl. 58(1): 940–950
kd Derivative gain
[14] Hammoudi M Y, Saadi R, Cardoso A J M, Benbouzid M E H
n No. of variables and Sahraoui M 2020 Practical implementation of H-infinity
control for fuel cell-interleaved boost converter. Int.
J. Model. Simul. 40(1): 44–61
[15] Ramakrishnan R and Subramaniam Nachimuthu D 2021
Design of state feedback LQR based dual mode fractional-
References order PID controller using inertia weighted PSO algorithm:
for control of an underactuated system. J. Inst. Eng. (India)
[1] Almasi O N, Fereshtehpoor V, Khooban M H and Blaabjerg Ser. C 102(6): 1403–1417
F 2017 Analysis, control and design of a non-inverting buck- [16] Åström K J, Hägglund T, Hang C C and Ho W K 1993
boost converter: a bump-less two-level T-S fuzzy PI control. Automatic tuning and adaptation for PID controllers-a
ISA Trans. 67: 515–527 survey. Control Eng. Pract. 1(4): 699–714
[2] Caricchi F, Crescimbini F, Capponi F G and Solero L 1998 [17] Rajesh R and Deepa S N 2020 Design of direct MRAC
February. Study of bi-directional buck-boost converter augmented with 2 DoF PIDD controller: an application to
topologies for application in electrical vehicle motor drives. speed control of a servo plant. J. King Saud Univ. Eng. Sci.
In: APEC’98 Thirteenth Annual Applied Power Electronics 32(5): 310–320
Conference and Exposition, pp. 287–293 [18] Rajesh R 2019 Optimal tuning of FOPID controller based on
[3] Kumar V I and Kapat S 2021 June. A Digitally Current PSO algorithm with reference model for a single conical tank
Mode Controlled Non-Inverting Buck-Boost Converter for system. SN Appl. Sci. 1(7): 1–14
Fast Voltage Transitions. In: 2021 IEEE Applied Power [19] Rajesh R and Krishnan P H 2018 Effects of adaption gain in
Electronics Conference and Exposition, pp. 2520–2525 direct model reference adaptive control for a single conical
[4] Wang F, Li J and Ma X 2016 Small-signal modeling and tank system. Digit. Signal Process. 10(5): 77–82
analysis of KY buck-boost converter. Electric Power Comp. [20] AlMa’aitah M, Abuashour M I, Al-Hattab M, Abdallah O
Syst. 44(7): 783–793 and Sweidan T E O 2019 Optimisation of PID controller
[5] Boora A A, Zare F, Ghosh A and Ledwich G 2009 Utilising employing PSO algorithm for interleaved buck-boost power
robustness of positive buck-boost converter against input electronic converter. Int. J. Ind. Electr. Drives 5(1): 49–55
voltage and load current disturbances. Aust. J. Electr. Electr. [21] Borin L C, Mattos E, Osorio C R, Koch G G and Montagner
Eng. 6(2): 165–178 V F 2019 Robust PID controllers optimized by PSO
[6] Chen Z, Hu J and Gao W 2010 Closed-loop analysis and algorithm for power converters. In: 2019 IEEE 15th Brazil-
control of a non-inverting buck–boost converter. Int. J. Con- ian Power Electronics Conference and 5th IEEE Southern
trol 83(11): 2294–2307 Power Electronics Conference. pp. 1–6
222 Page 18 of 18
[22] Chanjira P and Tunyasrirut S 2020 Intelligent control using
metaheuristic optimization for buck-boost converter. J. Eng.
2: 744
[23] Izci D, Ekinci S and Hekimoğlu B 2022 A novel modified Lévy
flight distribution algorithm to tune proportional, integral,
derivative and acceleration controller on buck converter system.
Trans. Inst. Measur. Control 44(2): 393–409
[24] Verma P, Patel N, Nair N K C and Sikander A 2016. Design
of PID controller using cuckoo search algorithm for buck-
boost converter of LED driver circuit. In: 2016 IEEE 2nd
Annual Southern Power Electronics Conference, pp. 1–4
[25] Izci D and Ekinci S 2022 A novel improved version of
hunger games search algorithm for function optimization and
efficient controller design of buck converter system. e-
Prime-Adv. Electr. Eng. Electr. Energy 2: 100039
[26] Ortatepe Z and Karaarslan A 2020 Pre-calculated duty cycle
optimization method based on genetic algorithm imple-
mented in DSP for a non-inverting buck-boost converter. J.
Power Electr. 20(1): 34–42
[27] Sivamani D, Shyam D, Ali A N, Premkumar K, Narendiran S
and Alexander S A 2021 Solar Powered Battery Charging
System Using Optimized PI Controller for Buck Boost
converter. In: IOP Conference Series: Materials Science and
Engineering, p. 012151
[28] Valarmathi K, Arundevi M and Mahendran R 2015 Real
coded genetic algorithm based improvement of efficiency in
interleaved boost converter. Int. J. Power Electron. Drive
Syst. 5(4): 529
[29] Gu X, Wang X, Liu Z, Zha W, Xu X and Zheng M 2020 A
multi-objective optimization model using improved NSGA-
II for optimizing metal mines production process. IEEE
Access 8: 28847–28858
[30] Versele C, Deblecker O and Lobry J 2011 Multiobjective
optimal choice and design of isolated dc-dc power convert-
ers. In: Proceedings of the 2011 14th European Conference
on Power Electronics and Applications, pp. 1–10
[31] Dell’Isola D, Urbain M, Weber M, Pierfederici S and
Meibody-Tabar F 2019 Optimal design of a DC–DC boost
converter in load transient conditions, including control
strategy and stability constraint. IEEE Trans. Transp. Electr.
5(4): 1214–1224
[32] Dell’Isola D, Urbain M, Weber M, Pierfederici S and
Meibody-Tabar F 2019 Optimal design of a DC–DC boost
converter in load transient conditions, including control
strategy and stability constraint. IEEE Trans. Transp. Electr.
5(4): 1214–1224
[33] Bharti M. and Jindal H 2019 Modified genetic algorithm for
resource selection on internet of things. In: International
Conference on Futuristic Trends in Networks and Computing
Technologies, pp. 164–176
[34] Bagis A 2007 Determination of the PID controller param-
eters by modified genetic algorithm for improved perfor-
mance. J. Inform. Sci. Eng. 23(5): 1469–1480
[35] Jeyadevi S, Baskar S, Babulal C K and Iruthayarajan M W
2011 Solving multiobjective optimal reactive power dispatch
using modified NSGA-II. Int. J. Electr. Power Energy Syst.
33(2): 219–228
[36] Dhanalakshmi S, Kannan S, Mahadevan K and Baskar S
2011 Application of modified NSGA-II algorithm to com-
bined economic and emission dispatch problem. Int. J. Elect.
Power Energy Syst. 33(4): 992–1002
Sådhanå (2022)47:222
[37] Ramesh S, Kannan S and Baskar S 2012 Application of
modified NSGA-II algorithm to multi-objective reactive
power planning. Appl. Soft Comput. 12(2): 741–753
[38] Kalaivani L, Subburaj P and Iruthayarajan M W 2013 Speed
control of switched reluctance motor with torque ripple
reduction using non-dominated sorting genetic algorithm
(NSGA-II). Int. J. Electr Power Energy Syst. 53: 69–77
[39] Rajesh R and Baranilingasen I 2022 Modeling and analysis
of different tuning methodologies of PID controller for a
linearly parameterized non linear system. Int. J. Sci. Adv.
Res. Tech. 3(5): 615–620
[40] Rajamani M P E, Rajesh R and Willjuice Iruthayarajan M
2021 Design and experimental validation of PID controller
for buck converter: a multi-objective evolutionary algorithms
based approach. IETE J. Res. 2: 1–12
[41] Marler R T and Arora J S 2004 Survey of multi-objective
optimization methods for engineering. Struct. Multi. Optim.
26(6): 369–395
[42] Kou G, Xiao H, Cao M and Lee L H 2021 Optimal
computing budget allocation for the vector evaluated genetic
algorithm in multi-objective simulation optimization. Auto-
matica 129: 109599
[43] Murata T and Ishibuchi H 1995 MOGA: multi-objective
genetic algorithms. In: IEEE Inter. Conference on Evolu-
tionary Computation, pp. 289–294
[44] Deb K and Goel T 2001 Controlled elitist non-dominated
sorting genetic algorithms for better convergence. In:
Interernational Conference on Evolutionary Multi-Criterion
Optimization, pp. 67–81
[45] Horn J, Nafpliotis N and Goldberg D E 1994 A niched Pareto
genetic algorithm for multiobjective optimization. In: Pro-
ceedings of the first IEEE Conference on Evolutionary
Computation. IEEE world congress on computational intel-
ligence, pp. 82–87
[46] Jiang S and Yang S 2017 A strength Pareto evolutionary
algorithm based on reference direction for multiobjective
and many-objective optimization. IEEE Trans. Evolut.
Comput. 21(3): 329–346
[47] Knowles J and Corne D 1999 The pareto archived evolution
strategy: A new baseline algorithm for pareto multiobjective
optimisation. In: Proceedings of the 1999 Congress on
Evolutionary Computation, pp. 98–105
[48] Kuriakose S and Shunmugam M S 2005 Multi-objective
optimization of wire-electro discharge machining process by
non-dominated sorting genetic algorithm. J. Mater. Process.
Technol. 170: 133–141
[49] Deb K, Pratap A, Agarwal S and Meyarivan T A M T 2002 A
fast and elitist multiobjective genetic algorithm: NSGA-II.
IEEE Trans. Evol. Comput. 6(2): 182–197
[50] Luo B, Zheng J, Xie J and Wu J 2008 Dynamic crowding
distance? A new diversity maintenance strategy for MOEAs.
In: 2008 Fourth International Conference on Natural
Computation, pp. 580–585
[51] Basso C 2008 The link between the phase margin and the
converter transient response. ON Semiconductor
[52] Erickson R W and Maksimovic D 2007 Fundamentals of
power electronics. Springer, Berlin