VLSI Design 18EC2

Module 2
Fabrication
The VLSI Design Funnel
$, €, ¥, £
• Engineering a VLSI Chip is an Marketing
extremely complex task. Sand CAD
Idea Engineers
• This views the process as one
where we provide the basic
necessities such as money, VLSI Design Funnel
an idea, and marketing info
and dump them all into a
“magic technology funnel”.
• With adding a pile of sand as
a raw material produces the
“Super Chip”. Super Chip

Referenced from- Introduction to VLSI Circuits and Systems by John. P. Uyemura

2
Silicon Wafer
• In electronics, a
wafer (also called a
slice or substrate )
is a thin slice of
semiconductor
material, such as a
silicon crystal,
used in the
fabrication of
integrated circuits
and other micro-
devices.
3
 Fabrication Process
1. Wafer Preparation.
• Takes care of electrical and mechanical properties of the wafer, which depends
on orientation of the crystalline plane.
2. Oxidation.
• Is the chemical process of silicon reacting with oxygen to form silicon-dioxide.
• Two types of oxidation,
• Dry Oxidation (high purity gas) - gives better electrical characteristic.
• Wet Oxidation (passing as a steam) - which gives faster growth rate.
3. Diffusion.
• Is a method by which to introduce impurity atoms into silicon to change its
resistivity.
4. Ion Implantation.
• Is the alternate method used to introduce impurity atoms into the semiconductor
crystal.
5. Chemical Vapour Deposition.
• Is a process by which gases or vapour’s are chemically reacted leading to the
formation of solids on a substrate.
4
Cont…
6. Photo-lithography.
• The surface geometry of the various IC
components is defined photolithographically.
• Two type of Photoresists,
• Positive Photoresist - The exposed area will be
softened and can be removed.
• Negative Photoresist - The exposed area will
be hardened and is retained, rest unexposed
area is removed.
7. Metallisation.
• Is the process to interconnect the various
components.
5
 Wafer Formation
• The basic raw material used in CMOS fabs is a wafer or disk of
silicon, roughly 75 mm to 300 mm (12”-- a dinner plate!) in
diameter and less than 1 mm thick.
• Wafers are cut from boules, cylindrical ingots of single-crystal
silicon, that have been pulled from a crucible of pure molten
silicon.
• This is known as the Czochralski method and is currently the most
common method for producing single-crystal material.
• Controlled amounts of impurities are added to the melt to
provide the crystal with the required electrical properties.
• A seed crystal is dipped into the melt to initiate crystal growth.
• A graphite radiator heated by radio-frequency induction
surrounds the quartz crucible and maintains the temperature a
few degrees above the melting point of silicon (1425°C).
 Photolithography

• A photomask is constructed with chromium (chrome) covered quartz glass. A UV

light source is used to expose the photoresist.
• The photomask has chrome where light should be blocked.
• The UV light floods the mask from the backside and passes through the clear
sections of the mask to expose the organic photoresist (PR) that has been coated
on the wafer.
• A developer solvent is then used to dissolve the soluble unexposed photoresist,
leaving islands of insoluble exposed photoresist. This is termed a negative
photoresist.
• A positive resist is initially insoluble, and when exposed to UV becomes soluble.
Positive resists provide for higher resolution than negative resists, but are less
sensitive to light.
Photolithography
 Well and Channel Formation

• Wells and other features require regions of doped silicon. Varying

proportions of donor and acceptor dopants can be achieved using epitaxy,
deposition, or implantation.
• Epitaxy involves growing a single-crystal film on the silicon surface (which is
already a single crystal) by subjecting the silicon wafer surface to an elevated
temperature and a source of dopant material.
• Deposition involves placing dopant material onto the silicon surface and
then driving it into the bulk using a thermal diffusion step. This can be used
to build deep junctions.
• A step called chemical vapor deposition (CVD) can be used for the
deposition.
• CVD occurs when heated gases react in the vicinity of the wafer and produce
a product that is deposited on the silicon surface. CVD is also used to lay
down thin films of material later in the CMOS process.
Cont…
• Ion implantation involves bombarding the silicon substrate with highly
energized donor or acceptor atoms.
• When these atoms impinge on the silicon surface, they travel below the
surface of the silicon, forming regions with varying doping
concentrations.
• At elevated temperature (>800 °C) diffusion occurs between silicon
regions having different densities of impurities, with impurities tending
to diffuse from areas of high concentration to areas of low concentration.
• Ion implantation is the standard well and source/drain implant method
used today.
• The placement of ions is a random process, so doping levels cannot be
perfectly controlled, especially in tiny structures with relatively small
numbers of dopant atoms.
 Silicon Dioxide
Oxidation of silicon is achieved by heating silicon wafers in an oxidizing
atmosphere.
The following are some common approaches:
• Wet oxidation––when the oxidizing atmosphere contains water vapor. The
temperature is usually between 900 ° C and 1000°C. This is also called pyrogenic
oxidation when a 2:1 mixture of hydrogen and oxygen is used. Wet oxidation is a
rapid process.
• Dry oxidation––when the oxidizing atmosphere is pure oxygen. Temperatures
are in the region of 1200 ° C to achieve an acceptable growth rate. Dry oxidation
forms a better quality oxide than wet oxidation. It is used to form thin, highly
controlled gate oxides, while wet oxidation may be used to form thick field
oxides.
• Atomic layer deposition (ALD)––when a thin chemical layer (material A) is
attached to a surface and then a chemical (material B) is introduced to produce
a thin layer of the required layer (i.e., SiO2––this can also be used for other
various dielectrics and metals). The process is then repeated and the required
layer is built up layer by layer.
Other CMOS Technologies
• Well and Channel Formation
• Isolation
• Gate Oxide
• Gate and Source/Drain Formations
• Contacts and Metallization
• Passivation

Refer: CMOS VLSI Design by Neil Weste

Section 3.2.1 to 3.2.10
nMOS Fabrication Steps

13
CMOS Fabrication
• Two types
• N-Well (P-Type Substarte)
• P-Well (N-Type Substrate)
Fabrication Steps
❑Start with blank wafer
❑Build inverter from the bottom up
❑First step will be to form the n-well
• Cover wafer with protective layer of SiO2 (oxide)
• Remove layer where n-well should be built
• Implant or diffuse n dopants into exposed wafer
• Strip off SiO2

1
Fabrication and Layout
5
Oxidation
❑Grow SiO2 on top of Si wafer
• 900 – 1200 C with H2O or O2 in oxidation furnace

1
Fabrication and Layout
6
Photoresist
❑Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light

1
Fabrication and Layout
7
Lithography
❑Expose photoresist through n-well mask
❑Strip off exposed photoresist

1
Fabrication and Layout
8
Etch
❑Etch oxide with hydrofluoric acid (HF)
• Seeps through skin and eats bone; nasty stuff!!!
❑Only attacks oxide where resist has been exposed

1
Fabrication and Layout
9
Strip Photoresist
❑Strip off remaining photoresist
• Use mixture of acids called piranah etch
❑Necessary so resist doesn’t melt in next step

2
Fabrication and Layout
0
n-well
❑n-well is formed with diffusion or ion implantation
❑Diffusion
• Place wafer in furnace with arsenic gas
• Heat until As atoms diffuse into exposed Si
❑Ion Implanatation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si

2
Fabrication and Layout
1
Strip Oxide
❑Strip off the remaining oxide using HF
❑Back to bare wafer with n-well
❑Subsequent steps involve similar series of steps

2
Fabrication and Layout
2
Polysilicon
❑Deposit very thin layer of gate oxide
• < 20 Å (6-7 atomic layers)
❑Chemical Vapor Deposition (CVD) of silicon layer
• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysilicon
• Heavily doped to be good conductor

2
Fabrication and Layout
3
Polysilicon Patterning
❑Use same lithography process to pattern
polysilicon

2
Fabrication and Layout
4
Self-Aligned Process
❑Use oxide and masking to expose where n+
dopants should be diffused or implanted
❑N-diffusion forms nMOS source, drain, and n-well
contact

2
Fabrication and Layout
5
N-diffusion
❑Pattern oxide and form n+ regions
❑Self-aligned process where gate blocks diffusion
❑Polysilicon is better than metal for self-aligned
gates because it doesn’t melt during later
processing

2
Fabrication and Layout
6
N-diffusion
❑Historically dopants were diffused
❑Usually ion implantation today
❑But regions are still called diffusion

2
Fabrication and Layout
7
N-diffusion
❑Strip off oxide to complete patterning step

2
Fabrication and Layout
8
P-Diffusion
❑Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

2
Fabrication and Layout
9
Contacts
❑Now we need to wire together the devices
❑Cover chip with thick field oxide
❑Etch oxide where contact cuts are needed

3
Fabrication and Layout
0
Metallization
❑Sputter on aluminum over whole wafer
❑Pattern to remove excess metal, leaving wires

3
Fabrication and Layout
1