Name and RegNumber: Harsh raj 21BEE0001 Assessment Number: 6

Course: BEEE206P- Digital Electronics Date:20-9-2022

Title: To design and verify the half adder using 4:1 multiplexer

Aim
verification of half adder truth table using 4:1 Multiplexers.

Apparatus / Components
Name of items Specification quantity
Digital IC’S 74158 1
LED 2
.
Resistor 330ohm 2
rps (0-5v)DC 1
breadboard 1

Theory
Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the control of
selection signals.Multiplexer means many to one. A multiplexer is a circuit with many inputs
but only one output. By using control signals (select lines) we can select any input to the
output. Multiplexer is also called as data selector because the output bit depends on the input
data bit that is selected. The general multiplexer circuit has 2n input signals, n control/select
signals and 1 output signal.

Four-to-One Multiplexer
In 4:1 MUX, there will be 4 input lines and 1 output line. And to control which input should
be selected out of these 4, we need 2 selection lines.
Thus, it is evident from the diagram below that D0, D1, D2 and D3 are the input lines and
A, B are the two selection lines. The combination of binary numbers given as a selection line
will determine the output of the MUX.
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Picture of Circuit Diagram(s)

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Snapshot of lab work

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Procedure
• Plug in the IC to the breadboard.

• There are 16 pins in the IC 74158.

• Connect pins 1 and 15 to ground and pin number 16 to Vcc

• We get outputs at pin numbers 7 and 9. So connect a resistor(330 ohm) and LED at each
position.

• As we are doing half adder in multiplexer,we take inputs at pin number 2 and 14.

• We connect the other pins depending on the truth table of half adder. Sum and Cout.

• As for sum, it is 0,1,1,0. So pins 3 and 6 are connected to ground and pins 4,5 are
connected to Vcc.

• For Cout, it is 0,0,0,1. So pins 10,11,12 are connected to ground and pin number 13 to
Vcc.

• Change the inputs to see different outputs.

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Tabulations
a b sum carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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Analysis

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Result
We have successfully able to realize logic of half adder using IC 74158 which is 4:1 multiplexer.

Inference
We understand the operation of 4:1 mux and have verified its truth table for half adder.

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Name and RegNumber: Harsh raj 21BEE0001 Assessment Number: 7
Course: BEEE206P- Digital Electronic Date: 24-9-2022
Title: Design and implementation of magnitude comparators using logic gates.

Aim
To design and setup single bit comparator using logic gates and verify the truth table.

Apparatus / Components
Name of items Specification quantity
Digital IC’S 7408,7486,7404 Each one
LED 1
Resistor 330ohm 3
rps (0-5v)DC 1
breadboard 1

Theory
A magnitude digital comparator is a combinational circuit that compares two digital or binary
numbers in order to find out whether one binary number is equal, less than or greater than the
other binary number. We logically design a circuit for which we will have two inputs one for
A and other for B and have three output terminals, one for A ¿ B condition, one for A = B
condition and one for A ¡ B condition. A comparator used to compare two bits is called a single
bit comparator. It consists of two inputs each for two single bit numbers and three outputs to
generate less than, equal to and greater than between two binary numbers.
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Picture of Circuit Diagram(s)

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Snapshot of lab work

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Procedure
• Plug the chips you will be using into the breadboard.

• Point all the chips in the same direction with pin1 at the upper left corner.

• Connect +5v and GND pins of each chip to the power and ground bus strips on the
breadboard.

• Make the connection as per circuit diagram.

• Switch on vcc and apply various combination of input according to truth table.

• Connect pin no 7 to ground.

• Connect pin 14 to vcc.

• Connect the circuit according to the given diagram.

• Verify the Truth Table and observe the outputs.

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Tabulations
a b b greater than a a equal to b a greater than b
0 0 0 1 0
0 1 1 0 0 .
1 0 0 0 1
1 1 0 1 0

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Analysis / Calculations

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Result
We have successfully able to realize logic of 1-bit magnitude comparator using AND,XOR,NOT
gates.

Inference
We understand the operation of a single bit comparator and have verified its truth table.

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Name and RegNumber: Harsh raj 21BEE0001 Assessment Number: 8
Course: BEEE206P- Digital Electronic Date: 27-9-2022
Title: To design and verify the priority encoder

Aim
To design and verify priority encoder and its truth table

Apparatus / Components
Vivado Software.

Theory
A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller
number of outputs. The output of a priority encoder is the binary representation of the index of
the most significant activated line, starting from zero. They are often used to control interrupt
requests by acting on the highest priority interrupt input. If two or more inputs are given at
the same time, the input having the highest priority will take precedence.[1] An example of a
single bit 4 to 2 encoder is shown, where highest-priority inputs are to the left and ”x” indicates
an irrelevant value - i.e. any input value there yields the same output since it is superseded by
higher-priority input. The output V indicates if the input is valid.
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Picture of Circuit Diagram(s)

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Snapshot of lab work

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Snapshot of lab work

Procedure
Procedure
• Open Vivado and create a new project.

• Give a project name and select Artix A-7 from the boards component for simulation.

• Then the project will be opened. Create a design file and give the input [3:0]w by
activating the bus(MSB-3,LSB-0) and outputs as v and y(For y, MSB-1,LSB-0).

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• A file will be created will the necessary inputs and outputs. Write the required code.
Make sure that output y is registered.

• After writing a design code, create a simulation file with no inputs and outputs.

• This will be our test bench. Write the required code for test bench and run the simulation.

• Make sure that both design file and it’s corresponding simulation file are in top module.

• After running the simulation, you obtain a graph.

Tabulations
w3 w2 w1 w0 y1 y0 v
0 0 0 0 x x 0
x x x 1 0 0 1
x x 1 0 0 1 1
x 1 0 0 1 0 1
1 0 0 0 1 1 1

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Graph [Simulation]

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Analysis / Calculations

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Analysis / Calculations

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Result
Analyzation of the priority encoder has been done and it has been verified.

Inference
We understand the operation of a priority encoder and have verified its truth table.

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Name and RegNumber: Harsh raj 21BEE0001 Assessment Number: 9
Course: BEEE206P- Digital Electronics Date: 18-10-2022
Title: Design and verification of shift registers using Verilog HDL.

Aim
To design and verify shift registers(PISO and PIPO) using Verilog HDL.

Apparatus / Components
Vivado Software

Theory
Shift Registers
We know that a Flip flop is used to store a single binary data bit but if we want to store
multiple data bits then several FFs are required. So a shift register includes a set of FFs used
for storing multiple data bits by connecting them serially. The data which is stored in these
registers can be shifted by using CLK signals. The shift registers which are used for shifting the
data bits to left are known as SLR or Shift left register whereas the data bits that are shifted
to the right side are known as SRR or Shift right register. We know that these registers are
classified into different types like SISO, SIPO, PISO, and PIPO.

PISO shift register

The shift register which uses parallel input and generates serial output is known as the parallel
input serial output shift register or PISO shift register. This shift register works in a reverse
way to the SIPO shift register. In this type of shift register, the input data enters a parallel
way and comes out serially. So the i/p of the second FF is the o/p of the first flip flop.

PIPO shift register

The shift register which uses parallel input and generates parallel output is known as the parallel
input parallel output shift register. This shift register includes three connections only the PI
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(parallel i/p), PO (parallel o/p) the CLK signal. This kind of shift register also works like a
time delay device or temporary storage device like a SISO shift register with the time delay
being changed through the CLK signals frequency.
In this type of register, the data is available in parallel format with respect to the parallel
i/p pins like PA to PD after that, it is transferred directly together to their respective o/p
pins from QA to QDby the similar CLK signal. After that single CLK signal will load unload
the shift register.

Picutre of Circuit Diagrams

PISO shift register

PIPO shfit register

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Snapshot of lab work

PISO

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PIPO

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Procedure
• Open Vivado and create a new project.

• Give a project name and select Artix A-7 from the boards component for simulation.

• For PISO shift register:

The project will be opened. Create a design file and give the inputs as clk,SL,rst and
output as S0.

Also take an input D with MSB 3 and LSB 0(Bus).

A file will be created will the necessary inputs and outputs.

Register another parameter with MSB 3 and LSB 0(Bus) as q.

After writing a design code, create a simulation file with no inputs and outputs.

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This will be our test bench. Write the required code for test bench and run the simulation.

Make sure that both design file and it’s corresponding simulation file are in top mod-
ule.

After running the simulation, you obtain an output.

• For PIPO shift register:

The project will be opened. Create a design file and give the inputs as clk,rst and output
as [3:0]q.

Also take an input D with MSB 3 and LSB 0(Bus).

A file will be created will the necessary inputs and outputs.

Make sure q is registered.

After writing a design code, create a simulation file with no inputs and outputs.

This will be our test bench. Write the required code for test bench and run the simulation.

Make sure that both design file and it’s corresponding simulation file are in top mod-
ule.

After running the simulation, you obtain an output.

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Analysis / Calculations
PIPO

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PISO

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Verified outputs
PIPO GRAPH

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PISO GRAPH

Result
We successfully verified the logic of PIPO and PISO shift registers and obtained the output
using Vivado software.

Inference
We understand the operation of a PISO and PIPO shift register and have verified its truth
table.

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Name and RegNumber: Harsh raj 21BEE0001 Assessment Number: 10
Course: BEEE206P- Digital Electronics Date: November 1, 2022
Title: Design and verification of up down counter using Verilog HDL.

Aim
To design and verify up down counter using verilog HDL.

Apparatus / Components
Vivado Software

Circuit diagram

Theory
Counter
In digital logic computing, a sequential circuit that is used to count pulses is called a counter.
A counter is a set of FFs including an applied CLK signal and this is the broad application
of FFs. These are designed as separate ICs (integrated circuits) to use extensively in digital
circuits and also in larger ICs. Counters are available in different types like Johnson counter,
asynchronous or ripple, synchronous counter, decade, ring, and Up/Down counter.
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Up down counter
The up/Down counter is also known as the bidirectional counter which is used to count in any
direction based on the condition of the input control pin. These are used in different appli-
cations to count up from zero to provide a change within the output condition on attaining a
fixed value others count down from a fixed value to zero to give an output condition change.

The circuit diagram of the 3-bit up/down counter is shown below. This circuit is designed
with flip-flops. In the up counter, every flip-flop is activated through the normal o/p of the
previous FF (from ‘Q’ o/p of primary flip-flop to the next FF’s CLK); while in a down-counter,
every flip-flop is activated through the complement o/p of the previous FF (from the output of
first FF to CLK of next FF).

Snapshot of lab work

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Procedure
• Open Vivado and create a new project.

• Give a project name and select Artix A-7 from the boards component for simulation.

• Then the project will be opened. Create a design file and give the inputs as rst,clk,ud.

• Take an output which have MSB 3 and LSB 0(Activate bus). Give that output name q.

• A file will be created with the necessary inputs and outputs. Write the code.

• Make the output reg after opening design code.

• After writing a design code, create a simulation file with no inputs and outputs.

• This will be our test bench. Write the required code for test bench and run the simulation.

• Make sure that both design file and it’s corresponding simulation file are in top module.

• After running the simulation, you obtain an output.

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GRAPH

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Verified outputs

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Result
We successfully verified the logic of up down counter and obtained the output using Vivado
software.