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A B C D E

1 1

Compal confidential
BAP00 schematic document
2 Sky Lake-H paltform with nVIDIA N17E-G1 2

Kaby Lake-H paltform with nVIDIA N17E-G1


Kaby Lake-H paltform with nVIDIA N17P-G0-B/N17P-G1-B
Rev: 1.0(A00) PVT
2016/09/05(BOM 2016/09/06)
@ : Nopop component
EMI@ / @EMI@ : EMI pop / unpop part PR8211 PR8211

3
ESD@ / @ESD@ : ESD pop / unpop part 3

34.8K_0402_1% 30K_0402_1%
RF@ / @RF@ : RF pop / unpop part SAMSUNG@ MICRON@

CONN@ : Connector component PR8215 PR8215

CMC@ : CMC debug


TBT@ : Thunderbolt 52.3K_0402_1% 68.1K_0402_1%

PD@ : Thunderbolt PD
SAMSUNG@ MICRON@

SKL@ : Sky lake CPU


KBL@ : Kaby lake CPU DAX PCB
DAX PCB

N17E@ : N17E-G1
N17P@ : N17P-G1-B / N17P-G0-B DAZ18F00101
4
DAZ18F00100 PCB 18F LA-B752P REV0 M/B 8 4
PCB 18F LA-B752P REV0 M/B 8
R3@
R1@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 1 of 80
A B C D E
A B C D E

Block Diagram
eDP panel eDP 1.3
P25
1 1

P46~54
65W dGPU
nVIDIA N17E-G1 PEG x8
Mini DP DP 1.3 nVIDIA N17P-G1-B
P26 port8~15
nVIDIA N17P-G0-B
6pcs GDDR5 192bit
Intel
HDMI 2.0
P27
HDMI 2.0
4pcs GDDR5 128bit Kaby Lake-H Memory Bus Dual Channel
1.2V DDR4 1866/2133MHz DDR4-SODIMM x2
DDI 1
BGA 1440
CIO/USB3.1
USB3.1 Thunderbolt DDI 2 P14~15

TypeC Alpine Ridge-SP


PEG x4
P58 USB PD SN1508014
P58 I2C/USB2 P56~57 port0~3

P7~13

DMI x 4

USB2.0 port4
2 AlienFX / ELC , C8051F383 P37 2

USB2.0 port6
PEG x4 Touch screen P25
port4~7
DS80PCI402
P41 USB2.0 port7
Caldera IR camera(with digital MIC) P25
USB3.0 port3
connector USB3.0 port1
USB2.0 port3 JUSB1 , left side
USB2.0 port1 P35
P41 Type A with Powershare
USB3.0 port4
USB2.0 port2 JUSB2 , right side , type A P35
RJ45 LAN(Gigabit) PCI-E port5
connector P30 Killer E2500
P30
Intel USB3.0 port2,5 JUSBC2 , right side
PCH-H,HM170 USB2.0 port8 Type C USB 3.0 with power delivery
PCI-E port6 P36
NGFF (M.2)
WLAN+BTP28 USB2.0 port5
BGA 837
digital MIC
3 3

NGFF (M.2) PCI-E port 9~12


SSD 1 P29 SATA3.0 port0
JACK1 : Global headset P31
Audio codec
HDA Realtek
NGFF (M.2) PCI-E port 13~16
SSD 2 P29 SATA3.0 port3 ALC3266
Jack2 : Re-tasking P31
P31
SPI ROM SPI
128Mbit P17

PS2/SMBus AMP
Touch pad P38 P16~22 Speaker
ALC1309 P32
P32
DC in 1.00V dGPU LPC Bus
Battery Core

3V/5V 2.5V Charger KC3810


P43
4 ENE KB9022 KB P40 4

KC3810
P43 P43
System CPU dGPU
1.2V Vcore 1.35V

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 2 of 80
A B C D E
A

Board ID Table for AD channel PCH-H , HM170


Vcc 3.3V +/- 1% HSIO USB3 PCIe SATA3 Function USB2 Function
Ra 100K +/- 1%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 1 1 JUSB1,type A 1 JUSB1(Powershare)
0 0 0.000V 0.000V 0.300V 0x00 - 0x13 2 2 JUSB3,type C 2 JUSB2
1 12K +/- 1% 0.347V 0.354V 0.360V 0x14 - 0x1E
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1F - 0x25 3 3 Caldera 3 Caldera
3 20K +/- 1% 0.541V 0.550V 0.559V 0x26 - 0x30 4 4 JUSB2,type A 4 ELC
4 27K +/- 1% 0.691V 0.702V 0.713V 0x31 - 0x3A
5 33K +/- 1% 0.807V 0.819V 0.831V 0x3B - 0x45 5 5 JUSB3,type C 5 Bluetooth
6 43K +/- 1% 0.978V 0.992V 1.006V 0x46 - 0x54 6 6 6 Touch screen
7 56K +/- 1% 1.169V 1.185V 1.200V 0x55 - 0x64
8 75K +/- 1% 1.398V 1.414V 1.430V 0x65 - 0x76 7 7 1 7 Camera
9 100K +/- 1% 1.634V 1.650V 1.667V 0x77 - 0x87 8 8 2 8 JUSB3
10 130K +/- 1% 1.849V 1.865V 1.881V 0x88 - 0x96
11 160K +/- 1% 2.015V 2.031V 2.046V 0x97 - 0xA4 9 9 3 9
12 200K +/- 1% 2.185V 2.200V 2.215V 0xA45- 0xAF 10 10 4 10
13 240K +/- 1% 2.316V 2.329V 2.343V 0xB0 - 0xB7
14 270K +/- 1% 2.395V 2.408V 2.421V 0xB8 - 0xBF 11 5 LAN 11
15 330K +/- 1% 2.521V 2.533V 2.544V 0xC0 - 0xC9 12 6 WLAN 12
16 430K +/- 1% 2.667V 2.677V 2.687V 0xCA - 0xD4
17 560K +/- 1% 2.791V 2.800V 2.808V 0xD5 - 0xDD 13 7 13
18 750K +/- 1% 2.905V 2.912V 2.919V 0xDE - 0xF0 14 8 14
19 NC 3.000V 3.300V 3.300V 0xF1 - 0xFF
15 9 0
JSSD1 Board ID TABLE
16 10 1 M.2 2280 ID SKL KBL
1
Voltage Rails 17 11 SATA 0 EVT 1

Power Plane Descript i on S0 S3 S4 / S5 PCIe x4 1 DVT1 EVT


18 12
VIN Adapter power supply N/A N/A N/A 2 DVT1.1
BATT+ Bat t er y po wer s uppl y N/A N/A N/A 19 13 0 3 DVT2
B+ AC or bat t er y po wer r ail f or po wer ci rc ui t N/A N/A N/A JSSD2 4 GC6
20 14 1 M.2 2280
+VCC_CORE Core voltage for CPU ON OFF OFF 5 MP
+VCCGT Sliced graphics power rail ON OFF OFF 21 15 2 SATA 6 DVT1
+0.6VS DDR4 +0.6VS power rail for DDR terminator ON OFF OFF PCIe x4 7 DVT2
22 16 3
+1VALW System +1VALW power rail ON ON ON* 8 DVT2.1/GC6

+1V_PCH_PRIM System +1VALW power rail ON ON ON* 9 MP


+VCCIO +1.0VS IO power rail ON OFF OFF
+PEX_VDD +1.0VS power rail for GPU ON OFF OFF Part No. Name BOM
+1.35VS_VGA +1.35~1.55VS power rail for GPU ON OFF OFF 431A3131L01 SKL I5 G1 DIS 6G SKL@, N17E@ ,TBT@, PD@, CMC@, EMI@, ESD@, RF@, CONN@
+1.2V_DDR DDR4 +1.2V power rail ON ON OFF 431A3131L02 SKL I7 G1 DIS 6G SKL@, N17E@ ,TBT@, PD@, CMC@, EMI@, ESD@, RF@, CONN@
+VCCST +1.0V power rail for CPU ON ON OFF 431A3131L03 KBL I5 G1 DIS KBL@, N17E@ ,TBT@, PD@, CMC@, EMI@, ESD@, RF@, CONN@
+VCCSTG +1.0VS power rail for CPU ON OFF OFF 431A3131L04 KBL I7 G1 DIS KBL@, N17E@ ,TBT@, PD@, CMC@, EMI@, ESD@, RF@, CONN@
+3VALW System +3VALW always on power rail ON ON ON*
+3VLP +19VB to +3VLP power rail for suspend power ON ON ON
+3V_PCH +3VALW power for PCH DSW rails ON ON ON*
+LAN_IO +3VALW power for LAN power rails ON ON ON* Symbol Note :
+3VS System +3VS power rail ON OFF OFF
+1V8_AON +1.8VS power rail for GPU ON OFF OFF
+3V3_SYS +3VS power rail for GPU ON OFF OFF Digital Ground
+5VALW System +5VALW power rail ON ON ON*
+5VS System +5VS power rail ON OFF OFF
+RTC_CELL RTC power ON ON ON
Analog Ground
+VCCSA System Agent power rail ON OFF OFF
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes list
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 4 of 80
A
5 4 3 2 1

D D

JPCMC CMC_DEBUG_36P
+1VALW
OBS DATA JTAG/RC/HOOKS

+3V_PCH 1 22
<9> CFG0 3 DATA_0 VCCOBS_AB
<9> CFG1 5 DATA_1
1 CMC@ 2 1K_0402_5% XDP_SPI_SI <9> CFG2 7 DATA_2
RC9
C <9> CFG3 9 DATA_3 28 C
<9> CFG4 11 DATA_4 XDP_TRST* 29 CPU_XDP_TRST# <9,22>
<9> CFG5 13 DATA_5 XDP_TDI 30 XDP_TDI <9,18>
<9> CFG6 15 DATA_6 XDP_TMS 32 PCH_JTAG_TCK XDP_TMS <9,18>
<9> CFG7 DATA_7 XDP_TCK0 31 XDP_TCK PCH_JTAG_TCK <9,18>
17 XDP_TCK1 35 XDP_TCK <18>
<9> CFG17 21 DATA_CLK_1P XDP_TDO XDP_TDO <9,18>
<9> CFG16 DATA_CLK_1N 33
+1VALW 2 XDP_PREQ* 34 XDP_PREQ# <9,22>
<9> CFG8 4 DATA_8 XDP_PRDY* XDP_PRDY# <9,22>
<9> CFG9 6 DATA_9 27 XDP_HOOK0 RC355 1 CMC@ 2 1K_0402_1%
1 CMC@ 2 1K_0402_5% XDP_ITP_PMODE <9> CFG10 8 DATA_10 HOOK_0 25 XDP_SPI_SI PCIRST# <17,28,29,30,43,56>
RC353
<9> CFG11 10 DATA_11 HOOK_3 26 XDP_ITP_PMODE XDP_SPI_SI <17>
<9> CFG12 12 DATA_12 HOOK_6 XDP_ITP_PMODE <18>
<9> CFG13 14 DATA_13 24 XDP_SPI_IO2 1 CMC@ 2 1K_0402_1%
RC354
<9> CFG14 16 DATA_14 XDP_PRSNT_PCH* 23 PCH_SPI_WP#_R <17>
<9> CFG15 DATA_15 XDP_PRSNT_CPU*
18 19
<9> CFG19 20 DATA_CLK_2P GND 36
<9> CFG18 DATA_CLK_2N <MT> GND
RC35 2 @ 1 51_0402_1% PCH_JTAG_TCK

RC348 2 CMC@ 1 51_0402_1% XDP_TCK

RH497 1 CMC@ 2 51_0402_5% CPU_XDP_TRST# INTEL_CMC_PRIMARY


CONN@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CMC CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 6 of 80
5 4 3 2 1
5 4 3 2 1

CPU1C SKYLAKE_HALO

BGA1440

E25 B25
<56> PEG_CRX_TTX_P15 PEG_RXP[0] PEG_TXP[0] PEG_CTX_TRX_P15 <56>
D25 A25
<56> PEG_CRX_TTX_N15 PEG_RXN[0] PEG_TXN[0] PEG_CTX_TRX_N15 <56>
E24 B24
<56> PEG_CRX_TTX_P14 PEG_RXP[1] PEG_TXP[1] PEG_CTX_TRX_P14 <56>
F24 C24

D Thunderbolt RX reverse
<56>

<56>
PEG_CRX_TTX_N14

PEG_CRX_TTX_P13
E23
D23
PEG_RXN[1]

PEG_RXP[2]
PEG_TXN[1]

PEG_TXP[2]
B23
A23
PEG_CTX_TRX_N14

PEG_CTX_TRX_P13
<56>

<56>
Thunderbolt TX reverse D
<56> PEG_CRX_TTX_N13 PEG_RXN[2] PEG_TXN[2] PEG_CTX_TRX_N13 <56>
E22 B22
<56> PEG_CRX_TTX_P12 F22 PEG_RXP[3] PEG_TXP[3] C22 PEG_CTX_TRX_P12 <56>
<56> PEG_CRX_TTX_N12 PEG_RXN[3] PEG_TXN[3] PEG_CTX_TRX_N12 <56>
E21 B21 PEG_CTX_GRX_P11 CC24 1 2 0.22U_0201_6.3V
<41> PEG_CRX_GTX_P11 D21 PEG_RXP[4] PEG_TXP[4] A21 PEG_CTX_GRX_N11 PEG_CTX_C_GRX_P11 <41>
CC12 1 2 0.22U_0201_6.3V
<41> PEG_CRX_GTX_N11 PEG_RXN[4] PEG_TXN[4] PEG_CTX_C_GRX_N11 <41>
E20 B20 PEG_CTX_GRX_P10 CC23 1 2 0.22U_0201_6.3V
<41> PEG_CRX_GTX_P10 PEG_RXP[5] PEG_TXP[5] PEG_CTX_C_GRX_P10 <41>
F20 C20 PEG_CTX_GRX_N10 CC11 1 2 0.22U_0201_6.3V

Caldera RX reverse
<41>

<41>
PEG_CRX_GTX_N10

PEG_CRX_GTX_P9
E19
D19
PEG_RXN[5]

PEG_RXP[6]
PEG_TXN[5]

PEG_TXP[6]
B19 PEG_CTX_GRX_P9
A19 PEG_CTX_GRX_N9
CC22 1
CC10 1
2 0.22U_0201_6.3V
2 0.22U_0201_6.3V
PEG_CTX_C_GRX_N10

PEG_CTX_C_GRX_P9 <41>
<41>
Caldera TX reverse
<41> PEG_CRX_GTX_N9 PEG_RXN[6] PEG_TXN[6] PEG_CTX_C_GRX_N9 <41>
E18 B18 PEG_CTX_GRX_P8 CC21 1 2 0.22U_0201_6.3V
<41> PEG_CRX_GTX_P8 PEG_RXP[7] PEG_TXP[7] PEG_CTX_C_GRX_P8 <41>
F18 C18 PEG_CTX_GRX_N8 CC9 1 2 0.22U_0201_6.3V
<41> PEG_CRX_GTX_N8 PEG_RXN[7] PEG_TXN[7] PEG_CTX_C_GRX_N8 <41>
D17 A17 PEG_CTX_GRX_P7 CC20 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_P7 E17 PEG_RXP[8] PEG_TXP[8] B17 PEG_CTX_GRX_N7 PEG_CTX_C_GRX_P7 <46>
CC8 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_N7 PEG_RXN[8] PEG_TXN[8] PEG_CTX_C_GRX_N7 <46>
F16 C16 PEG_CTX_GRX_P6 CC19 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_P6 E16 PEG_RXP[9] PEG_TXP[9] B16 PEG_CTX_GRX_N6 PEG_CTX_C_GRX_P6 <46>
CC7 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_N6 PEG_RXN[9] PEG_TXN[9] PEG_CTX_C_GRX_N6 <46>
D15 A15 PEG_CTX_GRX_P5 CC18 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_P5 PEG_RXP[10] PEG_TXP[10] PEG_CTX_C_GRX_P5 <46>
E15 B15 PEG_CTX_GRX_N5 CC6 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_N5 PEG_RXN[10] PEG_TXN[10] PEG_CTX_C_GRX_N5 <46>
F14 C14 PEG_CTX_GRX_P4 CC17 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_P4 PEG_RXP[11] PEG_TXP[11] PEG_CTX_C_GRX_P4 <46>
E14 B14 PEG_CTX_GRX_N4 CC5 1 2 0.22U_0201_6.3V
PEG RX reverse <46>

<46>
PEG_CRX_GTX_N4

PEG_CRX_GTX_P3
D13
E13
PEG_RXN[11]

PEG_RXP[12]
PEG_TXN[11]

PEG_TXP[12]
A13 PEG_CTX_GRX_P3
B13 PEG_CTX_GRX_N3
CC16 1
CC4 1
2 0.22U_0201_6.3V
2 0.22U_0201_6.3V
PEG_CTX_C_GRX_N4

PEG_CTX_C_GRX_P3
<46>

<46>
PEG TX reverse
<46> PEG_CRX_GTX_N3 PEG_RXN[12] PEG_TXN[12] PEG_CTX_C_GRX_N3 <46>
F12 C12 PEG_CTX_GRX_P2 CC15 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_P2 E12 PEG_RXP[13] PEG_TXP[13] B12 PEG_CTX_GRX_N2 PEG_CTX_C_GRX_P2 <46>
CC3 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_N2 PEG_RXN[13] PEG_TXN[13] PEG_CTX_C_GRX_N2 <46>
D11 A11 PEG_CTX_GRX_P1 CC14 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_P1 E11 PEG_RXP[14] PEG_TXP[14] B11 PEG_CTX_GRX_N1 PEG_CTX_C_GRX_P1 <46>
CC2 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_N1 PEG_RXN[14] PEG_TXN[14] PEG_CTX_C_GRX_N1 <46>
C C
F10 C10 PEG_CTX_GRX_P0 CC13 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_P0 PEG_RXP[15] PEG_TXP[15] PEG_CTX_C_GRX_P0 <46>
E10 B10 PEG_CTX_GRX_N0 CC1 1 2 0.22U_0201_6.3V
<46> PEG_CRX_GTX_N0 PEG_RXN[15] PEG_TXN[15] PEG_CTX_C_GRX_N0 <46>

1 2 PEG_RCOMP G2
+VCCIO PEG_RCOMP
RC2
24.9_0402_1%

D8 B8
<19> DMI_CRX_PTX_P0 E8 DMI_RXP[0] DMI_TXP[0] A8 DMI_CTX_PRX_P0 <19>
<19> DMI_CRX_PTX_N0 DMI_RXN[0] DMI_TXN[0] DMI_CTX_PRX_N0 <19>
E6 C6
<19> DMI_CRX_PTX_P1 F6 DMI_RXP[1] DMI_TXP[1] B6 DMI_CTX_PRX_P1 <19>
<19> DMI_CRX_PTX_N1 DMI_RXN[1] DMI_TXN[1] DMI_CTX_PRX_N1 <19>
D5 B5
<19> DMI_CRX_PTX_P2 DMI_RXP[2] DMI_TXP[2] DMI_CTX_PRX_P2 <19>
E5 A5
<19> DMI_CRX_PTX_N2 DMI_RXN[2] DMI_TXN[2] DMI_CTX_PRX_N2 <19>
J8 D4
<19> DMI_CRX_PTX_P3 DMI_RXP[3] DMI_TXP[3] DMI_CTX_PRX_P3 <19>
J9 B4
<19> DMI_CRX_PTX_N3 DMI_RXN[3] DMI_TXN[3] DMI_CTX_PRX_N3 <19>

3 OF 14
SKL-H_BGA1440
@

SKYLAKE_HALO
CPU1D
BGA1440
K36 D29
<56> CPU_DP1_P0 DDI1_TXP[0] EDP_TXP[0] CPU_EDP_TX0P <24>
K37 E29
B <56> CPU_DP1_N0 DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX0N <24> B
J35 F28
<56> CPU_DP1_P1 J34 DDI1_TXP[1] EDP_TXP[1] E28 CPU_EDP_TX1P <24>
<56> CPU_DP1_N1 DDI1_TXN[1] EDP_TXN[1] CPU_EDP_TX1N <24>
H37 B29
<56> CPU_DP1_P2 H36 DDI1_TXP[2] EDP_TXN[2] A29 CPU_EDP_TX2N <24>
<56> CPU_DP1_N2 DDI1_TXN[2] EDP_TXP[2] CPU_EDP_TX2P <24>
J37 B28
<56> CPU_DP1_P3 DDI1_TXP[3] EDP_TXN[3] CPU_EDP_TX3N <24>
J38 C28
<56> CPU_DP1_N3 DDI1_TXN[3] EDP_TXP[3] CPU_EDP_TX3P <24>
D27 C26
<56> CPU_DP1_AUXP E27 DDI1_AUXP EDP_AUXP B26 CPU_EDP_AUX <24>
<56> CPU_DP1_AUXN DDI1_AUXN EDP_AUXN CPU_EDP_AUX# <24>
H34

Thunderbolt DDI <56>


<56>
<56>
CPU_DP2_P0
CPU_DP2_N0
CPU_DP2_P1
H33
F37
G38
DDI2_TXP[0]
DDI2_TXN[0]
DDI2_TXP[1] EDP_DISP_UTIL
A33
+VCCIO
<56> CPU_DP2_N1 DDI2_TXN[1]
F34
<56> CPU_DP2_P2 DDI2_TXP[2] EDP_RCOMP
F35 D37 1 2
<56> CPU_DP2_N2 E37 DDI2_TXN[2] EDP_RCOMP
<56> CPU_DP2_P3 DDI2_TXP[3]
E36 RC30
<56> CPU_DP2_N3 DDI2_TXN[3] 24.9_0402_1%
F26
<56> CPU_DP2_AUXP DDI2_AUXP
E26
<56> CPU_DP2_AUXN DDI2_AUXN
C34
D34 DDI3_TXP[0]
B36 DDI3_TXN[0]
B34 DDI3_TXP[1]
F33 DDI3_TXN[1]
E33 DDI3_TXP[2]
C33 DDI3_TXN[2]
B33 DDI3_TXP[3]
DDI3_TXN[3] G27
A27 PROC_AUDIO_CLK G25 CPU_DISPA_BCLK <18>
DDI3_AUXP PROC_AUDIO_SDI CPU_DISPA_SDI_R CPU_DISPA_SDO <18>
CPU1 CPU@ B27 G29 1 2
DDI3_AUXN PROC_AUDIO_SDO CPU_DISPA_SDI <18>
4 OF 14 RC66
SKL-H_BGA1440 20_0402_5%
@
A A

SA000097D2L
SKL-H_BGA1440

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(1/7) DMI,PEG,DDI,EDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 7 of 80
5 4 3 2 1
5 4 3 2 1

D D

Interleave
SKYLAKE_HALO SKYLAKE_HALO
CPU1A CPU1B
BGA1440 BGA1440
DDR_A_D0 BR6 AG1 DDR_B_D0 BT11 AM9
DDR_A_D1 DDR0_DQ[0] DDR0_CKP[0] M_CLK_DDR0 <14> DDR_B_D1 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKP[0] M_CLK_DDR2 <15>
BT6 AG2 BR11 AN9
DDR_A_D2 BP3 DDR0_DQ[1] DDR0_CKN[0] AK1 M_CLK_DDR#0 <14> DDR_B_D2 BT8 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[0] AM8 M_CLK_DDR#2 <15>
<14> DDR_A_D[0..63] DDR_A_D3 DDR0_DQ[2] DDR0_CKN[1] M_CLK_DDR#1 <14> DDR_B_D3 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKN[1] M_CLK_DDR#3 <15>
BR3 AK2 BR8 AM7
<14> DDR_A_MA[0..13] DDR_A_D4 BN5 DDR0_DQ[3] DDR0_CKP[1] AL3 M_CLK_DDR1 <14> DDR_B_D4 BP11 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] AM11 M_CLK_DDR3 <15>
<14> DDR_A_DQS#[0..7] DDR_A_D5 DDR0_DQ[4] DDR0_CLKP[2] DDR_B_D5 DDR1_DQ[4]/DDR0_DQ[20] DDR1_CLKP[2]
BP6 AK3 BN11 AM10
<14> DDR_A_DQS[0..7] DDR_A_D6 DDR0_DQ[5] DDR0_CLKN[2] DDR_B_D6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CLKN[2]
BP2 AL2 BP8 AJ10
DDR_A_D7 BN3 DDR0_DQ[6] DDR0_CLKP[3] AL1 DDR_B_D7 BN8 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CLKP[3] AJ11
DDR_A_D8 BL4 DDR0_DQ[7] DDR0_CLKN[3] DDR_B_D8 BL12 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CLKN[3]
DDR_A_D9 BL5 DDR0_DQ[8] AT1 DDR_B_D9 BL11 DDR1_DQ[8]/DDR0_DQ[24] AT8
DDR_A_D10 DDR0_DQ[9] DDR0_CKE[0] DDR_CKE0_DIMMA <14> DDR_B_D10 DDR1_DQ[9]/DDR0_DQ[25] DDR1_CKE[0] DDR_CKE2_DIMMB <15>
BL2 AT2 BL8 AT10
DDR_A_D11 DDR0_DQ[10] DDR0_CKE[1] DDR_CKE1_DIMMA <14> DDR_B_D11 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CKE[1] DDR_CKE3_DIMMB <15>
BM1 AT3 BJ8 AT7
<15> DDR_B_D[0..63] DDR_A_D12 BK4 DDR0_DQ[11] DDR0_CKE[2] AT5 DDR_B_D12 BJ11 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CKE[2] AT11
<15> DDR_B_MA[0..13] DDR_A_D13 DDR0_DQ[12] DDR0_CKE[3] DDR_B_D13 DDR1_DQ[12]/DDR0_DQ[28] DDR1_CKE[3]
BK5 BJ10
<15> DDR_B_DQS#[0..7] DDR_A_D14 BK1 DDR0_DQ[13] AD5 DDR_B_D14 BL7 DDR1_DQ[13]/DDR0_DQ[29] AF11
<15> DDR_B_DQS[0..7] DDR_A_D15 DDR0_DQ[14] DDR0_CS#[0] DDR_CS0_DIMMA# <14> DDR_B_D15 DDR1_DQ[14]/DDR0_DQ[30] DDR1_CS#[0] DDR_CS2_DIMMB# <15>
BK2 AE2 BJ7 AE7
DDR_A_D16 DDR0_DQ[15] DDR0_CS#[1] DDR_CS1_DIMMA# <14> DDR_B_D16 DDR1_DQ[15]/DDR0_DQ[31] DDR1_CS#[1] DDR_CS3_DIMMB# <15>
BG4 AD2 BG11 AF10
DDR_A_D17 BG5 DDR0_DQ[16]/DDR0_DQ[32] DDR0_CS#[2] AE5 DDR_B_D17 BG10 DDR1_DQ[16]/DDR0_DQ[48] DDR1_CS#[2] AE10
DDR_A_D18 BF4 DDR0_DQ[17]/DDR0_DQ[33] DDR0_CS#[3] DDR_B_D18 BG8 DDR1_DQ[17]/DDR0_DQ[49] DDR1_CS#[3]
DDR_A_D19 BF5 DDR0_DQ[18]/DDR0_DQ[34] AD3 DDR_B_D19 BF8 DDR1_DQ[18]/DDR0_DQ[50] AF7
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_ODT[0] M_ODT0 <14> DDR_B_D20 DDR1_DQ[19]/DDR0_DQ[51] DDR1_ODT[0] M_ODT2 <15>
BG2 AE4 BF11 AE8
DDR_A_D21 DDR0_DQ[20]/DDR0_DQ[36] DDR0_ODT[1] M_ODT1 <14> DDR_B_D21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_ODT[1] M_ODT3 <15>
BG1 AE1 BF10 AE9
DDR_A_D22 BF1 DDR0_DQ[21]/DDR0_DQ[37] DDR0_ODT[2] AD4 DDR_B_D22 BG7 DDR1_DQ[21]/DDR0_DQ[53] DDR1_ODT[2] AE11
DDR_A_D23 BF2 DDR0_DQ[22]/DDR0_DQ[38] DDR0_ODT[3] DDR_B_D23 BF7 DDR1_DQ[22]/DDR0_DQ[54] DDR1_ODT[3]
C C
DDR_A_D24 BD2 DDR0_DQ[23]/DDR0_DQ[39] AH5 DDR_B_D24 BB11 DDR1_DQ[23]/DDR0_DQ[55] AH10
DDR_A_D25 DDR0_DQ[24]/DDR0_DQ[40] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_BS0 <14> DDR_B_D25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_RAS# <15>
BD1 AH1 BC11 AH11
DDR_A_D26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_BS1 <14> DDR_B_D26 DDR1_DQ[25]/DDR0_DQ[57] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_WE# <15>
BC4 AU1 BB8 AF8
DDR_A_D27 BC5 DDR0_DQ[26]/DDR0_DQ[42] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_BG0 <14> DDR_B_D27 BC8 DDR1_DQ[26]/DDR0_DQ[58] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_CAS# <15>
DDR_A_D28 BD5 DDR0_DQ[27]/DDR0_DQ[43] AH4 DDR_B_D28 BC10 DDR1_DQ[27]/DDR0_DQ[59] AH8
DDR_A_D29 BD4 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AG4 DDR_A_RAS# <14> DDR_B_D29 BB10 DDR1_DQ[28]/DDR0_DQ[60] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AH9 DDR_B_BS0 <15>
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_WE# <14> DDR_B_D30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_BS1 <15>
BC1 AD1 BC7 AR9
DDR_A_D31 DDR0_DQ[30]/DDR0_DQ[46] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_CAS# <14> DDR_B_D31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_BG0 <15>
BC2 BB7
DDR_A_D32 AB1 DDR0_DQ[31]/DDR0_DQ[47] AH3 DDR_A_MA0 DDR_B_D32 AA11 DDR1_DQ[31]/DDR0_DQ[63] AJ9 DDR_B_MA0
DDR_A_D33 AB2 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AP4 DDR_A_MA1 DDR_B_D33 AA10 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] AK6 DDR_B_MA1
DDR_A_D34 AA4 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AN4 DDR_A_MA2 DDR_B_D34 AC11 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] AK5 DDR_B_MA2
DDR_A_D35 AA5 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AP5 DDR_A_MA3 DDR_B_D35 AC10 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] AL5 DDR_B_MA3
DDR_A_D36 AB5 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] AP2 DDR_A_MA4 DDR_B_D36 AA7 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[3] AL6 DDR_B_MA4
DDR_A_D37 AB4 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AP1 DDR_A_MA5 DDR_B_D37 AA8 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[4] AM6 DDR_B_MA5
DDR_A_D38 AA2 DDR0_DQ[37]/DDR1_DQ[5] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] AP3 DDR_A_MA6 DDR_B_D38 AC8 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AN7 DDR_B_MA6
DDR_A_D39 AA1 DDR0_DQ[38]/DDR1_DQ[6] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AN1 DDR_A_MA7 DDR_B_D39 AC7 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] AN10 DDR_B_MA7
DDR_A_D40 V5 DDR0_DQ[39]/DDR1_DQ[7] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AN3 DDR_A_MA8 DDR_B_D40 W8 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AN8 DDR_B_MA8
DDR_A_D41 V2 DDR0_DQ[40]/DDR1_DQ[8] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AT4 DDR_A_MA9 DDR_B_D41 W7 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AR11 DDR_B_MA9
DDR_A_D42 U1 DDR0_DQ[41]/DDR1_DQ[9] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] AH2 DDR_A_MA10 DDR_B_D42 V10 DDR1_DQ[41]/DDR1_DQ[25] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AH7 DDR_B_MA10
DDR_A_D43 U2 DDR0_DQ[42]/DDR1_DQ[10] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] AN2 DDR_A_MA11 DDR_B_D43 V11 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AN11 DDR_B_MA11
DDR_A_D44 V1 DDR0_DQ[43]/DDR1_DQ[11] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] AU4 DDR_A_MA12 DDR_B_D44 W11 DDR1_DQ[43]/DDR1_DQ[27] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AR10 DDR_B_MA12
DDR_A_D45 V4 DDR0_DQ[44]/DDR1_DQ[12] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] AE3 DDR_A_MA13 DDR_B_D45 W10 DDR1_DQ[44]/DDR1_DQ[28] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AF9 DDR_B_MA13
DDR_A_D46 U5 DDR0_DQ[45]/DDR1_DQ[13] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU2 DDR_B_D46 V7 DDR1_DQ[45]/DDR1_DQ[29] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AR7
DDR_A_D47 U4 DDR0_DQ[46]/DDR1_DQ[14] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AU3 DDR_A_BG1 <14> DDR_B_D47 V8 DDR1_DQ[46]/DDR1_DQ[30] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] AT9 DDR_B_BG1 <15>
DDR_A_D48 DDR0_DQ[47]/DDR1_DQ[15] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_A_ACT# <14> DDR_B_D48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_ACT# <15>
R2 R11
DDR_A_D49 P5 DDR0_DQ[48]/DDR1_DQ[32] AG3 DDR_B_D49 P11 DDR1_DQ[48] AJ7
DDR_A_D50 DDR0_DQ[49]/DDR1_DQ[33] DDR0_PAR DDR_A_PAR <14> DDR_B_D50 DDR1_DQ[49] DDR1_PAR DDR_B_PAR <15>
R4 AU5 P7 AR8
DDR_A_D51 DDR0_DQ[50]/DDR1_DQ[34] DDR0_ALERT# DDR_A_ALERT# <14> DDR_B_D51 DDR1_DQ[50] DDR1_ALERT# DDR_B_ALERT# <15>
P4 R8
DDR_A_D52 R5 DDR0_DQ[51]/DDR1_DQ[35] DDR_B_D52 R10 DDR1_DQ[51]
DDR_A_D53 P2 DDR0_DQ[52]/DDR1_DQ[36] BR5 DDR_A_DQS#0 DDR_B_D53 P10 DDR1_DQ[52] BP9 DDR_B_DQS#0
DDR_A_D54 R1 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[0] BL3 DDR_A_DQS#1 DDR_B_D54 R7 DDR1_DQ[53] DDR1_DQSN[0]/DDR0_DQSN[2] BL9 DDR_B_DQS#1
DDR_A_D55 P1 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSN[1] BG3 DDR_A_DQS#2 DDR_B_D55 P8 DDR1_DQ[54] DDR1_DQSN[1]/DDR0_DQSN[3] BG9 DDR_B_DQS#2
DDR_A_D56 M4 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[2]/DDR0_DQSN[4] BD3 DDR_A_DQS#3 DDR_B_D56 L11 DDR1_DQ[55] DDR1_DQSN[2]/DDR0_DQSN[6] BC9 DDR_B_DQS#3
DDR_A_D57 M1 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSN[3]/DDR0_DQSN[5] AB3 DDR_A_DQS4 DDR_B_D57 M11 DDR1_DQ[56] DDR1_DQSN[3]/DDR0_DQSN[7] AC9 DDR_B_DQS#4
DDR_A_D58 L4 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSP[4]/DDR1_DQSP[0] V3 DDR_A_DQS5 DDR_B_D58 L7 DDR1_DQ[57] DDR1_DQSN[4]/DDR1_DQSN[2] W9 DDR_B_DQS#5
DDR_A_D59 L2 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] R3 DDR_A_DQS6 DDR_B_D59 M8 DDR1_DQ[58] DDR1_DQSN[5]/DDR1_DQSN[3] R9 DDR_B_DQS#6
DDR_A_D60 M5 DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQSP[6]/DDR1_DQSP[4] M3 DDR_A_DQS7 DDR_B_D60 L10 DDR1_DQ[59] DDR1_DQSN[6] M9 DDR_B_DQS#7
B DDR_A_D61 M2 DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D61 M10 DDR1_DQ[60] DDR1_DQSN[7] B
DDR_A_D62 L5 DDR0_DQ[61]/DDR1_DQ[45] BP5 DDR_A_DQS0 DDR_B_D62 M7 DDR1_DQ[61] BR9 DDR_B_DQS0
DDR_A_D63 L1 DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQSP[0] BK3 DDR_A_DQS1 DDR_B_D63 L8 DDR1_DQ[62] DDR1_DQSP[0]/DDR0_DQSP[2] BJ9 DDR_B_DQS1
DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSP[1] BF3 DDR_A_DQS2 DDR1_DQ[63] DDR1_DQSP[1]/DDR0_DQSP[3] BF9 DDR_B_DQS2
BA2 DDR0_DQSP[2]/DDR0_DQSP[4] BC3 DDR_A_DQS3 AW11 DDR1_DQSP[2]/DDR0_DQSP[6] BB9 DDR_B_DQS3
BA1 DDR0_ECC[0] DDR0_DQSP[3]/DDR0_DQSP[5] AA3 DDR_A_DQS#4 AY11 DDR1_ECC[0] DDR1_DQSP[3]/DDR0_DQSP[7] AA9 DDR_B_DQS4
AY4 DDR0_ECC[1] DDR0_DQSN[4]/DDR1_DQSN[0] U3 DDR_A_DQS#5 AY8 DDR1_ECC[1] DDR1_DQSP[4]/DDR1_DQSP[2] V9 DDR_B_DQS5
AY5 DDR0_ECC[2] DDR0_DQSN[5]/DDR1_DQSN[1] P3 DDR_A_DQS#6 AW8 DDR1_ECC[2] DDR1_DQSP[5]/DDR1_DQSP[3] P9 DDR_B_DQS6
BA5 DDR0_ECC[3] DDR0_DQSN[6]/DDR1_DQSN[4] L3 DDR_A_DQS#7 AY10 DDR1_ECC[3] DDR1_DQSP[6] L9 DDR_B_DQS7
BA4 DDR0_ECC[4] DDR0_DQSN[7]/DDR1_DQSN[5] AW10 DDR1_ECC[4] DDR1_DQSP[7]
AY1 DDR0_ECC[5] AY3 AY7 DDR1_ECC[5] AW9
AY2 DDR0_ECC[6] DDR0_DQSP[8] BA3 AW7 DDR1_ECC[6] DDR1_DQSP[8] AY9
DDR0_ECC[7] DDR0_DQSN[8] DDR1_ECC[7] DDR1_DQSN[8]

DDR CHANNEL B

DDR CHANNEL A RH148 1 2 121_0402_1% DDR_RCOMP0 G1 BN13 +V_DDR_REFA_R


RH149 1 2 75_0402_1% DDR_RCOMP1 H1 DDR_RCOMP[0] DDR_VREF_CA BP13
RH150 1 2 100_0402_1% DDR_RCOMP2 J2 DDR_RCOMP[1] DDR0_VREF_DQ BR13
DDR_RCOMP[2] DDR1_VREF_DQ +V_DDR_REFB_R
1 OF 14 2 OF 14
SKL-H_BGA1440 SKL-H_BGA1440
@ @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(2/7) DDR4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 8 of 80
5 4 3 2 1
5 4 3 2 1

+VCCST

RH163 1 2 1K_0402_5% H_THERMTRIP# CPU1E SKYLAKE_HALO

XDP_PREQ# BGA1440
RH156 1 @ 2 51_0402_5% B31 BN25
<17> PCH_CPU_BCLK_P BCLKP CFG[0] CFG0 <6>
A32 BN27
1 2 H_VCCST_PWRGD <17> PCH_CPU_BCLK_N BCLKN CFG[1] BN26 CFG1 <6>
RH164 1K_0402_5% CFG2
CFG[2] CFG2 <6>
D35 BN28
D VR_SVID_DATA <17> PCH_CPU_PCIBCLK_P PCI_BCLKP CFG[3] CFG3 <6> D
RH151 1 2 100_0402_1% C36 BR20 CFG4
<17> PCH_CPU_PCIBCLK_N PCI_BCLKN CFG[4] BM20 CFG4 <6>
CFG5
VR_SVID_ALERT# CFG[5] CFG5 <6>
RH152 1 2 56.2_0402_1% E31 BT20 CFG6
<17> CPU_24MHZ_P D31 CLK24P CFG[6] BP20 CFG6 <6>
CFG7
<17> CPU_24MHZ_N CLK24N CFG[7] CFG7 <6>
BR23
+VCCSTG CFG[8] CFG8 <6>
BR22
CFG[9] BT23 CFG9 <6>
CFG[10] CFG10 <6>
BT22
CFG[11] BM19 CFG11 <6>
CFG[12] CFG12 <6>
BR19
H_PROCHOT# CFG[13] CFG13 <6>
RH165 1 2 1K_0402_5% BP19
VR_SVID_ALERT# 1 2 220_0402_5% BH31 CFG[14] BT19 CFG14 <6>
RH153
<73> VR_SVID_ALERT# VIDALERT# CFG[15] CFG15 <6>
BH32
<73> VR_SVID_CLK VR_SVID_DATA BH29 VIDSCK BN23
<73> VR_SVID_DATA H_PROCHOT# VIDSOUT CFG[17] CFG17 <6>
RH158 1 2 499_0402_1% BR30 BP23
<43,61,62> H_PROCHOT# PROCHOT# CFG[16] CFG16 <6>
BP22
DDR_VTT_PG_CTRL BT13 CFG[19] BN22 CFG19 <6>
DDR_VTT_CNTL CFG[18] CFG18 <6>
BR27 XDP_BPM#0 T112 PAD~D @
BPM#[0] BT27 XDP_BPM#1 T113 PAD~D @
BPM#[1] BM31
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS H_VCCST_PWRGD BPM#[2]
RH154 1 2 60.4_0402_1% H13 BT30
<43,45> H_VCCST_PWRGD VCCST_PWRGD BPM#[3]
H_CPUPWRGD BT31
1: Normal Operation; Lane # definition matches <18> H_CPUPWRGD PLTRST_CPU# PROCPWRGD XDP_TDO
CFG2 BP35 BT28
socket pin map definition <16> PLTRST_CPU#
BM34 RESET# PROC_TDO BL32 XDP_TDI XDP_TDO <6,18>
<16> H_PM_SYNC_R 1 2 20_0402_5% BP31 PM_SYNC PROC_TDI BP28 XDP_TMS XDP_TDI <6,18>
RH155
<16> H_PM_DOWN PM_DOWN PROC_TMS PCH_JTAG_TCK XDP_TMS <6,18>
0:Lane Reversed BT34 BR28
* <16,43> H_PECI
<16> H_THERMTRIP#
H_THERMTRIP# J31 PECI
THERMTRIP#
PROC_TCK

PROC_TRST#
BP30 CPU_XDP_TRST#
XDP_PREQ#
PCH_JTAG_TCK

CPU_XDP_TRST#
<6,18>

<6,22>
RH519 1 @ 2 0_0402_5%~D BR33 BL30
1 2 <16> PROC_DETECT# BN1 SKTOCC# PROC_PREQ# BP27 XDP_PRDY# XDP_PREQ# <6,22>
CFG2
PROC_SELECT# PROC_PRDY# XDP_PRDY# <6,22>
RH184 1K_0402_5%
BM30
CATERR# BT25 CFG_RCOMP
CFG_RCOMP

1
C C
5 OF 14 RH59
SKL-H_BGA1440 49.9_0402_1%
@
Display Port Presence Strap

2
1 : Disabled; No Physical Display Port
CFG4 attached to Embedded Display Port +1.2V_DDR
UC1
0 : Enabled; An external Display Port device is 5 1
* connected to the Embedded Display Port
1
VCC NC

A
2 DDR_VTT_PG_CTRL
4
CH197 Y 3
0.1U_0402_10V7K GND
CFG4 1 2 2 74AUP1G07GW_TSSOP5 H_VCCST_PWRGD H_CPUPWRGD PLTRST_CPU#
RH185 1K_0402_5%

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
1 1 1

CH193
ESD@

CH194
ESD@

CH195
ESD@
+3VS
2 2 2
1

PCIE Port Bifurcation Straps RH525


330K_0402_5%
2

11: (Default) x16 - Device 1 functions 1 and 2 disabled


<64> SM_PG_CTRL
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
B B
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
* PCH_SYS_PWROK_XDP
RH489 1 2 1K_0402_5%
<17> PCH_SPI_SI_R +3VALW +3VS
CFG5 1 2
RH186 1K_0402_5%

CFG6 1 2

1
RH187 1K_0402_5%

1
RH2 RH5
10K_0402_5% 1K_0402_5%
+3V_PCH

2
2
RH493 1 2 2.2K_0402_5% PCH_SYS_PWROK_XDP
PBTN_OUT# <18,43> SYS_RESET# <18>

0.1U_0402_10V
1
CH174

CH175
0.1U_0402_10V
+VCCSTG

2
RH494 1 CMC@ 2 51_0402_5% XDP_TMS

RH495 1 CMC@ 2 51_0402_5% XDP_TDI

RH496 1 @ 2 51_0402_5% XDP_TDO

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(3/7) CFG,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 9 of 80
5 4 3 2 1
5 4 3 2 1

D D

+VCC_CORE +VCC_CORE

CPU1J SKYLAKE_HALO

BGA1440
BJ17
CPU1G SKYLAKE_HALO BJ19 VCCOPC
BJ20 VCCOPC
BGA1440 BK17 VCCOPC
AA13 V32 BK19 VCCOPC
AA31 VCC VCC V33 BK20 VCCOPC
AA32 VCC VCC V34 BL16 VCCOPC
AA33 VCC VCC V35 BL17 VCCOPC
AA34 VCC VCC V36 BL18 VCCOPC
AA35 VCC VCC V37 BL19 VCCOPC
AA36 VCC VCC V38 BL20 VCCOPC
AA37 VCC VCC W13 CPU1K SKYLAKE_HALO BL21 VCCOPC
AA38 VCC VCC W14 BM17 VCCOPC
AB29 VCC VCC W29 BGA1440
BN17 VCCOPC
AB30 VCC VCC W30 D1 BM33 T66 PAD~D @ VCCOPC
AB31 VCC VCC W31 E1 RSVD_TP RSVD_TP BL33 T67 PAD~D @ BJ23
AB32 VCC VCC W32 @ PAD~D T41 E3 RSVD_TP RSVD_TP BJ26 RSVD
AB35 VCC VCC W35 E2 RSVD_TP BJ14 T68 PAD~D @ BJ27 RSVD
AB36 VCC VCC W36 RSVD_TP RSVD_TP BJ13 T69 PAD~D @ BK23 RSVD
AB37 VCC VCC W37 @ PAD~D T43 BR1 RSVD_TP BK26 RSVD
AB38 VCC VCC W38 @ PAD~D T44 BT2 RSVD_TP BK28 BK27 RSVD
AC13 VCC VCC Y29 RSVD_TP RSVD BJ28 BL23 RSVD
AC14 VCC VCC Y30 BN35 RSVD BL24 RSVD
AC29 VCC VCC Y31 RSVD BJ18 BL25 RSVD
AC30 VCC VCC Y32 J24 VSS BL26 RSVD
C
AC31 VCC VCC Y33 H24 RSVD BJ16 T73 PAD~D @ BL27 RSVD C
AC32 VCC VCC Y34 BN33 RSVD RSVD_TP BK16 T74 PAD~D @ BL28 RSVD
AC33 VCC VCC Y35 BL34 RSVD RSVD_TP BM24 RSVD
AC34 VCC VCC Y36 RSVD RSVD
AC35 VCC VCC L14 N29 BK24 T75 PAD~D @
AC36 VCC VCC P29 R14 RSVD RSVD_TP BJ24 T76 PAD~D @ BL15
AD13 VCC VCC P30 AE29 RSVD RSVD_TP BM16 VCCOPC_SENSE
AD14 VCC VCC P31 AA14 RSVD BK21 VSSOPC_SENSE
AD31 VCC VCC P32 RSVD RSVD BJ21 BL22
AD32 VCC VCC P33 A36 RSVD BM22 RSVD
AD33 VCC VCC P34 A37 RSVD BT17 RSVD
AD34 VCC VCC P35 RSVD RSVD BR17
AD35 VCC VCC P36 RH167 1 2 30_0402_5% H23 RSVD BP15
VCC VCC <22> PCH_TRIGGER PROC_TRIGIN VCCEOPIO
AD36 R13 RH192 1 2 30_0402_5% J23 BK18 BR15
VCC VCC <22> CPU_TRIGGER PROC_TRIGOUT VSS VCCEOPIO
AD37 R31 BT15
AD38 VCC VCC R32 F30 BJ34 T81 PAD~D @ VCCEOPIO
AE13 VCC VCC R33 E30 RSVD RSVD_TP BJ33 T82 PAD~D @ BP16
AE14 VCC VCC R34 RSVD RSVD_TP BR16 RSVD
AE30 VCC VCC R35 B30 BT16 RSVD
AE31 VCC VCC R36 C30 RSVD RSVD
AE32 VCC VCC R37 RSVD G13
AE35 VCC VCC R38 G3 RSVD AJ8 BN15
AE36 VCC VCC T29 J3 RSVD RSVD BL31 BM15 VCCEOPIO_SENSE
AE37 VCC VCC T30 RSVD RSVD VSSEOPIO_SENSE
AE38 VCC VCC T31 B2 T85 PAD~D @ BP17
AF35 VCC VCC T32 NCTF B38 BN16 RSVD
AF36 VCC VCC T35 NCTF BP1 RSVD
AF37 VCC VCC T36 BR35 NCTF BR2 T88 PAD~D @
AF38 VCC VCC T37 BR31 RSVD NCTF C1 T89 PAD~D @ BM14
K13 VCC VCC T38 BH30 RSVD NCTF C38 BL14 VCC_OPC_1P8
K14 VCC VCC U29 RSVD NCTF VCC_OPC_1P8
L13 VCC VCC U30 11 OF 14 BJ35
N13 VCC VCC U31 SKL-H_BGA1440 BJ36 RSVD
N14 VCC VCC U32 @ RSVD
N30 VCC VCC U33
B B
N31 VCC VCC U34 +VCC_CORE AT13
N32 VCC VCC U35 AW13 ZVM#
N35 VCC VCC U36 MSM#
N36 VCC VCC V13 AU13
VCC VCC ZVM2#
1

N37 V14 AY13


N38 VCC VCC V31 RH197 MSM2#
P13 VCC VCC P14 RH166 1 @ 2 49.9_0402_1% BT29
100_0402_1%
VCC VCC RH57 1 @ 2 49.9_0402_1% BR25 OPC_RCOMP
RH58 1 @ 2 49.9_0402_1% BP25 OPCE_RCOMP
2

OPCE_RCOMP2
AG37
VCC_SENSE VCCSENSE <73>
AG38 10 OF 14
VSS_SENSE VSSSENSE <73>
SKL-H_BGA1440
@
1

7 OF 14 RH466
SKL-H_BGA1440 100_0402_1%
@
2

A A

Security Classification
2015/09/18
Compal Secret Data
2016/09/18 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(4/7) +VCC_CORE,RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 10 of 80
5 4 3 2 1
5 4 3 2 1

+VCCIO +VCCSTG +VCCST

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
D D

1 1 1 1 1 1 1 1 1

CH102

CH103

CH104

CH105

CH106

CH107

CH108

CH109

CH110
+VCCSA +1.2V_DDR
2 2 2 2 2 2 2 2 2

SKYLAKE_HALO
CPU1I
BGA1440
J30 AA6
K29 VCCSA VDDQ AE12
K30 VCCSA VDDQ AF5
K31 VCCSA VDDQ AF6 +1.2V_DDR
K32 VCCSA VDDQ AG5
K33 VCCSA VDDQ AG9
K34 VCCSA VDDQ AJ12
K35 VCCSA VDDQ AL11
L31 VCCSA VDDQ AP6
VCCSA VDDQ

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
L32 AP7 1 1 1 1
L35 VCCSA VDDQ AR12
VCCSA VDDQ

CH129

CH130

CH131

CH132
L36 AR6
L37 VCCSA VDDQ AT12
L38 VCCSA VDDQ AW6 2 2 2 2
M29 VCCSA VDDQ AY6
M30 VCCSA VDDQ J5
M31 VCCSA VDDQ J6
M32 VCCSA VDDQ K12
M33 VCCSA VDDQ K6
M34 VCCSA VDDQ L12
M35 VCCSA VDDQ L6 +1.2V_DDR
C +VCCIO M36 VCCSA VDDQ R6 C
VCCSA VDDQ T6 +1.2V_VCCPLL_OC
VDDQ W6
AG12 VDDQ
G15 VCCIO Y12
G17 VCCIO VDDQC
G19 VCCIO BH13 +1.2V_DDR
G21 VCCIO VCCPLL_OC G11
H15 VCCIO VCCPLL_OC +VCCST
H16 VCCIO
H17 VCCIO H30 +VCCSA
VCCIO VCCST +VCCSTG

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
H19
H20 VCCIO H29
VCCIO VCCSTG

2
H21 1 1 1 1 1 1 1 1 1 1 1
VCCIO

CH118

CH121

CH124

CH120

CH119

CH122

CH123

CH125

CH126

CH127

CH128
H26 G30 RH201
H27 VCCIO VCCSTG +VCCST
VCCIO 100_0402_1%
J15 H28
J16 VCCIO VCCPLL J28 2 2 2 2 2 2 2 2 2 2 2

1
J17 VCCIO VCCPLL
J19 VCCIO
J20 VCCIO M38
VCCIO VCCSA_SENSE VCCSA_SENSE <73>
J21 M37
VCCIO VSSSA_SENSE VSSSA_SENSE <73>
J26
VCCIO
1

J27 H14
VCCIO VCCIO_SENSE VCCIO_SENSE <76>
J14 RH469
VSSIO_SENSE VSSIO_SENSE <76>
100_0402_1%
2

B 9 OF 14 B
SKL-H_BGA1440
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(5/7) +VCCSA,+VCCIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 11 of 80
5 4 3 2 1
5 4 3 2 1

+VCCGT +VCCGT
+VCCGT
SKYLAKE_HALO
D SKYLAKE_HALO CPU1N D
CPU1H
BGA1440
BG34 BGA1440 AJ29
VCCGT AV29 VCCGT
BG35 VCCGT AJ30
VCCGT AV30 VCCGT AF29
BG36 VCCGT AJ31 VCCGTX
VCCGT AV31 VCCGT AF30
BH33 VCCGT AJ32 VCCGTX
VCCGT AV32 VCCGT AF31
BH34 VCCGT AJ33 VCCGTX
VCCGT AV33 VCCGT AF32
BH35 VCCGT AJ34 VCCGTX
VCCGT AV34 VCCGT AF33
BH36 VCCGT AJ35 VCCGTX
VCCGT AV35 VCCGT AF34
BH37 VCCGT AJ36 VCCGTX
VCCGT AV36 VCCGT AG13
BH38 VCCGT AK31 VCCGTX
VCCGT AW14 VCCGT AG14
BJ37 VCCGT AK32 VCCGTX
VCCGT AW31 VCCGT AG31
BJ38 VCCGT AK33 VCCGTX
VCCGT AW32 VCCGT AG32
BL36 VCCGT AK34 VCCGTX
VCCGT AW33 VCCGT AG33
BL37 VCCGT AK35 VCCGTX
VCCGT AW34 VCCGT AG34
BM36 VCCGT AK36 VCCGTX
VCCGT AW35 VCCGT AG35
BM37 VCCGT AK37 VCCGTX
VCCGT AW36 VCCGT AG36
BN36 VCCGT AK38 VCCGTX
VCCGT AW37 VCCGT AH13
BN37 VCCGT AL13 VCCGTX
VCCGT AW38 VCCGT AH14
BN38 VCCGT AL29 VCCGTX
VCCGT AY29 VCCGT AH29
BP37 VCCGT AL30 VCCGTX
VCCGT AY30 VCCGT AH30
BP38 VCCGT AL31 VCCGTX
VCCGT AY31 VCCGT AH31
BR37 VCCGT AL32 VCCGTX
VCCGT AY32 VCCGT AH32
BT37 VCCGT AL35 VCCGTX
VCCGT AY35 VCCGT AJ13
BE38 VCCGT AL36 VCCGTX
VCCGT AY36 VCCGT AJ14
BF13 VCCGT AL37 VCCGTX
VCCGT AY37 VCCGT
BF14 VCCGT AL38
VCCGT AY38 VCCGT
BF29 VCCGT AM13
VCCGT BA13 VCCGT
BF30 VCCGT AM14
VCCGT BA14 VCCGT
BF31 VCCGT AM29
VCCGT BA29 VCCGT
BF32 VCCGT AM30
VCCGT BA30 VCCGT
BF35 VCCGT AM31
C VCCGT BA31 VCCGT C
BF36 VCCGT AM32
VCCGT BA32 VCCGT
BF37 VCCGT AM33
VCCGT BA33 VCCGT
BF38 VCCGT AM34
VCCGT BA34 VCCGT
BG29 VCCGT AM35
VCCGT BA35 VCCGT
BG30 VCCGT AM36
VCCGT BA36 VCCGT
BG31 VCCGT AN13
VCCGT BB13 VCCGT
BG32 VCCGT AN14
VCCGT BB14 VCCGT
BG33 VCCGT AN31
VCCGT BB31 VCCGT
BC36 VCCGT AN32
VCCGT BB32 VCCGT
BC37 VCCGT AN33
VCCGT BB33 VCCGT
BC38 VCCGT AN34
VCCGT BB34 VCCGT
BD13 VCCGT AN35
VCCGT BB35 VCCGT
BD14 VCCGT AN36
VCCGT BB36 VCCGT
BD29 VCCGT AN37
VCCGT BB37 VCCGT
BD30 VCCGT AN38
VCCGT BB38 VCCGT
BD31 VCCGT AP13
VCCGT BC29 VCCGT +VCCGT
BD32 VCCGT AP14
VCCGT BC30 VCCGT
BD33 VCCGT AP29
VCCGT BC31 VCCGT
BD34 VCCGT AP30
VCCGT BC32 VCCGT
BD35 VCCGT AP31
VCCGT BC35 VCCGT
BD36 VCCGT AP32
VCCGT BE33 VCCGT
BE31 VCCGT AP35
VCCGT BE34 VCCGT
BE32 VCCGT AP36
VCCGT BE35 VCCGT
BE37 VCCGT AP37

1
VCCGT BE36 VCCGT
VCCGT AP38
VCCGT RH203
AR29
8 OF 14 AR30 VCCGT 100_0402_1%
SKL-H_BGA1440 AR31 VCCGT
@ AR32 VCCGT

2
AR33 VCCGT AH38
VCCGT VCCGT_SENSE VCCGT_SENSE <73>
AR34 AH35
AR35 VCCGT VSSGTX_SENSE AH37
B VCCGT VSSGT_SENSE VSSGT_SENSE <73> B
AR36 AH36
AT14 VCCGT VCCGTX_SENSE
AT31 VCCGT
AT32 VCCGT
AT33 VCCGT

1
AT34 VCCGT
VCCGT RH472
AT35
AT36 VCCGT 100_0402_1%
AT37 VCCGT
AT38 VCCGT

2
AU14 VCCGT
AU29 VCCGT
AU30 VCCGT
AU31 VCCGT
AU32 VCCGT
AU35 VCCGT
AU36 VCCGT
AU37 VCCGT
AU38 VCCGT
VCCGT
14 OF 14
SKL-H_BGA1440
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(6/7) +VCCGT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 12 of 80
5 4 3 2 1
5 4 3 2 1

SKYLAKE_HALO SKYLAKE_HALO
CPU1F CPU1L
BGA1440 CPU1M SKYLAKE_HALO
BGA1440
Y38 K1 BGA1440
VSS VSS C17 C25
Y37 J36 VSS VSS BB4 AK30
VSS VSS C13 C23 VSS VSS
Y14 J33 VSS VSS BB3 AK29
VSS VSS C9 C21 VSS VSS
Y13 J32 VSS VSS BB2 AK4
D VSS VSS BT32 C19 VSS VSS D
Y11 J25 VSS VSS BB1 AJ38
VSS VSS BT26 C15 VSS VSS
Y10 J22 VSS VSS BA38 AJ37
VSS VSS BT24 C11 VSS VSS
Y9 J18 VSS VSS BA37 AJ6
VSS VSS BT21 C8 VSS VSS
Y8 J10 VSS VSS BA12 AJ5
VSS VSS BT18 C5 VSS VSS
Y7 J7 VSS VSS BA11 AJ4
VSS VSS BT14 BM29 VSS VSS
W34 J4 VSS VSS BA10 AJ3
VSS VSS BT12 BM25 VSS VSS
W33 H35 VSS VSS BA9 AJ2
VSS VSS BT9 BM18 VSS VSS
W12 H32 VSS VSS BA8 AJ1
VSS VSS BT5 BM11 VSS VSS
W5 H25 VSS VSS BA7 AH34
VSS VSS BR36 BM8 VSS VSS
W4 H22 VSS VSS BA6 AH33
VSS VSS BR34 BM7 VSS VSS
W3 H18 VSS VSS B9 AH12
VSS VSS BR29 BM5 VSS VSS
W2 H12 VSS VSS AY34 AH6
VSS VSS BR26 BM3 VSS VSS
W1 H11 VSS VSS AY33 AG30
VSS VSS BR24 BL38 VSS VSS
V30 G28 VSS VSS AY14 AG29
VSS VSS BR21 BL35 VSS VSS
V29 G26 VSS VSS AY12 AG11
VSS VSS BR18 BL13 VSS VSS
V12 G24 VSS VSS AW30 AG10
VSS VSS BR14 BL6 VSS VSS
V6 G23 VSS VSS AW29 AG8
VSS VSS BR12 BK25 VSS VSS
U38 G22 VSS VSS AW12 AG7
VSS VSS BR7 BK22 VSS VSS
U37 G20 VSS VSS AW5 AG6
VSS VSS BP34 BK13 VSS VSS
U6 G18 VSS VSS AW4 AF14
VSS VSS BP33 BK6 VSS VSS
T34 G16 VSS VSS AW3 AF13
VSS VSS BP29 BJ30 VSS VSS
T33 G14 VSS VSS AW2 AF12
VSS VSS BP26 BJ29 VSS VSS
T14 G12 VSS VSS AW1 AF4
VSS VSS BP24 BJ15 VSS VSS
T13 G10 VSS VSS AV38 AF3
VSS VSS BP21 BJ12 VSS VSS
T12 G9 VSS VSS AV37 AF2
VSS VSS BP18 BH11 VSS VSS
T11 G8 VSS VSS AU34 AF1
VSS VSS BP14 BH10 VSS VSS
T10 G6 VSS VSS AU33 AE34
VSS VSS BP12 BH7 VSS VSS
T9 G5 VSS VSS AU12 AE33
VSS VSS BP7 BH6 VSS VSS
T8 G4 VSS VSS AU11 AE6
VSS VSS BN34 BH3 VSS VSS
T7 F36 VSS VSS AU10 AD30
VSS VSS BN31 BH2 VSS VSS
T5 F31 VSS VSS AU9 AD29
VSS VSS BN30 BG37 VSS VSS
T4 F29 VSS VSS AU8 AD12
C VSS VSS BN29 BG14 VSS VSS C
T3 F27 VSS VSS AU7 AD11
VSS VSS BN24 BG6 VSS VSS
T2 F25 VSS VSS AU6 AD10
VSS VSS BN21 BF34 VSS VSS
T1 F23 VSS VSS AT30 AD9
VSS VSS BN20 BF6 VSS VSS
R30 F21 VSS VSS AT29 AD8
VSS VSS BN19 BE30 VSS VSS
R29 F19 VSS VSS AT6 AD7
VSS VSS BN18 BE5 VSS VSS
R12 F17 VSS VSS AR38 AD6
VSS VSS BN14 BE4 VSS VSS
P38 F15 VSS VSS AR37 AC38
VSS VSS BN12 BE3 VSS VSS
P37 F13 VSS VSS AR14 AC37
VSS VSS BN9 BE2 VSS VSS
P12 F11 VSS VSS AR13 AC12
VSS VSS BN7 BE1 VSS VSS
P6 F9 VSS VSS AR5 AC6
VSS VSS BN4 BD38 VSS VSS
N34 F8 VSS VSS AR4 AC5
VSS VSS BN2 BD37 VSS VSS
N33 F5 VSS VSS AR3 AC4
VSS VSS BM38 BD12 VSS VSS
N12 F4 VSS VSS AR2 AC3
VSS VSS BM35 BD11 VSS VSS
N11 F3 VSS VSS AR1 AC2
VSS VSS BM28 BD10 VSS VSS
N10 F2 VSS VSS AP34 AC1
VSS VSS BM27 BD8 VSS VSS
N9 E38 VSS VSS AP33 AB34
VSS VSS BM26 BD7 VSS VSS
N8 E35 VSS VSS AP12 AB33
VSS VSS BM23 BD6 VSS VSS
N7 E34 VSS VSS AP11 AB6
VSS VSS BM21 BC33 VSS VSS
N6 E9 VSS VSS AP10 AA30
VSS VSS BM13 BC14 VSS VSS
N5 E4 VSS VSS AP9 AA29
VSS VSS BM12 BC13 VSS VSS
N4 D33 VSS VSS AP8 AA12
VSS VSS BM9 BC6 VSS VSS
N3 D30 VSS VSS AN30 A30
VSS VSS BM6 BB30 VSS VSS
N2 D28 VSS VSS AN29 A28
VSS VSS BM2 BB29 VSS VSS
N1 D26 VSS VSS AN12 A26
VSS VSS BL29 BB6 VSS VSS
M14 D24 VSS VSS AN6 A24
VSS VSS BK29 BB5 VSS VSS
M13 D22 VSS VSS AN5 A22
VSS VSS BK15 VSS VSS
M12 D20 VSS AM38 A20
VSS VSS BK14 VSS VSS
M6 D18 VSS AM37 A18
VSS VSS BJ32 VSS VSS
L34 D16 VSS AM12 A16
VSS VSS BJ31 VSS VSS
L33 D14 VSS AM5 A14
VSS VSS BJ25 VSS VSS
L30 D12 VSS AM4 A12
VSS VSS BJ22 VSS VSS
L29 D10 VSS AM3 A10
B VSS VSS BH14 VSS VSS B
K38 D9 VSS C2 AM2 A9
VSS VSS BH12 NCTFVSS VSS VSS
K11 D6 VSS BT36 AM1 A6
VSS VSS BH9 NCTFVSS VSS VSS
K10 D3 VSS BT35 AL34
VSS VSS BH8 NCTFVSS VSS
K9 C37 VSS BT4 AL33
VSS VSS BH5 NCTFVSS VSS
K8 C31 VSS BT3 AL14 B37
VSS VSS BH4 NCTFVSS VSS NCTFVSS
K7 C29 VSS BR38 AL12 B3
VSS VSS BH1 NCTFVSS VSS NCTFVSS
K5 C27 VSS AL10 A34
VSS VSS BG38 VSS NCTFVSS
K4 VSS AL9 A4
VSS BG13 VSS NCTFVSS
K3 D38 VSS AL8 A3
VSS NCTFVSS BG12 VSS NCTFVSS
K2 VSS AL7
VSS BF33 VSS
VSS AL4
BF12 VSS
6 OF 14 BE29 VSS
SKL-H_BGA1440 BE6 VSS
@ BD9 VSS 13 OF 14
BC34 VSS SKL-H_BGA1440
BC12 VSS @
BB12 VSS
VSS
12 OF 14
SKL-H_BGA1440
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 13 of 80
5 4 3 2 1
5 4 3 2 1

+1.2V_DDR JDIMM1
4H , RVS
+1.2V_DDR
1 2
DDR_A_D1 3 VSS1 VSS2 4 DDR_A_D0
<8> DDR_A_D[0..63] 5 DQ5 DQ4 6
<8> DDR_A_MA[0..13] DDR_A_D5 7 VSS3 VSS4 8 DDR_A_D4
<8> DDR_A_DQS#[0..7] 9 DQ1 DQ0 10
<8> DDR_A_DQS[0..7] DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
Layout Note: Layout Note: DQS0_t VSS7 DDR_A_D6
15 16
Place near JDIMM1.257,259 Place near JDIMM1.258 DDR_A_D3 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_A_D2
DDR_A_D7 21 VSS10 DQ2 22
23 DQ3 VSS11 24 DDR_A_D12
D DDR_A_D9 25 VSS12 DQ12 26 D
27 DQ13 VSS13 28 DDR_A_D13
+2.5V_MEM +0.6VS DDR_A_D8 29 VSS14 DQ8 30
31 DQ9 VSS15 32 DDR_A_DQS#1
Layout Note: VSS16 DQS1_c DDR_A_DQS1
33 34
Place near JDIMM1.255 35 DM1_n/DBI_n DQS1_t 36
DDR_A_D15 VSS17 VSS18 DDR_A_D14

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
37 38
DQ15 DQ14
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D
39 40
DDR_A_D10 VSS19 VSS20 DDR_A_D11
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
1 1 1 1 41 42
DQ10 DQ11

CD12

CD13

CD14

CD15
1 1 1 1 43 44
DDR_A_D16 VSS21 VSS22 DDR_A_D21
CD3

CD4
45 46
DQ21 DQ20
CD9

CD10

47 48
2 2 2 2 +3VS DDR_A_D17 49 VSS23 VSS24 50 DDR_A_D20
2 2 2 2 51 DQ17 DQ16 52
DDR_A_DQS#2 53 VSS25 VSS26 54
DDR_A_DQS2 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_A_D23
DDR_A_D19 VSS28 DQ22

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D
59 60
61 DQ23 VSS29 62 DDR_A_D22
1 1 DDR_A_D18 VSS30 DQ18

CD16

CD17
63 64
65 DQ19 VSS31 66 DDR_A_D28
DDR_A_D24 67 VSS32 DQ28 68
2 2 69 DQ29 VSS33 70 DDR_A_D25
DDR_A_D29 71 VSS34 DQ24 72
73 DQ25 VSS35 74 DDR_A_DQS#3
75 VSS36 DQS3_c 76 DDR_A_DQS3
77 DM3_n/DBI3_n DQS3_t 78
Layout Note: DDR_A_D26 VSS37 VSS38 DDR_A_D30
79 80
Place near JDIMM1 81 DQ30 DQ31 82
DDR_A_D27 83 VSS39 VSS40 84 DDR_A_D31 +1.2V_DDR
85 DQ26 DQ27 86
87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
+1.2V_DDR 91 VSS43 VSS44 92
CB1/NC CB0/NC

1
93 94
95 VSS45 VSS46 96 RD35
97 DQS8_c DM8_n/DBI_n/NC 98 470_0402_1%
DQS8_t VSS47
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

99 100
101 VSS48 CB6/NC 102
1 1 1 1 1 1 1 1

2
CB2/NC VSS49
CD1

CD2

CD75

CD74

CD77

CD76

CD79

CD78

103 104
C 105 VSS50 CB7/NC 106 C
107 CB3/NC VSS51 108
2 2 2 2 2 2 2 2 109 VSS52 RESET_n 110 H_DRAMRST# <15,18>
<8> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <8>

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
111 112
113 VDD1 VDD2 114
<8> DDR_A_BG1 BG1 ACT_n DDR_A_ACT# <8> 1 1

CD91
@ESD@

CD69
115 116
<8> DDR_A_BG0 117 BG0 ALERT_n 118 DDR_A_ALERT# <8>
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7 2 2
123 A9 A7 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
+1.2V_DDR DDR_A_MA6 127 A8 A5 128 DDR_A_MA4
129 A6 A4 130
DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2
DDR_A_MA1 133 A3 A2 134
135 A1 EVENT_n/NF 136
VDD9 VDD10
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

137 138
<8> M_CLK_DDR0 139 CK0_t CK1_t/NF 140 M_CLK_DDR1 <8>
1 <8> M_CLK_DDR#0 CK0_c CK1_c/NF M_CLK_DDR#1 <8>
1 1 1 1 1 1 1 1 141 142
+ CD11 143 VDD11 VDD12 144 DDR_A_MA0
<8> DDR_A_PAR PARITY A0 DDR_A_MA10
CD5

CD6

CD7

CD8

CD70

CD71

CD72

CD73

220U_D7_2VM_R6M 145 146


<8> DDR_A_BS1 147 BA1 A10/AP 148
2 2 2 2 2 2 2 2 2 149 VDD13 VDD14 150
<8> DDR_CS0_DIMMA# 151 CS0_n BA0 152 DDR_A_BS0 <8>
<8> DDR_A_WE# 153 WE_n/A14 RAS_n/A16 154 DDR_A_RAS# <8>
155 VDD15 VDD16 156
<8> M_ODT0 157 ODT0 CAS_n/A15 158 DDR_A_MA13 DDR_A_CAS# <8>
<8> DDR_CS1_DIMMA# 159 CS1_n A13 160
161 VDD17 VDD18 162
<8> M_ODT1 163 ODT1 C0/CS2_n/NC 164 +V_DDR_REFA
165 VDD19 VREFCA 166 DIMM_CHA_SA2
167 C1, CS3_n,NC SA2 168
DDR_A_D33 VSS53 VSS54 DDR_A_D36

0.1U_0402_16V7K~D
169 170
171 DQ37 DQ36 172
DDR_A_D37 VSS55 VSS56 DDR_A_D32 1

CD18
173 174
175 DQ33 DQ32 176
DDR_A_DQS#4 177 VSS57 VSS58 178
DDR_A_DQS4 179 DQS4_c DM4_n/DBI4_n 180 +1.2V_DDR 2
181 DQS4_t VSS59 182 DDR_A_D35
DDR_A_D38 183 VSS60 DQ39 184
B 185 DQ38 VSS61 186 DDR_A_D34 B
DDR_A_D39 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D40
DDR_A_D44 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_A_D45
DDR_A_D41 195 VSS66 DQ41 196
197 DQ40 VSS67 198 DDR_A_DQS#5
199 VSS68 DQS5_c 200 DDR_A_DQS5
+1.2V_DDR 201 DM5_n/DBI5_n DQS5_t 202
DDR_A_D43 203 VSS69 VSS70 204 DDR_A_D47
205 DQ46 DQ47 206
DIMM_CHA_SA0 DIMM_CHA_SA1 DIMM_CHA_SA2 DDR_A_D42 207 VSS71 VSS72 208 DDR_A_D46
209 DQ42 DQ43 210
DDR_A_D48 211 VSS73 VSS74 212 DDR_A_D50
DQ52 DQ53
1

213 214
@ @ @ DDR_A_D54 215 VSS75 VSS76 216 DDR_A_D52
RD28 RD29 RD30 217 DQ49 DQ48 218
0_0402_5% 0_0402_5% 0_0402_5% DDR_A_DQS#6 219 VSS77 VSS78 220
DDR_A_DQS6 221 DQS6_c DM6_n/DBI6_n 222 +1.2V_DDR
2

223 DQS6_t VSS79 224 DDR_A_D51


DDR_A_D53 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_A_D49
DDR_A_D55 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_A_D61
DDR_A_D56 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_A_D57
DDR_A_D60 237 VSS86 DQ57 238
239 DQ56 VSS87 240 DDR_A_DQS#7
+V_DDR_REFA_R +1.2V_DDR 241 VSS88 DQS7_c 242 DDR_A_DQS7
+1.2V_DDR 243 DM7_n/DBI7_n DQS7_t 244
DDR_A_D58 245 VSS89 VSS90 246 DDR_A_D59
DQ62 DQ63
1

247 248
DDR_A_D62 249 VSS91 VSS92 250 DDR_A_D63
W=20mils RH206 251 DQ58
VSS93
DQ59
VSS94
252
1K_0402_1%~D 253 254
<15,18,38> PCH_SMBCLK 255 SCL SDA 256 DIMM_CHA_SA0 PCH_SMBDATA <15,18,38>
+3VS
2

257 VDDSPD SA0 258


+V_DDR_REFA +2.5V_MEM VPP1 VTT DIMM_CHA_SA1 +0.6VS
RH484 1 2 2_0402_1% 259 260
261 VPP2 SA1 262
GND1 GND2
1
1

A A
CH101
0.022U_0402_25V7K RH209
2 1K_0402_1%~D
1

DEREN_40-42271-26001RHF
RH211 CONN@
24.9_0402_1%
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 DIMMA,RVS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 14 of 80
5 4 3 2 1
5 4 3 2 1

+1.2V_DDR JDIMM2
4H , STD
+1.2V_DDR
1 2
DDR_B_D0 3 VSS1 VSS2 4 DDR_B_D5
<8> DDR_B_D[0..63] 5 DQ5 DQ4 6
<8> DDR_B_MA[0..13] DDR_B_D4 7 VSS3 VSS4 8 DDR_B_D1
Layout Note: Layout Note: <8> DDR_B_DQS#[0..7] DQ1 DQ0
9 10
Place near JDIMM2.258 Place near JDIMM2.257,259 <8> DDR_B_DQS[0..7] DDR_B_DQS#0 11 VSS5 VSS6 12
DDR_B_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_B_D2
DDR_B_D6 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_B_D7
DDR_B_D3 21 VSS10 DQ2 22
23 DQ3 VSS11 24 DDR_B_D8
+0.6VS +2.5V_MEM DDR_B_D10 25 VSS12 DQ12 26
D 27 DQ13 VSS13 28 DDR_B_D9 D
DDR_B_D14 29 VSS14 DQ8 30
31 DQ9 VSS15 32 DDR_B_DQS#1
33 VSS16 DQS1_c 34 DDR_B_DQS1
DM1_n/DBI_n DQS1_t
1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
Layout Note: 35 36
DDR_B_D12 37 VSS17 VSS18 38 DDR_B_D15
1 1 1 1 1 1 1 1 Place near JDIMM2.255 DQ15 DQ14
CD32

CD30

CD31
39 40
DDR_B_D13 VSS19 VSS20 DDR_B_D11

CD90

CD89

CD88

CD27

CD28
41 42
43 DQ10 DQ11 44
2 2 2 2 2 2 2 2 DDR_B_D16 45 VSS21 VSS22 46 DDR_B_D22
47 DQ21 DQ20 48
DDR_B_D17 49 VSS23 VSS24 50 DDR_B_D18
51 DQ17 DQ16 52
+3VS DDR_B_DQS#2 53 VSS25 VSS26 54
DDR_B_DQS2 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_B_D21
DDR_B_D19 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_B_D20
DDR_B_D23 VSS30 DQ18

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D
63 64
65 DQ19 VSS31 66 DDR_B_D27
1 1 DDR_B_D25 VSS32 DQ28

CD34

CD35
67 68
69 DQ29 VSS33 70 DDR_B_D30
DDR_B_D28 71 VSS34 DQ24 72
2 2 73 DQ25 VSS35 74 DDR_B_DQS#3
75 VSS36 DQS3_c 76 DDR_B_DQS3
77 DM3_n/DBI3_n DQS3_t 78
Layout Note: DDR_B_D26 VSS37 VSS38 DDR_B_D29
79 80
Place near JDIMM2 81 DQ30 DQ31 82
DDR_B_D31 83 VSS39 VSS40 84 DDR_B_D24
85 DQ26 DQ27 86
87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
+1.2V_DDR 99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
103 CB2/NC VSS49 104
105 VSS50 CB7/NC 106
CB3/NC VSS51
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C 107 108 C
109 VSS52 RESET_n 110 H_DRAMRST# <14,18>
1 1 1 1 1 1 1 1 <8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8>
CD19

CD20

CD21

CD22

CD83

CD81

CD80

CD82

0.1U_0402_16V7K~D
111 112
113 VDD1 VDD2 114
<8> DDR_B_BG1 BG1 ACT_n DDR_B_ACT# <8> 1

CD92
@ESD@
115 116
2 2 2 2 2 2 2 2 <8> DDR_B_BG0 117 BG0 ALERT_n 118 DDR_B_ALERT# <8>
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7 2
123 A9 A7 124
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
129 A6 A4 130
DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
+1.2V_DDR DDR_B_MA1 133 A3 A2 134
135 A1 EVENT_n/NF 136
137 VDD9 VDD10 138
<8> M_CLK_DDR2 139 CK0_t CK1_t/NF 140 M_CLK_DDR3 <8>
<8> M_CLK_DDR#2 141 CK0_c CK1_c/NF 142 M_CLK_DDR#3 <8>
VDD11 VDD12 DDR_B_MA0
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

143 144
<8> DDR_B_PAR 145 PARITY A0 146 DDR_B_MA10
1 <8> DDR_B_BS1 BA1 A10/AP
1 1 1 1 1 1 1 1 147 148
+ CD33 149 VDD13 VDD14 150
<8> DDR_CS2_DIMMB# CS0_n BA0 DDR_B_BS0 <8>
CD23

CD24

CD25

CD26

CD87

CD85

CD84

CD86

220U_D7_2VM_R6M 151 152


<8> DDR_B_WE# 153 WE_n/A14 RAS_n/A16 154 DDR_B_RAS# <8>
2 2 2 2 2 2 2 2 2 155 VDD15 VDD16 156
<8> M_ODT2 157 ODT0 CAS_n/A15 158 DDR_B_MA13 DDR_B_CAS# <8>
<8> DDR_CS3_DIMMB# 159 CS1_n A13 160
161 VDD17 VDD18 162
<8> M_ODT3 163 ODT1 C0/CS2_n/NC 164 +V_DDR_REFB
165 VDD19 VREFCA 166 DIMM_CHB_SA2
167 C1, CS3_n,NC SA2 168
DDR_B_D38 VSS53 VSS54 DDR_B_D35

0.1U_0402_16V7K~D
169 170
171 DQ37 DQ36 172
DDR_B_D39 VSS55 VSS56 DDR_B_D34 1

CD29
173 174
175 DQ33 DQ32 176
DDR_B_DQS#4 177 VSS57 VSS58 178
DDR_B_DQS4 179 DQS4_c DM4_n/DBI4_n 180 +1.2V_DDR 2
181 DQS4_t VSS59 182 DDR_B_D36
DDR_B_D33 183 VSS60 DQ39 184
185 DQ38 VSS61 186 DDR_B_D37
B +3VS DDR_B_D32 187 VSS62 DQ35 188 B
189 DQ34 VSS63 190 DDR_B_D44
DDR_B_D40 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_B_D45
DDR_B_D41 195 VSS66 DQ41 196
DQ40 VSS67
1

197 198 DDR_B_DQS#5


@ 199 VSS68 DQS5_c 200 DDR_B_DQS5
RD5
+1.2V_DDR 201 DM5_n/DBI5_n DQS5_t 202
0_0402_5% DDR_B_D42 203 VSS69 VSS70 204 DDR_B_D47
205 DQ46 DQ47 206
2

DDR_B_D43 207 VSS71 VSS72 208 DDR_B_D46


DIMM_CHB_SA0 DIMM_CHB_SA1 DIMM_CHB_SA2 209 DQ42 DQ43 210
DDR_B_D52 211 VSS73 VSS74 212 DDR_B_D54
213 DQ52 DQ53 214
VSS75 VSS76
1

DDR_B_D51 215 216 DDR_B_D48


@ @ 217 DQ49 DQ48 218
RD38 RD40 DDR_B_DQS#6 219 VSS77 VSS78 220
0_0402_5% 0_0402_5% DDR_B_DQS6 221 DQS6_c DM6_n/DBI6_n 222 +1.2V_DDR
223 DQS6_t VSS79 224 DDR_B_D53
2

DDR_B_D50 225 VSS80 DQ54 226


227 DQ55 VSS81 228 DDR_B_D49
DDR_B_D55 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_B_D59
DDR_B_D61 233 VSS84 DQ60 234
+V_DDR_REFB_R 235 DQ61 VSS85 236 DDR_B_D57
+1.2V_DDR DDR_B_D62 237 VSS86 DQ57 238
239 DQ56 VSS87 240 DDR_B_DQS#7
241 VSS88 DQS7_c 242 DDR_B_DQS7
+1.2V_DDR DM7_n/DBI7_n DQS7_t
1

243 244
RH207 DDR_B_D56 245 VSS89 VSS90 246 DDR_B_D63
W=20mils 1K_0402_1%~D
DDR_B_D60
247 DQ62
VSS91
DQ63
VSS92
248
DDR_B_D58
249 250
251 DQ58 DQ59 252
2

253 VSS93 VSS94 254


1 2 2_0402_1% +V_DDR_REFB <14,18,38> PCH_SMBCLK 255 SCL SDA 256 DIMM_CHB_SA0 PCH_SMBDATA <14,18,38>
RH485 +3VS
257 VDDSPD SA0 258
+2.5V_MEM VPP1 VTT DIMM_CHB_SA1 +0.6VS
259 260
VPP2 SA1
1

1 261 262
RH210 GND1 GND2
CH100 1K_0402_1%~D
A 0.022U_0402_25V7K A
2
2
1

RH212
24.9_0402_1% DEREN_40-42261-26001RHF
CONN@
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 DIMMB,STD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 15 of 80
5 4 3 2 1
5 4 3 2 1

D D
SPT-H_PCH
UH1C

AV2 G31
CL_CLK PCIE9_RXN/SATA0A_RXN PCIE_PRX_DTX_N9 <29>
AV3 H31
CL_DATA CLINK PCIE9_RXP/SATA0A_RXP PCIE_PTX_DRX_N9_C PCIE_PRX_DTX_P9 <29>
AW2 C31 0.22U_0201_6.3V 2 1 CH210
CL_RST# PCIE9_TXN/SATA0A_TXN B31 PCIE_PTX_DRX_P9_C 2 1 CH211 PCIE_PTX_DRX_N9 <29>
0.22U_0201_6.3V
R44
R43
U39
GPP_G8/FAN_PWM_0
GPP_G9/FAN_PWM_1
PCIE9_TXP/SATA0A_TXP

G29
PCIE_PTX_DRX_P9 <29>
M.2 SSD
N42 GPP_G10/FAN_PWM_2
GPP_G11/FAN_PWM_3
FAN
PCIE10_RXN/SATA1A_RXN
PCIE10_RXP/SATA1A_RXP
PCIE10_TXN/SATA1A_TXN
E29
C32 PCIE_PTX_DRX_N10_C
PCIE_PTX_DRX_P10_C
0.22U_0201_6.3V 2 1 CH212
PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10
<29>
<29>
<29>
Slot#1
U43 B32 0.22U_0201_6.3V 2 1 CH213
U42 GPP_G0/FAN_TACH_0 PCIE10_TXP/SATA1A_TXP PCIE_PTX_DRX_P10 <29>
U41 GPP_G1/FAN_TACH_1 F41
GPP_G2/FAN_TACH_2 PCIE15_RXN/SATA2_RXN PCIE_PRX_DTX_N15 <29>
M44 E41
U36 GPP_G3/FAN_TACH_3 PCIE15_RXP/SATA2_RXP B39 PCIE_PTX_DRX_N15_C 2 1 CH214 PCIE_PRX_DTX_P15 <29>
0.22U_0201_6.3V
P44
T45
T44
GPP_G4/FAN_TACH_4
GPP_G5/FAN_TACH_5
GPP_G6/FAN_TACH_6
PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP
A39

D43
PCIE_PTX_DRX_P15_C 0.22U_0201_6.3V 2 1 CH215
PCIE_PTX_DRX_N15
PCIE_PTX_DRX_P15
<29>
<29> M.2 SSD
PCIE_PRX_DTX_N16 <29>
Slot#2

PCIe/SATA
GPP_G7/FAN_TACH_7 PCIE16_RXN/SATA3_RXN E42
2 1 CH202 PCIE_PTX_DRX_P11_C B33 PCIE16_RXP/SATA3_RXP A41 PCIE_PTX_DRX_N16_C 2 1 CH216 PCIE_PRX_DTX_P16 <29>
0.22U_0201_6.3V 0.22U_0201_6.3V
M.2 SSD <29> PCIE_PTX_DRX_P11
<29> PCIE_PTX_DRX_N11
<29> PCIE_PRX_DTX_P11
0.22U_0201_6.3V 2 1 CH203 PCIE_PTX_DRX_N11_C C33
K31
L31
PCIE11_TXP
PCIE11_TXN
PCIE11_RXP
PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP
A40

H42
PCIE_PTX_DRX_P16_C 0.22U_0201_6.3V 2 1 CH217
PCIE_PTX_DRX_N16
PCIE_PTX_DRX_P16
<29>
<29>

Slot#1 <29> PCIE_PRX_DTX_N11


AB33
PCIE11_RXN

GPP_F10/SCLOCK
PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN
H40
E45
AB35 F45
AA44 GPP_F11/SLOAD PCIE17_TXP/SATA4_TXP
AA45 GPP_F13/SDATAOUT0 K37 +3VS
GPP_F12/SDATAOUT1 PCIE18_RXN/SATA5_RXN G37
0.22U_0201_6.3V 2 1 CH204 PCIE_PTX_DRX_N14_C B38 PCIE18_RXP/SATA5_RXP G45
<29> PCIE_PTX_DRX_N14 PCIE_PTX_DRX_P14_C PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN
0.22U_0201_6.3V 2 1 CH205 C38 G44
<29> PCIE_PTX_DRX_P14 D39 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP PCH_SATALED# 1 2 10K_0402_5%
RH512
M.2 SSD <29> PCIE_PRX_DTX_N14
<29> PCIE_PRX_DTX_P14
0.22U_0201_6.3V 2 1 CH206 PCIE_PTX_DRX_N13_C
E37

C36
PCIE14_RXN/SATA1B_RXN
PCIE14_RXP/SATA1B_RXP GPP_E8/SATALED#
GPP_E0/SATAXPCIE0/SATAGP0
AD44
AG36
AG35
PCH_SATALED#

HDD_DET# M2_SLOT1_PEDET <29>


HDD_DET# RH513 1 2 10K_0402_5%

C
Slot#2 <29> PCIE_PTX_DRX_N13
<29> PCIE_PTX_DRX_P13
<29> PCIE_PRX_DTX_N13
0.22U_0201_6.3V 2 1 CH207 PCIE_PTX_DRX_P13_C B36
G35
PCIE13_TXN/SATA0B_TXN
PCIE13_TXP/SATA0B_TXP
PCIE13_RXN/SATA0B_RXN
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP3
AG39
AD35
M2_SLOT2_PEDET <29>
C

E35 AD31
<29> PCIE_PRX_DTX_P13 PCIE13_RXP/SATA0B_RXP GPP_F1/SATAXPCIE4/SATAGP4 AD38

M.2 SSD <29> PCIE_PTX_DRX_P12


<29> PCIE_PTX_DRX_N12
0.22U_0201_6.3V
0.22U_0201_6.3V
2
2
1 CH208
1 CH209
PCIE_PTX_DRX_P12_C
PCIE_PTX_DRX_N12_C
A35
B35
H33
PCIE12_TXP
PCIE12_TXN
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7
AC43
AB44

Slot#1 <29> PCIE_PRX_DTX_P12


<29> PCIE_PRX_DTX_N12
G33
J45
PCIE12_RXP
PCIE12_RXN
PCIE20_TXP/SATA7_TXP
GPP_F21/EDP_BKLTCTL
GPP_F20/EDP_BKLTEN
W36
W35
IGPU_INV_PWM
IGPU_ENBKL
<24>
<24>
K44 W42
PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN IGPU_ENVDD <24>
N38
N39 PCIE20_RXP/SATA7_RXP AJ3 H_THERMTRIP#_R RH79 1 2 620_0402_5%
HOST H_THERMTRIP# <9>
H44 PCIE20_RXN/SATA7_RXN THERMTRIP# AL3 H_PECI_R RH73 1 2 12.1_0402_1%
PCIE19_TXP/SATA6_TXP PECI H_PECI <9,43>
H43 AJ4
L39 PCIE19_TXN/SATA6_TXN PM_SYNC AK2 H_PM_SYNC_R <9>
PCIE19_RXP/SATA6_RXP PLTRST_PROC# PLTRST_CPU# <9>
L37 AH2
PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOWN <9>

SKL-H-PCH_BGA837 3 OF 12 REV = 1.3

UH1E
SPT-H_PCH

AW4 BB3
<56> CPU_DDI1HPD GPP_I0/DDPB_HPD0 GPP_I7/DDPC_CTRLCLK CPU_DDC2CLK <56>
<56> CPU_DDI2HPD AY2 BD6
AV4 GPP_I1/DDPC_HPD1 GPP_I8/DDPC_CTRLDATA BA5 CPU_DDC2DATA <56>
GPP_I2/DDPD_HPD2 GPP_I5/DDPB_CTRLCLK CPU_DDC1CLK <56>
BA4 BC4
B GPP_I3/DDPE_HPD3 GPP_I6/DDPB_CTRLDATA CPU_DDC1DATA <56> B
BE5
GPP_I9/DDPD_CTRLCLK BE6
GPP_I10/DDPD_CTRLDATA
Y44
GPP_F14 PROC_DETECT# <9>
BD7 V44
<24> EDP_HPD_CPU GPP_I4/EDP_HPD GPP_F23 W39
GPP_F22 L43
GPP_G23 STRAP3_PCH <51>
L44
GPP_G22 U35 STRAP5_PCH <51>
GPP_G21 R35
GPP_G20 BD36
GPP_H23
1

RH9
+3VS
100K_0402_5% SKL-H-PCH_BGA837 5 OF 12 REV = 1.3
2

2
RH584
10K_0402_5%

SKL eDP_HPD pull down 100K


1

DET <25>
2

@
RH585
10K_0402_5%
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/7) SATA,DDC,PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 16 of 80
5 4 3 2 1
5 4 3 2 1

PCH_RTCX1
SPT-H_PCH
UH1G

AR17 L1 PCH_XDP_CLK_N T19 PAD~D @ RH70


GPP_A16/CLKOUT_48 CLKOUT_ITPXDP_N L2 PCH_XDP_CLK_P T21 PAD~D @ 10M_0402_5%
G1 CLKOUT_ITPXDP_P J1 1 2 PCH_RTCX2
D <9> CPU_24MHZ_P CLKOUT_CPUNSSC_P CLKOUT_CPUPCIBCLK_N PCH_CPU_PCIBCLK_N <9> D
F1 J2
<9> CPU_24MHZ_N CLKOUT_CPUNSSC_N CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_P <9>
G2 YH1
<9> PCH_CPU_BCLK_P H2 CLKOUT_CPUBCLK_P N7 32.768KHZ_X1A000141000300

+1V_PCH
<9> PCH_CPU_BCLK_N
XTAL24_OUT
XTAL24_IN
A5
A6
CLKOUT_CPUBCLK_N

XTAL24_OUT
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
N8

L7
CLK_PEG_GPU#
CLK_PEG_GPU
<46>
<46> PEG 1 2

RH71 1 2 2.7K_0402_1% E1
XTAL24_IN

XCLK_BIASREF
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
L5
CLK_PCIE_N1
CLK_PCIE_P1
<29>
<29> NGFF1 1 1
+3VS
PCH_RTCX1
PCH_RTCX2
BC9
BD10 RTCX1
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
D3
F2
CLK_PCIE_N2
CLK_PCIE_P2
<29>
<29>
NGFF2 CH45
8.2P_0402_50V
CH46
8.2P_0402_50V

4
3
RP3
5
6
CLKREQ#_GPU
CLKREQ_PCIE#1 PEG <46> CLKREQ#_GPU
CLKREQ#_GPU
CLKREQ_PCIE#1
BC24
AW24
RTCX2

GPP_B5/SRCCLKREQ0#
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
E5
G4 CLK_PCIE_N3
CLK_PCIE_P3
<56>
<56>
Thunderbolt 2 2

2
1
7
8
CLKREQ_PCIE#2
CLKREQ_PCIE#4
NGFF1
<29>
<29>
<56>
CLKREQ_PCIE#1
CLKREQ_PCIE#2
CLKREQ_PCIE#3
CLKREQ_PCIE#2

CLKREQ_PCIE#4
AT24
BD25
GPP_B6/SRCCLKREQ1#
GPP_B7/SRCCLKREQ2#
GPP_B8/SRCCLKREQ3#
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
D5
E6 CLK_PCIE_N4
CLK_PCIE_P4
<30>
<30>
LAN
10K_0804_8P4R_5%
NGFF2
<30>
<28>
CLKREQ_PCIE#4
CLKREQ_PCIE#5
CLKREQ_PCIE#5
CLKREQ#_DGPU
BB24
BE25
AT33
GPP_B9/SRCCLKREQ4#
GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_N5
D8
D7
CLK_PCIE_N5 <28>
WLAN
4
3
RP5
5
6
CLKREQ#_DGPU
CLKREQ_PCIE#5 Thunderbolt <46>
<41,43> CLKREQ#_DGPU

GPU_GC6_FB_EN_R
AR31
BD32
BC32
GPP_H0/SRCCLKREQ6#
GPP_H1/SRCCLKREQ7#
GPP_H2/SRCCLKREQ8#
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
R8
R7
CLK_PCIE_P5

CLK_PCIE_N6
<28>

<41>
Caldera
2 7 BB31 GPP_H3/SRCCLKREQ9# CLKOUT_PCIE_P6 CLK_PCIE_P6 <41>
1 8 LAN BC33
BA33
GPP_H4/SRCCLKREQ10#
GPP_H5/SRCCLKREQ11#
GPP_H6/SRCCLKREQ12#
CLKOUT_PCIE_N7
CLKOUT_PCIE_P7
U5
U7
10K_0804_8P4R_5%
WLAN AW33
BB33
BD33
GPP_H7/SRCCLKREQ13#
GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_N8
W10
W11
Caldera R13
R11
GPP_H9/SRCCLKREQ15#

CLKOUT_PCIE_N15
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9
N3
N2
CLKOUT_PCIE_P15 CLKOUT_PCIE_P9
P1 P3 XTAL24_IN
R2 CLKOUT_PCIE_N14 CLKOUT_PCIE_N10 P2
CLKOUT_PCIE_P14 CLKOUT_PCIE_P10 RH72
W7 R3 1M_0402_5%~D
Y5 CLKOUT_PCIE_N13 CLKOUT_PCIE_N11 R4 1 2 XTAL24_OUT
C C
CLKOUT_PCIE_P13 CLKOUT_PCIE_P11
U2
U3 CLKOUT_PCIE_N12
CLKOUT_PCIE_P12 1 3
SKL-H-PCH_BGA837 7 OF 12 REV = 1.3 2 4
YH2
1 24MHZ 12PF +-10PPM 7M24090001 1
CH47 CH48
15P_0402_50V 15P_0402_50V
2 2

+3VS
SPT-H_PCH
UH1A

BD17 BB27 PCH_PLTRST#


GPP_A11/PME# GPP_B13/PLTRST# PCH_PLTRST# <41,46> 1
CH201
AG15 0.1U_0201_6.3V6K
AG14 RSVD P43
RSVD GPP_G16/GSXCLK TBT_FORCE_PWR <56> 2
AF17 R39
AE17 RSVD GPP_G12/GSXDOUT R36
RSVD GPP_G13/GSXSLOAD R42 UH3
GPP_G14/GSXDIN

5
AR19 R41 TC7SH08FU_SSOP5
AN17 TP2 GPP_G15/GSXSRESET# PCH_PLTRST# 1

P
TP1 B 4
PCH_SPI_SI_R Y PCIRST# <6,28,29,30,43,56>
RH1 1 2 1K_0402_1% BB29 AF41 2
<6> XDP_SPI_SI SPI0_MOSI GPP_E3/CPU_GP0 A

1
G
PCH_SPI_SO_R BE30 AE44
PCH_SPI_CS# BD31 SPI0_MISO GPP_E7/CPU_GP1 BC23 RH199

3
PCH_SPI_CLK_R BC31 SPI0_CS0# GPP_B3/CPU_GP2 BD24 100K_0402_5%
AW31 SPI0_CLK GPP_B4/CPU_GP3 +RTC_CELL
B +3V_PCH SPI0_CS1# BC36 B

2
PCH_SPI_WP#_R BC29 GPP_H18/SML4ALERT# BE34
<6> PCH_SPI_WP#_R PCH_SPI_HOLD#_R SPI0_IO2 GPP_H17/SML4DATA
BD30 BD39
SPI0_IO3 GPP_H16/SML4CLK

2
AT31 BB36
AN36 SPI0_CS2# GPP_H15/SML3ALERT# BA35 RH531
RH75 1 2 1K_0402_5% PCH_SPI_WP#_R AL39 GPP_D1/SPI1_CLK GPP_H14/SML3DATA BC35
GPP_D0/SPI1_CS# GPP_H13/SML3CLK 1M_0402_5%
AN41 BD35
RH78 1 2 1K_0402_5% PCH_SPI_HOLD#_R AN38 GPP_D3/SPI1_MOSI GPP_H12/SML2ALERT# AW35

1
AH43 GPP_D2/SPI1_MISO GPP_H11/SML2DATA BD34
AG44 GPP_D22/SPI1_IO3 GPP_H10/SML2CLK BE11
GPP_D21/SPI1_IO2 INTRUDER#

SKL-H-PCH_BGA837 1 OF 12 REV = 1.3

+3V_PCH

RPH5
PCH_SPI_HOLD# 4 5 PCH_SPI_HOLD#_R
PCH_SPI_SO 3 6 PCH_SPI_SO_R
1 PCH_SPI_SI PCH_SPI_SI_R
2 7
PCH_SPI_WP# PCH_SPI_WP#_R PCH_SPI_SI_R <9>
CH49 1 8
0.1U_0402_16V7K~D
2 15_0804_8P4R_5%
UH4
PCH_SPI_CS# 1 8
PCH_SPI_SO 2 /CS VCC 7 PCH_SPI_HOLD#
PCH_SPI_WP# 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK
4 /WP(IO2) CLK 5 PCH_SPI_SI PCH_SPI_CLK 1 2 PCH_SPI_CLK_R
GND DI(IO0) RH104 EMI@ 15_0402_1%
W25Q128FVSIQ_SO8

A A

Winbond ,W25Q128FVSIQ ,SA00005VV10


MXIC ,MX25L12873FM2I-10G ,SA00006O300
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/7) CLK,SPI,PLTRST
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 17 of 80
5 4 3 2 1
5 4 3 2 1

+3VALW

WAKE# RH453 1 2 10K_0402_5%


PCH_BATLOW# RH515 1 2 8.2K_0402_5%

RP2 AC_PRESENT RH533 1 2 8.2K_0402_5%


D
1 8 PCH_AZ_SDOUT D
<31> PCH_AZ_CODEC_SDOUT 2 7 PCH_AZ_SYNC WAKE_PCH# 1 2 10K_0402_5%
RH545
<31> PCH_AZ_CODEC_SYNC PCH_AZ_RST#
3 6
<31> PCH_AZ_CODEC_RST# 4 5 PCH_AZ_BITCLK
<31> PCH_AZ_CODEC_BITCLK
33_0804_8P4R_5% +3V_PCH

UH1D SPT-H_PCH ME_SUS_PWR_ACK RH506 1 @ 2 1M_0402_5%


SYS_RESET# RH571 1 @ 2 8.2K_0402_5%
PCH_AZ_BITCLK BA9 BB17
PCH_AZ_RST# BD8 HDA_BCLK GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AW22 CLKRUN#
BE7 HDA_RST# GPP_A8/CLKRUN# +3VS
<31> PCH_AZ_CODEC_SDIN0 HDA_SDI0
BC8 AR15
HDA_SDI1 GPD11/LANPHYPC
RH16 1 2 1K_0402_1% PCH_AZ_SDOUT BB7 AV13 CLKRUN# RH85 1 2 8.2K_0402_5%
<43> ME_EN PCH_AZ_SYNC HDA_SDO GPD9/SLP_WLAN#
BD9
HDA_SYNC BC14
DRAM_RESET# H_DRAMRST# <14,15>
BD1 BD23
BE2 RSVD_BD1 GPP_B2/VRALERT# AL27
RSVD_BE2 GPP_B1 AR27
RH39 1 2 30_0402_5% CPU_DISPA_SDO_R AM1 AUDIO GPP_B0 N44
<7> CPU_DISPA_SDO AN2 DISPA_SDO GPP_G17/ADR_COMPLETE AN24
<7> CPU_DISPA_SDI CPU_DISPA_BCLK_R DISPA_SDI GPP_B11
RH38 1 2 30_0402_5% AM2 AY1
<7> CPU_DISPA_BCLK DISPA_BCLK SYS_PWROK SYS_PWROK <43>
AL42 BC13 WAKE# RH4 2 @ 1 0_0402_5%
GPP_D8/I2S0_SCLK WAKE# PCIE_WAKE# <30,43>
AN42 BC15
AM43 GPP_D7/I2S0_RXD GPD6/SLP_A# AV15
AJ33 GPP_D6/I2S0_TXD SLP_LAN# BC26
AH44 GPP_D5/I2S0_SFRM GPP_B12/SLP_S0# AW15
AJ35 GPP_D20/DMIC_DATA0 GPD4/SLP_S3# BD15 PM_SLP_S3# <37,43,45>
GPP_D19/DMIC_CLK0 GPD5/SLP_S4# PM_SLP_S4# <43,45,65>
AJ38 BA13
AJ42 GPP_D18/DMIC_DATA1 GPD10/SLP_S5# PM_SLP_S5# <37,43>
GPP_D17/DMIC_CLK1 AN15
GPD8/SUSCLK PCH_BATLOW# SUSCLK <28,29>
BD13
GPD0/BATLOW# BB19 PCH_BATLOW# <56>
PCH_RTCRST# GPP_A15/SUSACK# ME_SUS_PWR_ACK SUSACK# <43>
C BC10 BD19 C
PCH_SRTCRST# BB10 RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK ME_SUS_PWR_ACK <43>
SRTCRST#
AW11 BD11 WAKE_PCH#
<43> PCH_PWROK EC_RSMRST# BA11 PCH_PWROK GPD2/LAN_WAKE# BB15 AC_PRESENT 2 1 DH1
<43> EC_RSMRST# RSMRST# GPD1/ACPRESENT VCIN1_AC_IN <37,43,61,62>
BB13 RB751V-40_SOD323-2
PCH_DPWROK AV11 SLP_SUS# AT13 PM_SLP_SUS# <43>
<43> PCH_DPWROK DSW_PWROK GPD3/PWRBTN# SYS_RESET# PBTN_OUT# <9,43>
BB41 AW1
PCH_SMBCLK GPP_C2/SMBALERT# SYS_RESET# SYS_RESET# <9>
AW44 BD26

SMBUS
PCH to DDR, XDP, FFS <14,15,38>
<14,15,38>
PCH_SMBCLK
PCH_SMBDATA
PCH_SMBDATA

SML0CLK
BB43
BA40
AY44
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C5/SML0ALERT#
GPP_B14/SPKR
PROCPWRGD
AM3

AT2
HDA_SPKR
H_CPUPWRGD
<31>
<9>

<41> SML0CLK GPP_C3/SML0CLK ITP_PMODE XDP_ITP_PMODE <6>


SML0DATA BB39 AR3
<41> SML0DATA GPP_C4/SML0DATA JTAGX PCH_JTAG_TCK <6,9>
AT27 JTAG AR2
AW42 GPP_B23/SML1ALERT#/PCHHOT# JTAG_TMS AP1 XDP_TMS <6,9>
SML1CLK
GPP_C6/SML1CLK JTAG_TDO XDP_TDO <6,9>
SML1DATA AW45 AP2
+RTC_CELL GPP_C7/SML1DATA JTAG_TDI AN3 XDP_TDI <6,9>
JTAG_TCK XDP_TCK <6>
RH83 1 2 20K_0402_5%~D PCH_SRTCRST#
SKL-H-PCH_BGA837 4 OF 12 REV = 1.3
1
CH52
1U_0603_10V6K~D

+RTC_CELL

RH84 1 2 20K_0402_5%~D PCH_RTCRST#


PCH_RTCRST# <43>
1
1

CH53 CLRP1
1U_0603_10V6K~D SHORT PADS
2

B 2 B

+3VS

+3V_PCH
2

RH460 1 2 1K_0402_5% SML1CLK SML1CLK 6 1


EC_SMB_CK2 <41,42,43,46,58>
RH461 1 2 1K_0402_5% SML1DATA QH5A
5

DMN66D0LDW-7

SML1DATA 3 4
EC_SMB_DA2 <41,42,43,46,58>
QH5B
+3VS DMN66D0LDW-7

RH463 1 2 1K_0402_5% PCH_SMBCLK

RH462 1 2 1K_0402_5% PCH_SMBDATA

RH501 1 2 499_0402_1% SML0CLK

RH502 1 2 499_0402_1% SML0DATA

A A

RH88 1 2 10K_0402_5% EC_RSMRST#

RH90 1 2 100K_0402_5% PCH_DPWROK

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/7) PM,HDA,SMB,JTAG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 18 of 80
5 4 3 2 1
5 4 3 2 1

SPT-H_PCH
UH1B

L27 AF5
<7>
<7>
<7>
DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
N27
C27
B27
DMI_RXN0
DMI_RXP0
DMI_TXN0
USB2N_1
USB2P_1
USB2N_2
AG7
AD5
AD7
USB20_N1
USB20_P1
USB20_N2
<35>
<35>
<35>
Right side JUSB1(Powershare,debug port)
D <7>
<7>
<7>
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
E24
G24
DMI_TXP0
DMI_RXN1
DMI_RXP1
USB2P_2
USB2N_3
USB2P_3
AG8
AG10
USB20_P2
USB20_N3
USB20_P3
<35>
<41>
<41>
Lef t si de J USB2 D

<7>
<7>
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
B28
A28
G27
DMI_TXN1
DMI_TXP1
DMI
USB2N_4
USB2P_4
AE1
AE2
AC2
USB20_N4
USB20_P4
<37>
<37> Cladera
<7> DMI_CTX_PRX_N2 USB20_N5 <28>
<7>
<7>
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
E26
B29
C29
DMI_RXN2
DMI_RXP2
DMI_TXN2
USB2N_5
USB2P_5
USB2N_6
AC3
AF2
AF3
USB20_P5
USB20_N6
<28>
<25>
ELC
<7>
<7>
<7>
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
L29
K29
DMI_TXP2
DMI_RXN3
DMI_RXP3
USB 2.0
USB2P_6
USB2N_7
USB2P_7
AB3
AB2
USB20_P6
USB20_N7
USB20_P7
<25>
<25>
<25>
Bluetooth
<7>
<7>
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3
B30
A30 DMI_TXN3
DMI_TXP3
USB2N_8
USB2P_8
AL8
AL7
AA1
USB20_N8
USB20_P8
<36>
<36> Touch screen
RH193 1 2 100_0402_1% PCIECOMP#
PCIECOMP
B18
C17 PCIE_RCOMPN
PCIE_RCOMPP
USB2N_9
USB2P_9
USB2N_10
AA2
AJ8
AJ7
Camera
H15
PCIE1_RXN/USB3_7_RXN
USB2P_10
USB2N_11
USB2P_11
W2
W3
JUSB3
G15 AD3
A16 PCIE1_RXP/USB3_7_RXP USB2N_12 AD2

PCIe/USB 3
B16 PCIE1_TXN/USB3_7_TXN USB2P_12 V2
B19 PCIE1_TXP/USB3_7_TXP USB2N_13 V1
C19 PCIE2_TXN/USB3_8_TXN USB2P_13 AJ11
E17 PCIE2_TXP/USB3_8_TXP USB2N_14 AJ13
G17 PCIE2_RXN/USB3_8_RXN USB2P_14
L17 PCIE2_RXP/USB3_8_RXP +3V_PCH
K17 PCIE3_RXN/USB3_9_RXN
B20 PCIE3_RXP/USB3_9_RXP AD43 USB_OC0# RPH6
C20 PCIE3_TXN/USB3_9_TXN GPP_E9/USB2_OC0# AD42 USB_OC1# USB_OC0# <35> USB_OC2# 1 8
PCIE3_TXP/USB3_9_TXP GPP_E10/USB2_OC1# USB_OC2# USB_OC1# <35> USB_OC3#
E20 AD39 2 7
G19 PCIE4_RXN/USB3_10_RXN GPP_E11/USB2_OC2# AC44 USB_OC3# USB_OC1# 3 6
B21 PCIE4_RXP/USB3_10_RXP GPP_E12/USB2_OC3# Y43 USB_OC0# 4 5
A21 PCIE4_TXN/USB3_10_TXN GPP_F15/USB2_OCB_4 Y41
K19 PCIE4_TXP/USB3_10_TXP GPP_F16/USB2_OCB_5 W44 10K_8P4R_5%
<30> PCIE_PRX_DTX_N5 PCIE5_RXN GPP_F17/USB2_OCB_6
L19 W43
LAN <30>
<30>
<30>
PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5
D22
C22
G22
PCIE5_RXP
PCIE5_TXN
PCIE5_TXP
GPP_F18/USB2_OCB_7

AG3 USB2_COMP RH109 1 2 113_0402_1%


C C
<28> PCIE_PRX_DTX_N6 E22 PCIE6_RXN USB2_COMP AD10 RH580 1 2 1K_0402_5%

WLAN <28>
<28>
<28>
PCIE_PRX_DTX_P6
PCIE_PTX_DRX_N6
PCIE_PTX_DRX_P6
B22
A23
L22
PCIE6_RXP
PCIE6_TXN
PCIE6_TXP
USB2_VBUSSENSE
RSVD_AB13
USB2_ID
AB13
AG2 RH581 1 2 1K_0402_5%

K22 PCIE7_RXN
C23 PCIE7_RXP
B23 PCIE7_TXN BD14
K24 PCIE7_TXP GPD7/RSVD
L24 PCIE8_RXN
C24 PCIE8_RXP
B24 PCIE8_TXN
PCIE8_TXP
SKL-H-PCH_BGA837 2 OF 12 REV = 1.3

SPT-H_PCH
UH1F
C11
<35> USB3TN1 USB3_1_TXN +3VS
B11 AT22
LPC/eSPI

B
Right side JUSB1 <35> USB3TP1
<35> USB3RN1
<35> USB3RP1
B7
A7
USB3_1_TXP
USB3_1_RXN
USB3_1_RXP
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
AV22
AT19
BD16
LPC_AD0
LPC_AD1
LPC_AD2
<43>
<43>
<43>
SERIRQ RH111 1 2 10K_0402_5%~D
B

B12 GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <43>


<36> USB3TN2 USB3_2_TXN/SSIC_1_TXN KB_RST#
A12 BE16 RH518 1 2 10K_0402_5%~D
Lef t si de J USB3 <36> USB3TP2
<36> USB3RN2
<36> USB3RP2
C8
B8
USB3_2_TXP/SSIC_1_TXP
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
GPP_A5/LFRAME#/ESPI_CS0#
GPP_A6/SERIRQ/ESPI_CS1#
GPP_A7/PIRQA#/ESPI_ALERT0#
BA17
AW17
AT17
SERIRQ
KB_RST#
LPC_FRAME#
SERIRQ <43>
<43>

B15 GPP_A0/RCIN#/ESPI_ALERT1# BC18 KB_RST# <43>


C15 USB3_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET#
K15 USB3_6_TXP
USB3_6_RXN
USB

K13 BC17 2 1
USB3_6_RXP GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_LPC <43>
AV19
B14 GPP_A10/CLKOUT_LPC1 RH89
<36> USB3TN5 USB3_5_TXN
C14 M45 22_0402_5%
Lef t si de J USB3 <36> USB3TP5
<36> USB3RN5
<36> USB3RP5
G13
H13
USB3_5_TXP
USB3_5_RXN
USB3_5_RXP
GPP_G19/SMI#
GPP_G18/NMI#
N43

D13 AE45
<41> USB3TP3 USB3_3_TXP/SSIC_2_TXP GPP_E6/DEVSLP2
C13 AG43
Caldera <41> USB3TN3
<41> USB3RP3
<41> USB3RN3
A9
B10
USB3_3_TXN/SSIC_2_TXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_RXN/SSIC_2_RXN
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0
GPP_F9/DEVSLP7
AG42
AB39
AB36
DEVSLP0 <29>
SATA

B13 GPP_F8/DEVSLP6 AB43


<35> USB3TP4 USB3_4_TXP GPP_F7/DEVSLP5
A14 AB42
Lef t si de J USB2 <35> USB3TN4
<35> USB3RP4
<35> USB3RN4
G11
E11
USB3_4_TXN
USB3_4_RXP
USB3_4_RXN
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3
AB41
DEVSLP3 <29>

SKL-H-PCH_BGA837 6 OF 12 REV = 1.3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/7) DMI,PCIE,USB,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 19 of 80
5 4 3 2 1
5 4 3 2 1

+3V_PCH

SKL@
CPU_ID RH23 1 2 10K_0201_5%
RH24 1 2 10K_0201_5%

KBL@

D +3V_PCH D

N17E@
GPU_ID RH25 1 2 10K_0201_5%
RH26 1 2 10K_0201_5%

N17P@

SPT-H_PCH +3VS
UH1K

AT29 AL44
+3VS AR29 GPP_B22/GSPI1_MOSI GPP_D9 AL36
EC_SCI# GPP_B21/GSPI1_MISO GPP_D10 CPU_ID DGPU_HOLD_RST# <46>
AV29 AL35
<43> EC_SCI# BC27 GPP_B20/GSPI1_CLK GPP_D11 AJ39 DGPU_PWR_EN DGPU_PWR_EN 1 2 10K_0201_5%
RH537
<51> VROM_SEL GPP_B19/GSPI1_CS# GPP_D12 DGPU_PWR_EN <43,55>
BD28 AJ43 GPU_ID
BD27 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS# AL43
AW27 GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS# AK44
<43,46> GC6_FB_EN AR24 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL AK45
EC_SCI# <46> GC6_EVENT# GPP_B15/GSPI0_CS# GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA
RH521 1 2 10K_0402_5%
AV44
UART_2_CRXD_DTXD <24,43> EDP_SW GPP_C9/UART0_TXD
RC62 2 1 49.9K_0402_1% BA41
WL_OFF# AU44 GPP_C8/UART0_RXD
2 1 49.9K_0402_1% UART_2_CTXD_DRXD <28> WL_OFF# BT_OFF# AV43 GPP_C11/UART0_CTS#
RC63
<28> BT_OFF# GPP_C10/UART0_RTS# BC38
RC65 2 @ 1 49.9K_0402_1% UART_2_CCTS_DRTS AU41 GPP_H20/ISH_I2C0_SCL BB38
<27> HDMI_HPD_PCH GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA
AT44
DGPU_PWROK <26> DP_HPD_PCH GPP_C14/UART1_RTS#/ISH_UART1_RTS#
RH516 1 2 10K_0402_5% AT43 BD38
AU43 GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL BE39
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
C C
AN43
<56> TBT_CIO_PLUG_EVENT# UART_2_CCTS_DRTS GPP_C23/UART2_CTS#
AN44
UART_2_CTXD_DRXD AR39 GPP_C22/UART2_RTS# BC22
UART_2_CRXD_DTXD AR45 GPP_C21/UART2_TXD GPP_A23/ISH_GP5 BD18
GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BE21
AR41 GPP_A21/ISH_GP3 BD22 XMP2 <64>
<56> RTD3_USB_PWR_EN GPP_C19/I2C1_SCL GPP_A20/ISH_GP2 XMP1 <64>
AR44 BD21
<56> RTD3_CIO_PWR_EN GPP_C18/I2C1_SDA GPP_A19/ISH_GP1
AR38 BB22
AT42 GPP_C17/I2C0_SCL GPP_A18/ISH_GP0 BC19 DGPU_PRSNT#
AM44 GPP_C16/I2C0_SDA GPP_A17/ISH_GP7
DGPU_PWROK AJ44 GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA
<43> DGPU_PWROK GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

2
RH135
SKL-H-PCH_BGA837 11 OF 12 REV = 1.3 10K_0402_5%

1
+5VALW

JWDB
1
UART_2_CTXD_DRXD 2 1
UART_2_CRXD_DTXD 3 2 5
4 3 G1 6
4 G2
ACES_88266-04001
B B
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/7) I2C,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 20 of 80
5 4 3 2 1
5 4 3 2 1

+1VALW @ +1V_PCH_PRIM
SPT-H_PCH
UH1H
JP2
+1V_PCH
1 2 AA23
AA26 VCCPRIM_1P0 +3VALW
PAD-OPEN 43x39 AA28 VCCPRIM_1P0 AL22
VCCPRIM_1P0 VCCPRIM_1P0

CORE
AC23
+1VALW @ +1V_PCH AC26 VCCPRIM_1P0 BA24
AC28 VCCPRIM_1P0 VCCDSW_3P3
JP1 VCCPRIM_1P0

VCCGPIO
D D
+1V_PCH +1V_VCCDSW AE23 BA31
1 2 AE26 VCCPRIM_1P0 VCCPGPPA BC42
Y23 VCCPRIM_1P0 VCCPGPPBCH BD40
PAD-OPEN 43x39 Y25 VCCPRIM_1P0 VCCPGPPBCH AJ41 +3V_PCH
+1V_MPHY BA29 VCCPRIM_1P0 VCCPGPPEF AL41
DCPDSW_1P0 VCCPGPPEF AD41
N17 VCCPGPPG AN5
RH12 1 @ 2 0_0805_5% R19 VCCCLK1 VCCPRIM_3P3
U20 VCCCLK3 +1V_PCH
V17 VCCCLK4 AD15
R17 VCCCLK2 VCCPRIM_1P0 AD13
VCCCLK2 VCCATS +3VS
+1V_MPHY BA20
K2 VCCRTCPRIM_3P3 BA22
K3 VCCCLK5 VCCRTC BA26 1 2 +RTC_CELL
VCCCLK5 DCPRTC CH70 0.1U_0402_10V7K~D
U21 AJ20
VCCMPHY_1P0 VCCPRIM_1P0 +1V_PCH_PRIM

MPHY
U23 AJ21
U25 VCCMPHY_1P0 VCCPRIM_1P0 AJ23 +3V_PCH
+1V_MPHY U26 VCCMPHY_1P0 VCCPRIM_1P0 AJ25
V26 VCCMPHY_1P0 VCCPRIM_1P0
A43 VCCMPHY_1P0 BE41
+1V_PCH B43 VCCMPHYPLL_1P0 VCCSPI BE43
VCCMPHYPLL_1P0 VCCSPI +3V_PCH
RF@ C44 BE42
RH6 C45 VCCPCIE3PLL_1P0 VCCSPI
0_0603_5% VCCPCIE3PLL_1P0 BC44
+3V_PCH 1 2 V28 VCCPGPPD BA45
VCCAPLLEBB_1P0 VCCPGPPD

USB
+3VALW AC17 BC45
RF@ AJ5 VCCPRIM_1P0 VCCPGPPD BB45
RH7 AL5 VCCUSB2PLL_1P0 VCCPGPPD +3V_PCH
0_0603_5% AN19 VCCUSB2PLL_1P0 BD3
1 2 BA15 VCCHDAPLL_1P0 VCCPRIM_3P3 BE3
VCCHDA VCCPRIM_3P3 BE4
W15 VCCPRIM_3P3
VCCDSW_3P3
SKL-H-PCH_BGA837 8 OF 12 REV = 1.3

0.1U_0402_10V7K

0.1U_0402_10V7K
C C

CH3
@RF@

CH4
@RF@
1 1

2 2

+1V_VCCDSW +1V_PCH +3V_PCH +3V_PCH +3VS +3VALW +3V_PCH +3V_PCH


0.1U_0402_10V7K
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
CH200

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
1 1 1 1 1 1 1 1
CH176

CH185

CH188

CH82
CH189

CH190

CH192
2 2 2 2 2 2 2 2

Close to BA29 Close to AC17 Close to BA15 Close to AN5 Close to AD13 Close to W15 Close to AD41 Close to BC42,BD40

B +1V_MPHY +1V_MPHY +RTC_CELL B


+1V_PCH +3V_PCH +3V_PCH
22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1U_0402_6.3V6K~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1U_0402_6.3V6K~D

22U_0805_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
1 1 1 1 1 1 1 1 1 1 1 1 1
CH179

CH180

CH183

CH187

CH80
CH177

CH178

CH181

CH182

CH184

CH186

CH173

CH191
2 2 2 2 2 2 2 2 2 2 2 2 2

Close to K2,K3 Close to A43,B43 Close to U21,U23,U25,U26,V26 Close to BA20 Close to BA22 Close to AJ41,AL41

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 21 of 80
5 4 3 2 1
5 4 3 2 1

SPT-H_PCH
UH1I UH1L
D D
SPT-H_PCH
AC18 AR5 C42 AB11
AN4 VSS VSS AR7 D10 VSS VSS AB7
AN10 VSS VSS U15 D12 VSS VSS AB14 UH1J SPT-H_PCH
BE14 VSS VSS AL4 D15 VSS VSS AB31
BE18 VSS VSS AE29 D16 VSS VSS AB32
BE23 VSS VSS AE4 D17 VSS VSS AB38 AR22
BE28 VSS VSS AE42 D19 VSS VSS AB4 BD2 RSVD W13
BE32 VSS VSS AF18 D21 VSS VSS AB5 BD45 VSS RSVD U13
BE37 VSS VSS AF20 D24 VSS VSS AC1 BD44 VSS RSVD
BE40 VSS VSS AF21 D25 VSS VSS AC20 BE44 VSS P31
BE9 VSS VSS AF23 D27 VSS VSS AC21 D45 VSS RSVD N31
C10 VSS VSS AF25 D29 VSS VSS AC25 A42 VSS RSVD
C2 VSS VSS AF26 D30 VSS VSS AC29 B45 VSS P27
C28 VSS VSS AF28 D31 VSS VSS AC45 B44 VSS RSVD R27
C37 VSS VSS AF29 D33 VSS VSS AB8 A4 VSS RSVD N29
J7 VSS VSS AG11 D35 VSS VSS AD11 A3 VSS RSVD P29
K10 VSS VSS AG13 D36 VSS VSS AD14 B2 VSS RSVD AN29
K27 VSS VSS AG31 E13 VSS VSS AB15 A2 VSS RSVD R24
K33 VSS VSS AG32 E15 VSS VSS AD32 B1 VSS RSVD P24
K36 VSS VSS AG33 E31 VSS VSS AD33 BB1 VSS RSVD
K4 VSS VSS AG38 E33 VSS VSS AD36 BC1 VSS AT3
K42 VSS VSS AG4 F44 VSS VSS AD4 A44 VSS PREQ# AT4 XDP_PREQ# <6,9>
K43 VSS VSS AH1 F8 VSS VSS AD8 VSS PRDY# AY5 XDP_PRDY# <6,9>
L12 VSS VSS AH17 G42 VSS VSS AE18 C1 CPU_TRST# AL2 CPU_XDP_TRST# <6,9>
L13 VSS VSS AH18 G9 VSS VSS AE20 D1 RSVD PCH_TRIGOUT AK1 PCH_TRIGGER <10>
L15 VSS VSS AH20 H17 VSS VSS AE21 RSVD PCH_TRIGIN CPU_TRIGGER <10>
L4 VSS VSS AH21 H19 VSS VSS AE25
L41 VSS VSS AH23 H22 VSS VSS AE28
L8 VSS VSS AH25 H24 VSS VSS AL10 SKL-H-PCH_BGA837
M35 VSS VSS AH26 H27 VSS VSS AL11 10 OF 12
C M42 VSS VSS AH28 H29 VSS VSS AL13 REV = 1.3 C
N10 VSS VSS AH29 H3 VSS VSS AL17
N15 VSS VSS AH45 H35 VSS VSS AL19
N19 VSS VSS AJ10 J10 VSS VSS AL24
N22 VSS VSS AJ14 J11 VSS VSS AL29
N24 VSS VSS AJ15 J3 VSS VSS AL32
N35 VSS VSS AJ17 J39 VSS VSS AL33
N36 VSS VSS AJ18 J5 VSS VSS AL38
N4 VSS VSS AJ26 T42 VSS VSS AM15
N41 VSS VSS AJ28 U10 VSS VSS AM17
N5 VSS VSS AJ29 U11 VSS VSS AM19
P17 VSS VSS AJ31 U14 VSS VSS AM22
P19 VSS VSS AJ32 U17 VSS VSS AM24
P22 VSS VSS AJ36 U18 VSS VSS AM27
P45 VSS VSS AK4 U28 VSS VSS AM29
R10 VSS VSS AK42 U29 VSS VSS AM45
R14 VSS VSS AU7 U31 VSS VSS AN11
R22 VSS VSS AV17 U32 VSS VSS AN22
R29 VSS VSS AV24 U33 VSS VSS AN27
R33 VSS VSS AV27 U38 VSS VSS AN31
R38 VSS VSS AV31 U4 VSS VSS AN39
R5 VSS VSS AV33 U8 VSS VSS AN7
T1 VSS VSS AV6 V18 VSS VSS AN8
T2 VSS VSS AW13 V20 VSS VSS AP11
T4 VSS VSS AW19 V21 VSS VSS AP4
Y18 VSS VSS AW29 V23 VSS VSS AR33
Y20 VSS VSS AW37 V25 VSS VSS AR34
Y21 VSS VSS AW9 V29 VSS VSS AR42
Y26 VSS VSS AY38 V3 VSS VSS AR9
Y28 VSS VSS AY45 V45 VSS VSS AT10
Y29 VSS VSS B25 W14 VSS VSS AT15
A18 VSS VSS B3 W31 VSS VSS AT36
B A25 VSS VSS B37 W32 VSS VSS AT9 B
A32 VSS VSS B40 W33 VSS VSS AU1
A37 VSS VSS B6 W38 VSS VSS AU35
AA17 VSS VSS BA1 W4 VSS VSS AU36
AA18 VSS VSS BB11 W8 VSS VSS AU39
AA20 VSS VSS BB16 Y17 VSS VSS AU45
AA21 VSS VSS BB21 VSS VSS C4
AA25 VSS VSS BB25 VSS
AA29 VSS VSS BB30
AA4 VSS VSS BB34
AA42 VSS VSS BC2
AB10 VSS VSS BD43
VSS VSS SKL-H-PCH_BGA837
12 OF 12
SKL-H-PCH_BGA837 REV = 1.3
9 OF 12
REV = 1.3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 22 of 80
5 4 3 2 1
5 4 3 2 1

+3VS

1
RV19
100K_0402_5%
+3VS

2
+3VS
MUX_EDP_AUXN <25>
@
MUX_EDP_AUXP <25>
RV21
4.7K_0402_1%~D

1
D D
1 1 RV20 I2C_CTL_EN
CV437 CV436 100K_0402_5% I2C_CTL_EN
IN1_AEQ# , IN2_AEQ# 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D UV21 I2C Control Enable; Internal pull down at ~150KΩ , 3. 3V I / O.
Automat i c E Q di sabl e; I nt er nal pull do wn at ~150K Ω, 3. 3V I /O.

1
21 L: Pin control mode is selected

2
L: Automat i c E Q enabl e ( def aul t) 2 2 26 VDD33
VDD33
@ H: I2C control is selected with default address 0x66/67
H: Automat i c E Q di sabl e 35 RV22
49 VDD33 32 4.7K_0402_1%~D
M: I2C control is selected with alternat i ve addr ess 0x D8/ D9
60 VDD33 OUT_AUXp_SCL 31

2
VDD33 OUT_AUXn_SDA
IN2_PEQ# 51
IN1_PEQ# 52 IN2_PEQ/SCL_CTL 53 I2C_CTL_EN
RV634 1 2 4.7K_0402_1%~D 59 IN1_PEQ/SDA_CTL I2C_CTL_EN
RV635 1 2 4.7K_0402_1%~D 58 IN1_AEQ#
+3VS IN2_AEQ# 56 PI0
PI0 38 PC0
0.1U_0201_6.3V6K 2 1 CV416 GPU_TX0P_C 1 PC0 55 PC1
<47> GPU_TX0P 2 1 GPU_TX0N_C 2 IN1_D0p PC1
0.1U_0201_6.3V6K CV417
<47> GPU_TX0N 2 1 GPU_TX1P_C 4 IN1_D0n
0.1U_0201_6.3V6K CV418 RV23 +3VS
<47> GPU_TX1P 2 1 GPU_TX1N_C 5 IN1_D1p
0.1U_0201_6.3V6K CV419 1M_0402_5%
GPU <47>
<47>
GPU_TX1N
GPU_TX2P
0.1U_0201_6.3V6K 2 1 CV420 GPU_TX2P_C 6 IN1_D1n
IN1_D2p CA_DET
48 2 1

2
0.1U_0201_6.3V6K 2 1 CV421 GPU_TX2N_C 7
<47> GPU_TX2N 2 1 GPU_TX3P_C 9 IN1_D2n
0.1U_0201_6.3V6K CV422 @
<47> GPU_TX3P 2 1 GPU_TX3N_C 10 IN1_D3p 46
0.1U_0201_6.3V6K CV423 RV623
<47> GPU_TX3N IN1_D3n OUT_D0p 45 MUX_EDP_A0P <25>
4.7K_0402_1%~D
2 1 CV424 GPU_AUXP/DDC_C 28 OUT_D0n 43 MUX_EDP_A0N <25>
0.1U_0201_6.3V6K PI0

1
<47> GPU_AUXP/DDC 2 1 CV425 GPU_AUXN/DDC_C 27 IN1_AUXp OUT_D1p 42 MUX_EDP_A1P <25>
0.1U_0201_6.3V6K
<47> GPU_AUXN/DDC 23 IN1_AUXn OUT_D1n 40 MUX_EDP_A1N <25>
PI0 Auto test enable; Internal pull down at ~150KΩ , 3. 3V I / O.
2 1 RV669 22 IN1_SCL OUT2_D2p 39 MUX_EDP_A2P <25> L: Auto test disable & input of fset cancell at i on enabl e ( def ault)
100K_0201_1%
IN1_SDA OUT2_D2n MUX_EDP_A2N <25>

1
100K_0201_1% 2 1 RV670 37 H: Auto test enable & input of fset cancell at i on enable
OUT_D3p 36 MUX_EDP_A3P <25>
@
0.1U_0201_6.3V6K 2 1 CV426 CPU_EDP_P0_C 11 OUT_D3n MUX_EDP_A3N <25>
RV622
M: Auto test disable & input of fset cancell at i on di s able
<7> CPU_EDP_TX0P 2 1 CPU_EDP_N0_C 12 IN2_D0p
0.1U_0201_6.3V6K CV427 4.7K_0402_1%~D
<7> CPU_EDP_TX0N 2 1 CPU_EDP_P1_C 14 IN2_D0n 54 EDP_SW
0.1U_0201_6.3V6K CV428

2
<7> CPU_EDP_TX1P 2 1 CPU_EDP_N1_C 15 IN2_D1p SW
0.1U_0201_6.3V6K CV429
CPU <7>
<7>
<7>
CPU_EDP_TX1N
CPU_EDP_TX2P
CPU_EDP_TX2N
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
2
2
2
1
1
1
CV430
CV431
CPU_EDP_P2_C
CPU_EDP_N2_C
CPU_EDP_P3_C
16
17
19
IN2_D1n
IN2_D2p
IN2_D2n
OUT_HPD
44
EDP_HPD <25>
0.1U_0201_6.3V6K CV432
<7> CPU_EDP_TX3P 2 1 CPU_EDP_N3_C 20 IN2_D3p
0.1U_0201_6.3V6K CV433
<7> CPU_EDP_TX3N IN2_D3n 34
C 0.1U_0201_6.3V6K 2 1 CV434 CPU_EDP_AUX_C 30 REXT 47 C
<7> CPU_EDP_AUX 2 1 CV435 CPU_EDP_AUX#_C 29 IN2_AUXp CEXT
0.1U_0201_6.3V6K
<7> CPU_EDP_AUX# 25 IN2_AUXn
24 IN2_SCL 8
IN2_SDA GND 1

1
18
GND 33 CV438 RV24
3 GND 41 2.2U_0402_6.3V6M~D 4.99K_0402_1%
<46> EDP_HPD_GPU 13 IN1_HPD GND 57 2
<16> EDP_HPD_CPU IN2_HPD GND 61

2
Epad 50
PD
+3VS SA000060U10
PS8331BQFN60GTR-A2_QFN60_5X9
2

RV629
4.7K_0402_1%~D
1

IN1_PEQ#
1

RV628
4.7K_0402_1%~D
2

IN1_PEQ# , IN2_PEQ#
Programmable input equalizat i on l evel s; I nt er nal pull do wn at ~150K Ω, 3. 3V I /O
.
+3VS L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
2

RV631
4.7K_0402_1%~D
1

B B
+3VS
IN2_PEQ#
1

2
@
RV630 RV625
4.7K_0402_1%~D 4.7K_0402_1%~D
PC0
2

1
PC0 AUX intercept i on di sabl e f or Port y ( y = 1, 2). I nt er nal pull do wn at ~150K Ω, 3. 3V I /O;
+5VS L: AUX intercept i on enabl e, dri ver c onf i gur at i on i s set by l i nk tr ai ni ng (defaut)l

1
H: AUX intercept i on di sabl e, dri ver out put wit h f i xed 80 0mV and 0d B
@
RV624
M: AUX intercept i on di sabl e, dri ver out put wit h f i xed 40 0mV and 0d B
1
4.7K_0402_1%~D
CV484 +3VS

2
0.1U_0402_16V4Z~D UV22
2 16
Vcc
2

4
2 1A 7 INV_PWM <25>
RV659
<46> DGPU_INV_PWM 3 1B1 2A 9 ENVDD <25>
<16> IGPU_INV_PWM 1B2 3A ENBKL <43> 10K_0402_5%
5 12
<46> DGPU_ENVDD 6 2B1 4A
1

<16> IGPU_ENVDD 11 2B2 15


<46> DGPU_ENBKL 10 3B1 OE# 1 EDP_SW
<16> IGPU_ENBKL 14 3B2 S EDP_SW <20,43>
13 4B1 8
4B2 GND +3VS
SN74CBT3257CPWR_TSSOP16

2
@
RV627
4.7K_0402_1%~D
PC1

1
PC1 Output swing adjustment for Port y (y = 1, 2). Internal pull down at ~150KΩ , 3. 3V I / O;
S1 OE output function L: default

1
H: +20%
A @ A
RV626
M: -16.7%
L L A=B1 DGPU
4.7K_0402_1%~D
H L A=B2 IGPU

2
X H

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP MUX PS8331B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 24 of 80
5 4 3 2 1
A B C D E

LCD power control


+3VS +LCDVDD

UV17
5 1
1 IN OUT 1
10P_0402_50V8J

4.7U_0805_10V4Z

0.1U_0402_10V7K

4.7U_0805_10V4Z

10P_0402_50V8J
1 2
GND
1

CV372
@RF@

CV5
1 1
eDP connector

1
CV9

CV10

CV373
@RF@
4 3 1 2
EN OC +3VS
2

2 SY6288C20AAC_SOT23-5 RV45

2
10K_0201_1% 2 2 JEDP
0.1U_0201_6.3V6K 2 1 CV1 EDP_TX0_C 1
<24> MUX_EDP_A0P 2 1 CV2 EDP_TX0#_C 2 1 41
0.1U_0201_6.3V6K
<24> MUX_EDP_A0N 3 2 G1 42
0.1U_0201_6.3V6K 2 1 CV3 EDP_TX1_C 4 3 G2 43
<24> ENVDD <24> MUX_EDP_A1P 2 1 CV4 EDP_TX1#_C 5 4 G3 44
0.1U_0201_6.3V6K
<24> MUX_EDP_A1N 6 5 G4
6
2
0.1U_0201_6.3V6K 2 1 CV8 EDP_TX2_C 7
<24> MUX_EDP_A2P 2 1 CV6 EDP_TX2#_C 8 7
RV600 0.1U_0201_6.3V6K
100K_0201_1% <24> MUX_EDP_A2N 9 8
0.1U_0201_6.3V6K 2 1 CV7 EDP_TX3_C 10 9
<24> MUX_EDP_A3P 2 1 CV11 EDP_TX3#_C 11 10
0.1U_0201_6.3V6K
<24> MUX_EDP_A3N
1

12 11
0.1U_0201_6.3V6K 2 1 CV12 EDP_AUX_C 13 12
<24> MUX_EDP_AUXP 2 1 CV13 EDP_AUX#_C 14 13
0.1U_0201_6.3V6K
<24> MUX_EDP_AUXN 15 14
16 15
<24> EDP_HPD USB20_N6 17 16
USB20_N6 USB20_P6 18 17
<19> USB20_N6 USB20_CAM_N7_R 19 18
USB20_P6 USB20_CAM_P7_R 20 19
<19> USB20_P6 21 20
<46> G-SYNC# 21
22
<31> MIC_DATA 23 22
<31> MIC_CLK 24 23
+3VS_CAM 24
2

25
2 26 25 2
2

+LCDVDD 26
27
27

1
28
<16> DET 29 28
@ESD@ @EMI@
DV2 RV13 30 29
L03ESDL5V0CG3-2_SOT-523-3 0_0402_5% 31 30
<43> LCD_TEST 31
1

32
+3VS_CAM

2
33 32
+VDD_TOUCH
1

34 33
2 1 <43> TS_EN DISPOFF# 35 34
<43> BKOFF# 35

1
@RF@ 36
<24> INV_PWM 37 36
CV374 DV1
10P_0402_50V8J RB751V-40_SOD323-2 38 37

2
38

1
39
1 2 USB20_CAM_P7_R RV1 RV8 40 39
<19> USB20_P7 +INV_PWR_SRC 40
10K_0201_1% 100K_0201_1%

1
CV375 ACES_50473-0400M-P01
4 3 USB20_CAM_N7_R 10P_0402_50V8J CONN@
<19> USB20_N7

2
@RF@

2
MCM1012B900F06BP_4P
LV2
3

EMI@
@ESD@
DV4
TVNST52302AB0_SOT523-3
1

3
LCD backlight power control 3

Touch screen panel power


B+
+INV_PWR_SRC +3VS +VDD_TOUCH
+LCDVDD IR camera pindef i ne :
IR_LED+

10U_0603_6.3V6M
0.1U_0402_10V7K
6 1 @ 2
5 1 1
IR_LED+

CV17

CV18
4
2
1
1 RV81
0_0402_5%
1 IR_LED+/NC
S

1 CV21 CV19
2 2 IR_LED-/DET , connect to PCH GPIO
1000P_0402_50V7K
CV15

100K_0402_5%
RV9

CV14 4.7U_0805_10V4Z 0.1U_0402_10V7K


IR_LED-
1

0.1U_0603_25V7K 2 2
G

1
QV1
IR_LED-
3

SI3457CDV-T1-GE3_TSOP6 2

2 Place close to JEDP Diglog_loop , connect to PCH GPIO


Camera power
2

PWR_SRC_ON
DGND
D+
1

+3VS +3VS_CAM
RV12
D-
100K_0402_5% USB3V3
1 @ 2 MIC_SIG
2

RV47 MIC_CLK
1

4 D 4
0_0402_5%
<43> EN_INVPWR
2 QV2 DGND
G 2N7002W-T/R7_SOT323-3
S
3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP/camera/TS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-D581P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 07, 2016 Sheet 25 of 80
A B C D E
A B C D E

+3VS JDP
+5VS 1
1 mDP_HPD 2 GND 1
CV26 1 2 0.1U_0201_6.3V6K mDP_LANE_P0_C 3 HOT_PLUG
<47> GPU_mDP_P0 DP_CBL_DET 4 LANE0_P
mDP_LANE_N0_C CONFIG1

2.2K_0201_5%

2.2K_0201_5%
1 CV27 1 2 0.1U_0201_6.3V6K 5
<47> GPU_mDP_N0 LANE0_N

1
RV18 1 2 5.1M_0402_5% DISP_CEC 6
CONFIG2

RV671

RV672
CV23 RV16 7
0.1U_0201_6.3V6K 8 GND
100K_0201_5% GND
2 CV28 1 2 0.1U_0201_6.3V6K mDP_LANE_P1_C 9
<47> GPU_mDP_P1 1 2 mDP_LANE_P3_C 10 LANE1_P
CV29 0.1U_0201_6.3V6K
<47> GPU_mDP_P3

2
UV3 CV30 1 2 0.1U_0201_6.3V6K mDP_LANE_N1_C 11 LANE3_P
16 <47> GPU_mDP_N1 1 2 mDP_LANE_N3_C 12 LANE1_N
CV31 0.1U_0201_6.3V6K
Vcc 4 DISP_CLK_AUXP_CONN <47> GPU_mDP_N3 13 LANE3_N
GPU_DPC_AUX 0.1U_0201_6.3V6K 2 1 CV24 DP_AUXP_C 2 1A 7 DISP_DAT_AUXN_CONN 14 GND
mDP_AUX_SCL 3 1B1 2A 9 CV32 1 2 0.1U_0201_6.3V6K mDP_LANE_P2_C 15 GND 21
GPU_DPC_AUX# 0.1U_0201_6.3V6K 2 1 CV25 DP_AUXN_C 5 1B2 3A 12 <47> GPU_mDP_P2 DISP_CLK_AUXP_CONN 16 LANE2_P GND1 22
2B1 4A AUX_CH_P GND2

2
mDP_AUX#_SDA 6 CV33 1 2 0.1U_0201_6.3V6K mDP_LANE_N2_C 17 23
11 2B2 15 <47> GPU_mDP_N2 DISP_DAT_AUXN_CONN 18 LANE2_N GND3 24
RV15
10 3B1 OE# 1 DP_CBL_DET 19 AUX_CH_N GND4
3B2 S 100K_0201_5% GND
14 20
4B1 DP_PWR

1
13 8

1
4B2 GND RV17 +3VS +3VS_DP ACON_MAR2F-20K1800
SN74CBT3257CPWR_TSSOP16 1M_0201_1% CONN@
1 2

10U_0402_6.3V6M

0.1U_0201_6.3V6K
FV2
1.1A_6V_SPR-P110 1 1

CV34

CV35
2 2

2 Funct i on S OE# 2

mini DP cable L L
mini DP dongle H L

mDP_AUX_SCL

mDP_AUX#_SDA +3VS

QX2
S TR METR3904W-G NPN SOT323-3

1
C
2 1 2 mDP_HPD
B
E RX2

3
150K_0402_5% 1
+1V8_AON <20> DP_HPD_PCH
CX1

1
0.1U_0402_16V7K

1
3 RX4 2 3
RX5 100K_0402_5%
10K_0402_5%
+1.8VS

2
2 @ 1 GPU_DPC_AUX
<47> mDP_AUX_SCL

2
RV619 CV20
<46> DP_HPD_GPU# 1 2
0_0402_5%

2 @ 1 GPU_DPC_AUX# 0.1U_0402_16V7K
<47> mDP_AUX#_SDA

5
RV618

VCC
0_0402_5% QV97A 1
DMN53D0LDW-7 2N SOT363-6 2 4 IN B
OUT Y 2 DGPU_PEX_RST#

GND
IN A DGPU_PEX_RST# <27,46,55>
1

1
RV664 RV665
100K_0402_5% 100K_0402_5%

3
UX1
NL17SZ08DFT2G_SC70-5
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini DP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-D581P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 07, 2016 Sheet 26 of 80
A B C D E
5 4 3 2 1

+HDMI_5V_OUT
+5VS

1 EMI@ 2 TMDS_L_TXCN 1 2 TMDS_R_TXCN 1 2


RV641 5.6_0402_1%

10U_0603_6.3V6M~D

0.1U_0201_6.3V6K
LV3 @EMI@ 6.04 +-1% 0402 FV3

2
2 1 TMDS_C_TXCN 1 2 RV673 1.1A_6V_SPR-P110
<47> TMDS_TXCN 1 1

CV1068

CV1069
CV1057 0.1U_0201_6.3V6K RV500
158_0402_1%
2 1 TMDS_C_TXCP 4 3
D <47> TMDS_TXCP EMI@ 2 2 D
CV1058 0.1U_0201_6.3V6K 6.04 +-1% 0402

1
HCM1012GH900BP_4P RV674
1 EMI@ 2 TMDS_L_TXCP 1 2 TMDS_R_TXCP
RV640 5.6_0402_1%

1 EMI@ 2 TMDS_L_TX0N 1 2 TMDS_R_TX0N


RV643 5.6_0402_1% +3V3_SYS
LV4 @EMI@ 6.04 +-1% 0402

1
2 1 TMDS_C_TX0N 1 2 RV27
<47> TMDS_TX0N
CV1060 0.1U_0201_6.3V6K RV501 RV655
158_0402_1% @ 10K_0402_5%
2 1 TMDS_C_TX0P 4 3
<47> TMDS_TX0P EMI@
CV1059 0.1U_0201_6.3V6K 6.04 +-1% 0402 JHDMI

2
HCM1012GH900BP_4P RV28 HDMI_HPLUG 19
1 EMI@ 2 TMDS_L_TX0P 1 2 TMDS_R_TX0P 18 HP_DET
RV646 5.6_0402_1% 17 +5V
TMDS_CTRLDAT_R 16 DDC/CEC_GND
TMDS_CTRLCLK_R 15 SDA
1 EMI@ 2 TMDS_L_TX1N 1 2 TMDS_R_TX1N 14 SCL
RV642 5.6_0402_1% 13 Reserved
LV5 @EMI@ 6.04 +-1% 0402 TMDS_R_TXCN 12 CEC 20
CK- GND

2
2 1 TMDS_C_TX1N 1 2 RV29 11 21
<47> TMDS_TX1N TMDS_R_TXCP 10 CK_shield GND 22
CV1062 0.1U_0201_6.3V6K RV502
TMDS_R_TX0N 9 CK+ GND 23
158_0402_1% D0- GND
2 1 TMDS_C_TX1P 4 3 8
<47> TMDS_TX1P EMI@ TMDS_R_TX0P D0_shield
CV1061 0.1U_0201_6.3V6K 6.04 +-1% 0402 7

1
HCM1012GH900BP_4P RV30 TMDS_R_TX1N 6 D0+
1 EMI@ 2 TMDS_L_TX1P 1 2 TMDS_R_TX1P 5 D1-
RV639 5.6_0402_1% TMDS_R_TX1P 4 D1_shield
TMDS_R_TX2N 3 D1+
2 D2-
TMDS_R_TX2P 1 D2_shield
1 EMI@ 2 TMDS_L_TX2N 1 2 TMDS_R_TX2N D2+
RV645 5.6_0402_1% ACON_HMRA3-AK1L0C
LV6 @EMI@ 6.04 +-1% 0402 CONN@

2
2 1 TMDS_C_TX2N 1 2 RV33
C <47> TMDS_TX2N C
CV1064 0.1U_0201_6.3V6K RV503
158_0402_1%
2 1 TMDS_C_TX2P 4 3
<47> TMDS_TX2P EMI@
CV1063 0.1U_0201_6.3V6K 6.04 +-1% 0402

1
HCM1012GH900BP_4P RV34
1 EMI@ 2 TMDS_L_TX2P 1 2 TMDS_R_TX2P
RV638 5.6_0402_1%

TMDS_C_TX0N RX31 1 2 499_0201_1% LX1 1 2 PBY100505T-601Y-N_2P


TMDS_C_TX0P RX32 1 2 499_0201_1% LX2 1 2 PBY100505T-601Y-N_2P
TMDS_C_TXCN RX33 1 2 499_0201_1% LX3 1 2 PBY100505T-601Y-N_2P
TMDS_C_TXCP RX34 1 2 499_0201_1% LX4 1 2 PBY100505T-601Y-N_2P

TMDS_C_TX1N RX35 1 2 499_0201_1% LX5 1 2 PBY100505T-601Y-N_2P


TMDS_C_TX1P RX36 1 2 499_0201_1% LX6 1 2 PBY100505T-601Y-N_2P
TMDS_C_TX2N RX37 1 2 499_0201_1% LX7 1 2 PBY100505T-601Y-N_2P
TMDS_C_TX2P RX38 1 2 499_0201_1% LX8 1 2 PBY100505T-601Y-N_2P

+3V3_SYS HDMI_Down

1
D
2 QX1
G BSS138-G_SOT23-3

1
S

3
B RX1 B
100K_0402_5%

2
+HDMI_5V_OUT

DGPU_PEX_RST# +3VS
SDM10U45-7_SOD523-2

SDM10U45-7_SOD523-2

QX3
S TR METR3904W-G NPN SOT323-3
2

1
C
+1V8_AON HDMI_HPLUG
DV12

DV13

2 1 2
B
E RX6

3
+1V8_AON 150K_0402_5%
<20> HDMI_HPD_PCH 1
1

CX2

1
10K_0402_5%

10K_0402_5%

0.1U_0402_16V7K
1

2
RV652

RX7 RX8
2

2
RV648

2K_0402_5%

2K_0402_5%

10K_0402_5% 100K_0402_5%
+1.8VS
RV649

RV653

2
2

CV1056
<46> HDMI_HPD_GPU#
1

1 2
5

0.1U_0402_16V7K

5
HDMI_CTRLCLK 4 3 TMDS_SCLF 2 1 TMDS_CTRLCLK_R
<47> HDMI_CTRLCLK
QV97B

VCC
QV96B RV651 DMN53D0LDW-7 2N SOT363-6 1

To GPU IN B
2

DMN53D0LDW-7 2N SOT363-6 33_0402_1% 5 4


OUT Y 2 DGPU_PEX_RST#

GND
HDMI_CTRLDAT 1 6 TMDS_SDAF 2 1 TMDS_CTRLDAT_R IN A DGPU_PEX_RST# <26,46,55>
<47> HDMI_CTRLDAT

4
A A
RV650

3
QV96A 33_0402_1% UX2
DMN53D0LDW-7 2N SOT363-6 NL17SZ08DFT2G_SC70-5

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-D581P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 07, 2016 Sheet 27 of 80
5 4 3 2 1
5 4 3 2 1

D D

M.2 2230 slot(type E)

+3VS

JWLAN
1 2
3 GND 3.3VAUX 4
<19> USB20_P5 5 USB_D+ 3.3VAUX 6
<19> USB20_N5 7 USB_D- LED1# 8 +3VS
9 GND PCM_CLK 10
11 SIDO_CLK PCM_SYNC 12
SDIO_CMD PCM_IN

1
13 14
15 SDO_DAT0 PCM_OUT 16 RN16
17 SDO_DAT1 LED2# 18 10K_0402_5%
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_WAKE# 22
For EC to detect

2
23 SDIO_WAKE# UART_RX BT_OFF#_R 1 @ 2
SDIO_RESET# BT_OFF# <20>
RN17 0_0201_5%
C
debug card insert. 1
C

24 1 2 CN25
25 UART_TX 26 1U_0402_10V6K
CN23 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P6_C 27 GND UART_CTS 28 RM31
<19> PCIE_PTX_DRX_P6 2 1 PCIE_PTX_DRX_N6_C 29 PETP0 UART_RTS 30 2
CN24 0.1U_0402_16V7K 100K_0402_5%
<19> PCIE_PTX_DRX_N6 31 PETN0 RESERVED 32 EC_TX <43>
33 GND RESERVED 34 EC_RX <43>
<19> PCIE_PRX_DTX_P6 35 PERP0 RESERVED 36
<19> PCIE_PRX_DTX_N6 37 PERN0 COEX3 38
39 GND COEX2 40 +3VS
<17> CLK_PCIE_P5 41 REFCLKP0 COEX1 42
<17> CLK_PCIE_N5 REFCLKN0 SUSCLK SUSCLK <18,29>
43 44
GND PERST0# PCIRST# <6,17,29,30,43,56>

1
45 46 BT_OFF#_R
<17> CLKREQ_PCIE#5 47 CLKEQ0# W_DISABLE2# 48 WL_OFF#_R RN5
49 PEWAKE0# W_DISABLE1# 50 10K_0402_5%
51 GND I2C_DATA 52
53 RSRVD/PETP1 I2C_CLK 54

2
55 RSRVD/PETN1 ALERT 56 WL_OFF#_R 1 @ 2
57 GND RESERVED 58 WL_OFF# <20>
RN15 0_0201_5%
59 RSRVD/PERP1 RESERVED 60
61 RSRVD/PERN1 RESERVED 62
GND RESERVED 1
63 64 CN9
65 RESERVED 3.3VAUX 66 1U_0402_10V6K
67 RESERVED 3.3VAUX
GND 2

69 68
MTG77 MTG76

LCN_DAN05-67306-0102
CONN@

B B

closed to pin 2, 4 closed to pin 64, 66 WLAN power control


+3VS +3VS

+3VS
22U_0603_6.3V6M~D

0.1U_0402_10V7K~D

22U_0603_6.3V6M~D

0.1U_0402_10V7K~D

1 1 1 1
CM12

CM13

CM14

CM15

2 2 2 2
1 1
CM11 CM10
4.7U_0805_10V4Z 0.1U_0402_10V7K
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF WLAN/BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 28 of 80
5 4 3 2 1
5 4 3 2 1

SSD
NGFF Slot_1 Key M
+3VS_SSD
JSSD1
1 2
3 GND 3.3VAUX 4
PCIE_PRX_DTX_N12 5 GND 3.3VAUX 6
<16> PCIE_PRX_DTX_N12 PCIE_PRX_DTX_P12 7 PERn3 NC 8
<16> PCIE_PRX_DTX_P12 9 PERp3 NC 10
11 GND DAS/DSS# 12
D <16> PCIE_PTX_DRX_N12 PETn3 3.3VAUX D
13 14
<16> PCIE_PTX_DRX_P12 15 PETp3 3.3VAUX 16
PCIE_PRX_DTX_N11 17 GND 3.3VAUX 18
<16> PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 19 PERn2 3.3VAUX 20
<16> PCIE_PRX_DTX_P11 21 PERp2 NC 22
23 GND NC 24
<16> PCIE_PTX_DRX_N11 25 PETn2 NC 26
<16> PCIE_PTX_DRX_P11 27 PETp2 NC 28
PCIE_PRX_DTX_N10 29 GND NC 30
<16> PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 31 PERn1 NC 32
<16> PCIE_PRX_DTX_P10 33 PERp1 NC 34
35 GND NC 36
<16> PCIE_PTX_DRX_N10 37 PETn1 NC 38
<16> PCIE_PTX_DRX_P10 39 PETp1 DEVSLP 40 DEVSLP0 <19>
PCIE_PRX_DTX_P9 41 GND NC 42
<16> PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 43 PERn0/SATA-B+ NC 44 +3VS_SSD
<16> PCIE_PRX_DTX_N9 45 PERp0/SATA-B- NC 46
47 GND NC 48
<16> PCIE_PTX_DRX_N9 49 PETn0/SATA-A- NC 50 PCIRST#
<16> PCIE_PTX_DRX_P9 PETp0/SATA-A+ PERST# PCIRST# <6,17,28,30,43,56>

0.047U_0402_16V4Z

0.047U_0402_16V4Z
51 52

33P_0402_50V8J

33P_0402_50V8J

22U_0402_6.3V8J

22U_0402_6.3V8J

22U_0402_6.3V8J
53 GND CLKREQ# 54 CLKREQ_PCIE#1 <17>
<17> CLK_PCIE_N1 REFCLKN PEWAKE# 1 1 1 1 1 1 1
55 56
<17> CLK_PCIE_P1 REFCLKP NC

C623

C621

C618

C617

C622

C635

C636
57 58
GND NC
+3VS_SSD 2 2 2 2 2 2 2
67 68 SUSCLK
69 NC SUSCLK(32kHz) 70 SUSCLK <18,28>
PEDET(NC-PCIe/GND-SATA) 3.3VAUX

2
71 72
73 GND 3.3VAUX 74
R363 75 GND 3.3VAUX
10K_0402_5% GND 76
GND 77

1
GND
LCN_DAN05-67406-0103
<16> M2_SLOT1_PEDET
CONN@

C C

PEDET Module Type


0 SATA +3VALW

1 PCIE

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1
4.4m ohm/6A

C2515

C2514
+3VS_SSD
2 2 U16
1
2 VIN1

SSD 7
VIN2

VIN thermal VOUT


6

NGFF Slot_2 Key M

10U_0603_6.3V6M

10U_0603_6.3V6M
3
+5VALW VBIAS
1 1

C2513

C2512
4 5
<43,45,56,64,67,76> SUSP# ON GND
+3VS_SSD
2 2

0.1U_0402_10V7K
JSSD2 AOZ1334DI-02_WSON8
1 2 1
GND 3.3VAUX

C2516
3 4
PCIE_PRX_DTX_N13 5 GND 3.3VAUX 6
<16> PCIE_PRX_DTX_N13 PCIE_PRX_DTX_P13 7 PERn3 NC 8
<16> PCIE_PRX_DTX_P13 9 PERp3 NC 10 2
11 GND DAS/DSS# 12
<16> PCIE_PTX_DRX_N13 13 PETn3 3.3VAUX 14
<16> PCIE_PTX_DRX_P13 15 PETp3 3.3VAUX 16
PCIE_PRX_DTX_N14 17 GND 3.3VAUX 18
<16> PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 19 PERn2 3.3VAUX 20
B <16> PCIE_PRX_DTX_P14 PERp2 NC B
21 22
23 GND NC 24
<16> PCIE_PTX_DRX_N14 25 PETn2 NC 26
<16> PCIE_PTX_DRX_P14 27 PETp2 NC 28
PCIE_PRX_DTX_N15 29 GND NC 30
<16> PCIE_PRX_DTX_N15 PCIE_PRX_DTX_P15 31 PERn1 NC 32
<16> PCIE_PRX_DTX_P15 33 PERp1 NC 34
35 GND NC 36
<16> PCIE_PTX_DRX_N15 37 PETn1 NC 38
<16> PCIE_PTX_DRX_P15 39 PETp1 DEVSLP 40 DEVSLP3 <19>
PCIE_PRX_DTX_P16 41 GND NC 42
<16> PCIE_PRX_DTX_P16 PCIE_PRX_DTX_N16 43 PERn0/SATA-B+ NC 44 +3VS_SSD
<16> PCIE_PRX_DTX_N16 45 PERp0/SATA-B- NC 46
47 GND NC 48
<16> PCIE_PTX_DRX_N16 49 PETn0/SATA-A- NC 50 PCIRST#
<16> PCIE_PTX_DRX_P16 PETp0/SATA-A+ PERST#

0.047U_0402_16V4Z

0.047U_0402_16V4Z
51 52

33P_0402_50V8J

33P_0402_50V8J

22U_0402_6.3V8J

22U_0402_6.3V8J

22U_0402_6.3V8J
53 GND CLKREQ# 54 CLKREQ_PCIE#2 <17>
<17> CLK_PCIE_N2 REFCLKN PEWAKE# 1 1 1 1 1 1 1
55 56
<17> CLK_PCIE_P2 REFCLKP NC

C625

C627

C620

C628

C624

C637

C638
57 58
GND NC
+3VS_SSD 2 2 2 2 2 2 2
67 68 SUSCLK
69 NC SUSCLK(32kHz) 70
PEDET(NC-PCIe/GND-SATA) 3.3VAUX
2

71 72
73 GND 3.3VAUX 74
R365 75 GND 3.3VAUX
10K_0402_5% GND 76
GND 77
1

GND
LCN_DAN05-67406-0103
<16> M2_SLOT2_PEDET
CONN@

PEDET Module Type


A A

0 SATA
1 PCIE

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 29 of 80
5 4 3 2 1
5 4 3 2 1

UL1
PCIE_PRX_DTX_P5 2 1 PCIE_PRX_DTX_P5_C 30 1
<19> PCIE_PRX_DTX_P5 TX_P VDD33 +LAN_IO
CL1 0.1U_0402_16V7K 16
PCIE_PRX_DTX_N5 2 1 PCIE_PRX_DTX_N5_C 29 AVDD33
<19> PCIE_PRX_DTX_N5 TX_N
CL2 0.1U_0402_16V7K
PCIE_PTX_DRX_P5 2 1 PCIE_PTX_DRX_P5_C 35 13 +AVDDL
+LAN_IO <19> PCIE_PTX_DRX_P5 RX_P AVDDL
CL3 0.1U_0402_16V7K 19
PCIE_PTX_DRX_N5 2 1 PCIE_PTX_DRX_N5_C 36 AVDDL 31
<19> PCIE_PTX_DRX_N5 RX_N AVDDL 34
CL4 0.1U_0402_16V7K
33 AVDDL 6 +DVDDL
<17> CLK_PCIE_P4 REFCLK_P AVDDL_REG

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D
RL1 32
<17> CLK_PCIE_N4 REFCLK_N 22 +AVDDH
D 4.7K_0402_5%~D 1 1 D
4 AVDDH 9
<17> CLKREQ_PCIE#4 CLKREQ# AVDDH_REG CL43 CL44

2
2
<6,17,28,29,43,56> PCIRST# PERST# 37 +DVDDL 2 2
PCIE_WAKE# 3 DVDDL_REG
<18,43> PCIE_WAKE# WAKE#
11 LAN_MDIP0
25 TRXP0 12 LAN_MDIN0
26 SMCLK TRXN0 14 LAN_MDIP1

The pull-up resisters might not be 28


27
SMDATA

NC
TRXP1
TRXN1
TRXP2
15
17
18
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
close to UL1 pin37
necessory due to existence 41 TESTMODE
GND
TRXN2
TRXP3
TRXN3
20
21
LAN_MDIP3
LAN_MDIN3

on PCH side. XTLI


XTLO
8
7 XTLI
XTLO 40 +AVDDH

25MHZ_12PF_7V25000012
1 2 5 LX

1U_0402_6.3V6K~D
+LAN_IO

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
RL2 30K_0402_5% ISOLAT# 24
PPS

4
LAN_ACTIVITY# 1 1 1
38 10 +RBIAS 1 2

GND

GND
LAN_LINK#_R 39 LED_0 RBIAS CL5 CL6 CL7
LAN_LED2#_R 23 LED_1 RL3
LED_2

2
2.37K_0402_1%~D 2 2 2

OSC

OSC
RL4
YL1 5.1K_0402_1%~D S IC E2400-BL3A-R QFN 40P E-LAN CTRL

1
CL8
18P_0402_50V8J
2 2
CL9
22P_0402_50V8J
Killer E2500 SA0000A6L00 close to UL1 pin9 close to UL1 pin22
+3VALW 1 1
C C

1 1
CL40 CL41

4.7U_0805_10V4Z 0.1U_0402_16V7K
2 2
+LAN_IO 1A
UL2 +AVDDL
1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
4.7U_0603_6.3V6K~D
5 OUT

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
1000P_0402_50V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
IN 2 1 1 1 1 1 1 1 1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
4 GND

CL22
<43> EN_WOL# EN 3 1 2 CL18 CL19 CL20 CL21 CL23 CL24 CL25
OCB +3VS 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2 2
CL42 SY6288D20AAC_SOT23-5 RL5 CL11 CL12 CL13 CL14 CL15 CL16 CL17
10K_0402_5%
0.1U_0402_16V7K 2 2 2 2 2 2 2
2

close to UL1 pin1 close to UL1 pin16 close to UL1 pin6 close to UL1 pin34 close to UL1 pin31 close to UL1 pin13 close to UL1 pin19

TL1 JLAN
B LAN_MDIN3 1 24 RJ45_MDI3- @EMI@ B
TD1+ TX1+ 2 1 LAN_ACTIVITY# 10
LAN_MDIP3 2 23 RJ45_MDI3+ RL9 CL27 470P_0402_50V7K Yellow LED-
TD1- TX1- 75_0402_1%~D 2 1 9
+VDDCT_L RJ45_CT3 +LAN_IO Yellow LED+
3 22 1 2 RJ45_CT RL8 330_0402_5%
TDCT1 TXCT1 RJ45_MDI3- 8
4 21 RJ45_CT2 1 2 PR4-
TDCT2 TXCT2 RJ45_MDI3+ 7
LAN_MDIN2 5 20 RJ45_MDI2- RL10 PR4+
TD2+ TX2+ 75_0402_1%~D RJ45_MDI1- 6
LAN_MDIP2 6 19 RJ45_MDI2+ PR2-
TD2- TX2- RJ45_MDI2- 5
LAN_MDIN1 7 18 RJ45_MDI1- PR3-
TD3+ TX3+ RJ45_MDI2+ 4
LAN_MDIP1 8 17 RJ45_MDI1+ RL11 PR3+ 17
TD3- TX3- 75_0402_1%~D RJ45_MDI1+ 3 GND
9 16 RJ45_CT1 1 2 PR2+ 16
TDCT3 TXCT3 RJ45_MDI0- 2 GND
10 15 RJ45_CT0 1 2 PR1- 15
TDCT4 TXCT4 RJ45_MDI0+ 1 GND
LAN_MDIN0 11 14 RJ45_MDI0- RL12 PR1+ 14
TD4+ TX4+ 2 GND
75_0402_1%~D 2 1 LAN_LINK# 11
LAN_MDIP0 12 13 RJ45_MDI0+ CL30 @EMI@ CL28 470P_0402_50V7K Green LED-
TD4- TX4- 10P_1808_3KV7K~D 2 1 LAN_LED2# 13
1 @EMI@ CL29 470P_0402_50V7K Orange LED-
MHPC_NS692417 +LAN_IO
1 2 12
2N7002K_SOT23-3 LL1 Green-Orange LED+
QL3 BLM15AG121SN1D_L0402_2P
SDAN_601029-013231

D
3 1 2 1 CONN@
RL13 130_0402_1%~D

2
LAN_LED2#_R 2 1 1
1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D
0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

RL15 130_0402_5%~D @EMI@


G
CL32

CL33

CL34

CL35

CL36

CL37

CL38

CL39

2 1 2 1 2 1 2 1 RL14 CL31
LAN_LINK#_R 2 1K_0402_1%~D 470P_0402_50V7K
A 2 A

1
1 2 1 2 1 2 1 2
+LAN_IO

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN E2400
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 30 of 80
5 4 3 2 1
5 4 3 2 1

CA1,CA2 close +3.3V_1.8V_DVDD_IO


+1.8VS

PCH_AZ_CODEC_BITCLK
+3.3V_1.8V_DVDD_IO
to UA1 pin19 RA68
0_0603_5%
+5V_PVDD RA69
0_0603_5%
+5V_PVDD
LA3 @
+5V_PVDD +5VS

1 @ 2 1 @ 2 1 2 RA1 1 2 0_0603_5%

0.1U_0402_16V7K
1 1 1 @ 1 1 1 1 @ 1 1 @ 1 BLM15AG121SN1D_L0402_2P 1 @ 2

1
+3VS

CA2

10U_0603_6.3V6M
CA3

0.1U_0402_16V7K
CA4

10U_0603_6.3V6M
CA5

0.1U_0402_16V7K
CA6

10U_0603_6.3V6M
CA7

0.1U_0402_16V7K
CA8

10U_0603_6.3V6M
CA9

0.1U_0402_16V7K
CA10
EC Beep RA3 0_0603_5% RA4 1 2 0_0603_5%

4.7U_0402_6.3V6M
CA1
RA2
22_0402_5% DA1 RA5 1 2 0_0603_5% +5VA +5VS RA6 1 2 0_0603_5%
EMI@ 2 2 CA12,CA13 close 2 2 2 2 2 2 2 2
<43> BEEP# 2
RA7 1 2 0_0603_5%
2
to UA1 pin7
+3.3V_1.8V_DVDD
1 PC_BEEP 1 @ 2
1 RA8 0_0603_5%
CA11 3
<18> HDA_SPKR Moat

1
10P_0402_50V8J
EMI@ BAT54C-7-F_SOT23-3 @
2 RA9 +3.3V_1.8V_DVDD +1.8VS Moat GNDA GND
1 1 +5VA +CODEC_AVDD2

0.1U_0402_16V7K
CA12
10K_0402_5%

CA13
4.7U_0402_6.3V6M
+CODEC_AVDD2 +1.8VS
MCU Beep

2
D LA5 @ D
PCH_AZ_CODEC_SDOUT 2 2 Place on the moat between GND & GNDA.

10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

10U_0603_6.3V6M
1 1 1 2 LA4

CA14

CA15
1 1 BLM15AG121SN1D_L0402_2P 1 2
+3VS

CA16

CA17
BLM15AG121SN1D_L0402_2P
1

RA10 2 2 RA11 1 @ 2 0_0603_5%


33_0402_1% 2 2
@EMI@
2

1 1 2 LDO2-CAP
CA18
0_0402_5%
22P_0402_50V8J @ RA12 Moat

57

19

46

51

45

24
@EMI@

7
2 UA1
RA15 1K_0402_1%

DVDD-IO

PVDD1

PVDD2

AVDD1

CPVDD/AVDD2
T-PAD

DVDD
23 CA19 2 1 0.1U_0402_16V7K 2 1 PC_BEEP
I2C0_SDA_EC 11 PCBEEP
<32,43> I2C0_SDA_EC I2C DATA 25 CA20 1 2 2.2U_0402_6.3V6M
I2C0_SCL_EC 12 CBN2
<32,43> I2C0_SCL_EC I2C CLK 26 1 2
PCH_AZ_CODEC_BITCLK 13 CBP2
<18> PCH_AZ_CODEC_BITCLK AUDIOLINK: BCLK/IBCLK RA16
27 CA21 1 2 2.2U_0402_6.3V6M
CBP1 10K_0402_5% +3VALW
14
<18> PCH_AZ_CODEC_SYNC AUDIOLINK:SYNC/LRCK 28
2 1 PCH_AZ_CODEC_RST#_R 15 CBN1
<18> PCH_AZ_CODEC_RST# @ AUDIOLINK:RESETB/MCLK

1
RA17 0_0402_5% 39 LINE1_VREFO_R
1 2 16 Mic1-VrefO-R/AGPO-1
<18> PCH_AZ_CODEC_SDIN0 AUDIOLINK:SDATA-IN/DOUT MIC1-VREFO_L
RA18 22_0402_5% 38 RA13
PCH_AZ_CODEC_SDOUT 17 Mic1-VrefO-L/AGPP-0 10K_0402_5%
<18>
PCH_AZ_CODEC_SDOUT AUDIOLINK:SDATA-OUT/DIN 37 SLEEVE
LA6

2
MIC_CLK EMI@ 1 2 DMIC_CLK1_R 53 Mic1-R/Sleeve
<25> MIC_CLK DMIC-CLK1 36 RING2
MIC_DATA BLM15BB221SN1D_2P DMIC_DATA1_R Mic1-L/Ring2 GPIO_1
1 @ 2 54 2
<25> MIC_DATA DMIC-DATA1 LINE1_L
RA19 0_0402_5% 35
Line1-L HP_MUTE# 1
I2S_LRCK_R 1 34 LINE1_R
GPIO_1 2 GPIO_9/I2S_LRCK Line1-R 3 DEPOP#_EC
I2S_OUT_R GPIO_1/DMIC_CLK2/SPDIF_O/I2S_In JD DEPOP#_EC <43>
3 33 HPOUT-R
4 GPIO_6/I2S_Out HP_Out-R
+3.3V_1.8V_DVDD I2S_DATA_OUT_R 5 GPIO_2/DMIC DATA2/I2S_Out JD 32 HPOUT-L DA2
8 GPIO_5/I2S_In HP_Out-L BAT54AW_SOT323-3~D
AMP_I2S_MCLK_R 55 I2S_Out JD/Mic JD 40 LINE1_VREFO_L
1

AMP_I2S_BCLK_R 56 GPIO_8/I2S-MCLK/SPDIF_IN LINE1-VREFO


C +3.3V_1.8V_DVDD RA21 GPIO_7/I2S-BCLK C
1 @ 2 100K_0201_1% 41
RA70 EAPD# 52 MIC1-CAP
10K_0402_5% EAPD+PD#/GPIO_11 44
LDO1-CAP
1

2 EAPD# 47
2

SPK-OUT-LP
1K_0402_1%
RA22

1 48 21
<32> CODEC_Mute# SPK-OUT-LN VREF1
3 EC_MUTE# 49 22 LDO2-CAP
EC_MUTE# <43>
2

SPK-OUT-RN LDO2-cap
50 43
DA3 SPK-OUT-RP VREF
BAT54AW_SOT323-3~D HP_Line1_JD 9 29
HP JD/Line JD CPVPP
18 30
LDO3_cap CPVREF
1 1
+3.3V_1.8V_DVDD VD33STB 10 31
VD33STB CPVEE
10U_0402_6.3V6M
CA85

0.1U_0402_16V7K
CA23

AUDIO_IRQ @
6 42
AUDIO_IRQ 2 2 HD-SOC SEL AVSS1

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_16V7K

2.2U_0402_6.3V6M

0.1U_0402_16V7K

10U_0603_6.3V6M

0.1U_0402_16V7K

4.7U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
RA24 1 2
20 1 1 1 1 1 1 1 1 1 1
10K_0402_5% AVSS2

CA24

CA25

CA26

CA27

CA28

CA29

CA30

CA31

CA32

CA33
+RTC_CELL 2 2 2 2 2 2 2 2 2 2

2 @ 1 VD33STB
ALC3266-CG_QFN56_7X7
RA25
0_0402_5%

MIC1-VREFO_L RA26 1 2 2.2K_0201_5%

33_0402_5% RA28 1 2 2.2K_0201_5%


AMP_I2S_MCLK_R RA27 1 2 AMP_I2S_MCLK
AMP_I2S_MCLK <32> MIC_DATA MIC_CLK
33_0402_5%
AMP_I2S_BCLK_R RA29 1 2 AMP_I2S_BCLK +3.3V_1.8V_DVDD
AMP_I2S_BCLK <32>
33_0402_5% ESD@
I2S_LRCK_R RA30 1 2 I2S_LRCK
I2S_LRCK <32> 1
1
SLEEVE LA7 2 1 BLM15PX330SN1D 0402 W=40mils SLEEVE_R

1
33_0402_5% @EMI@ @EMI@ ESD@
I2S_OUT_R RA31 1 2 I2S_OUT
I2S_OUT <32>
CA35
2
CA34 RA32 RING2 RA35 LA8 2 1 BLM15PX330SN1D 0402 W=40mils RING2_R
B 33_0402_5% 22P_0402_50V8J 10P_0402_50V8J 100K_0402_1% 2_0402_1% EMI@ B
I2S_DATA_OUT_R RA33 1 2 I2S_DATA_OUT 2 HPOUT-L 1 2 Line-IN-L LA9 2 1 FBMA-L11-160808-800LMT_2P AUD_HP_OUT_L_CN
I2S_DATA_OUT <32>
EMI@
2

200K_0402_1% 1 2 RA34 HPOUT_JD HPOUT-R 1 2 Line-IN-R LA10 2 1 FBMA-L11-160808-800LMT_2P AUD_HP_OUT_R_CN


1 1 1 1 1 Close to UA1 Pin53
22P_0402_50V8J
CA36 @EMI@

22P_0402_50V8J
CA37 @EMI@

22P_0402_50V8J
CA38 @EMI@

22P_0402_50V8J
CA39 @EMI@
22P_0402_50V8J
CA40 @EMI@

HP_Line1_JD 100K_0402_1% 1 2 RA36 LINE1_JD 2_0402_1%


RA37 UA3
2 2 2 2 2 RA38 MAX9892ERT+T_UCSP6~D
0.1U_0402_10V7K

1 @ 0_0201_5%
1 @ 2 A1
CA41

INL

2
1 @ 2 A3
2 HP_MUTE# INR

AZ5125-02S.R7G_SOT23-3
DA4
ESD@

AZ5123-02S SOT23
DA5
ESD@
B1 +3VS
RA39 /MUTE
Near Codec 1 1 1 1 1 1

100P_0201_50V
CA42

100P_0201_50V
CA43

680P_0201_50V
CA45

680P_0201_50V
CA46

680P_0402_50V8J
CA91 @ESD@

680P_0402_50V8J
CA92 @ESD@
0_0201_5%
B2
2 1 B3 VDD
SET 2 2 2 2 2 2

0.1U_0402_10V7K
Moat

GND
1

CA259

EMI@

EMI@

ESD@

ESD@
CA44
0.01U_0201_16V7K

1
A2
2
LINE1_VREFO_R RA40 1 2 2.2K_0201_5%
LINE1_VREFO_L RA41 1 2 2.2K_0201_5%
Set t i ng t he Turn - Of f Tim
e:
EMI@
Ton (ms) = 0.02 x Cset (pF)
LINE1_R 1 2 HP2_D_R_C 1 2 HP2_D_R_R 2
LA11
1 HP2_D_R1_JK
Jack1 : Global Headset
+

1
CA47 RA42
BLM15PX330SN1D 0402
CA48
OMTP/CTIA headset, Headphone, Line-Out
330U_D2E_6.3VM_R25M 8.2_0402_5%~D 100P_0201_50V
EMI@ 2 Re-tasking port
LINE1_L 1 2 HP2_D_L_C 1 2 HP2_D_L_R 2
LA12
1 HP2_D_L1_JK Headphone, Line-Out, Mic-In, Line-In
+

1
JACK1
BLM15PX330SN1D 0402
1

RING2_R
22K_0201_5%
RA44

22K_0201_5%
RA45

CA49 RA43 CA50 JACK2 4


AUD_HP_OUT_L_CN
AZ5125-02S.R7G_SOT23-3
DA6
ESD@

330U_D2E_6.3VM_R25M 8.2_0402_5%~D 100P_0201_50V 4 1


2 HP2_D_L1_JK 1

5
2

LINE1_JD 5
UA2
A
RA46 MAX9892ERT+T_UCSP6~D
Moat HPOUT_JD 6
A

0_0201_5% 6 AUD_HP_OUT_R_CN 2
1

1 @ 2 A1 HP2_D_R1_JK 2 SLEEVE_R 3
INL @ +3VLP 3 7
1 @ 2 A3 RA85 7
HP_MUTE# B1 INR 0_0201_5% +3VALW YUQIU_PJ741-F07J1BE-C
RA47 /MUTE 1 2 YUQIU_PJ741-F07J1BE-C CONN@
0_0201_5% CONN@
Set t i ng t he Turn - Of f Tim 2 1 B3 VDD
B2 1 @ 2
SET
Ton (ms) = 0.02 x Cset (pF)
0.1U_0402_10V7K

RA84
GND

1
CA51 0_0201_5%
Compal Electronics, Inc.
CA258

0.01U_0201_16V7K Security Classification Compal Secret Data


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title
A2

2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio codec ALC3266
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 31 of 80
5 4 3 2 1
5 4 3 2 1

B+_BIAS +PVDD
+PVDD +PVDD +1.8VS +1.8VS

RA83 1 @ 2 0_0805_5%
1 1 1
1 1 1 1 1 1 1 1 1 CA61 CA62 CA63
CA54 CA57 CA58 CA59 CA60
10U_0603_25V 0.1U_0402_25V7K 1000P_0402_50V7K
CA52 CA53 1000P_0402_50V7K CA55 CA56 1000P_0402_50V7K 10U_0402_6.3V6M 0.1U_0402_16V7K 0.1U_0402_16V7K
10U_0603_25V6M 0.1U_0402_25V7K 10U_0603_25V6M 0.1U_0402_25V7K 2 2 2
+3.3V_1.8V_DVDD 2 2 2 2 2 2 2 2 2

CA52, CA53 and CA54 close to PIN1,56 CA55, CA56 and CA57 close to PIN42,43 CA60 close to PIN21 CA61, CA62 and CA63 close to PIN37
1 1 CA58, CA59 close to PIN17
10U_0402_6.3V6M

0.1U_0402_16V7K
CA64 CA65
2 2 +PVDD +PVDD
D D

1 1 1 1 1 1
CA81 CA84
CA79 CA80 1000P_0402_50V7K CA82 CA83 1000P_0402_50V7K
10U_0603_25V6M 0.1U_0402_25V7K 10U_0603_25V6M 0.1U_0402_25V7K
CA64, CA65 close to PIN16 2 2 2 2 2 2

CA52, CA53 and CA54 close to PIN 51 CA52, CA53 and CA54 close to PIN 48

OUT_A

OUT_B

OUT_C
+1.8VS
OUT_D +3.3V_1.8V_DVDD

CA71 1U_0402_16V6K

CA66 1U_0402_16V6K
330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K

1 1

1
1 1 1 1 +PVDD @
I2C0_SDA_EC_R
CA90

CA89

CA88

CA87

RA52 +3.3V_1.8V_DVDD RA53 2 1 1K_0402_5%


1K_0402_5% I2C0_SCL_EC_R RA50 2 1 1K_0402_5%
+PVDD 2 2
2 2 2 2 +1.8VS
+PVDD +PVDD +PVDD

2
1 @ 2
1

+3.3V_1.8V_DVDD
RA76

RA75

RA74

RA73

RA51
10_0402_5%

10_0402_5%

10_0402_5%

10_0402_5%

0_0402_5%
C 0x22h C

56

51

48

43

42

37

21

40

16

17
1

1
UA4
2

RA66 @

PVDD-A

PVDD-A

PVDD-B

AVDD1

AVDD2

PGVdd

GVDD-AB

DVDD-IO
PVDD-C

PVDD-D

PVDD-D

GVDD-CD

DVDD
10K_0402_5%
7 I2C0_SDA_EC_R 0_0402_5% 2 @ 1 RA55 I2C0_SDA_EC
OUT_A SDA I2C0_SDA_EC <31,43>
CA67 1 2 .033U_0603_50V7 2

2
BST-A 8 I2C0_SCL_EC_R 0_0402_5% 2 @ 1 RA56 I2C0_SCL_EC AMP_ASEL
OUT_B SCL I2C0_SCL_EC <31,43>
CA68 1 2 .033U_0603_50V7 50
BST-B

1
18 AMP_ASEL
OUT_C CA69 1 2 .033U_0603_50V7 49 ASEL EMI@ CA254 1 2 1000P_0402_50V7K RA67
BST-C 39 SYNC_IN 10K_0402_5%
OUT_D CA70 1 2 .033U_0603_50V7 41 SYNC-IN EMI@ CA255 1 2 1000P_0402_50V7K
RA58.1 should from RA57.1 directly BST-D SYNC_OUT
RA59.1 should from RA57.2 directly 38

2
SYNC-OUT TP@ TC24
RA61.1 should from JSPK.4 directly AMP_LDO_A1.5V 22 EMI@ LA50
0x20h
LDO A1.5 55 OUT_A 1 2 BLM15PX121SN1D_2P ISENSEP_L_R RA57 1 2 0.2_0805_1% SPK_L-_CONN
ISENSEP_L_R RA58 1 2 39K_0402_0.1% ISENSEP_L 25 OUT-A EMI@ LA51
LISENDE_P 52 OUT_B 1 2 BLM15PX121SN1D_2P SPK_L+_CONN
SPK_L-_CONN RA59 1 2 39K_0402_0.1% IVSENSE_L 26 OUT-B EMI@ LA52
LISENDE_N/LVSENSE_P 47 OUT_C 1 2 BLM15PX121SN1D_2P ISENSEP_R_R RA60 1 2 0.2_0805_1% SPK_R-_CONN
SPK_L+_CONN RA61 1 2 39K_0402_0.1% VSENSEN_L 27 OUT-C EMI@ LA53
LVSENSE_N 44 OUT_D 1 2 BLM15PX121SN1D_2P SPK_R+_CONN
OUT-D
1 RA62 2 5
22.1K_0402_1%
OC_ADJ 23 CA74 1 2 0.1U_0402_16V7K EMI@ CA256 1 2 1000P_0402_50V7K
ISENSEP_R_R RA63 1 2 39K_0402_0.1% ISENSEP_R 28 VREF
RISENSE_P EMI@ CA257 1 2 1000P_0402_50V7K
SPK_R-_CONN RA64 1 2 39K_0402_0.1% IVSENSE_R 29 9 AMP_I2S_MCLK
RISENSE_N/RVSENSE_P MCLK AMP_I2S_MCLK <31>
SPK_R+_CONN RA65 1 2 39K_0402_0.1% VSENSEN_R 30 10 AMP_I2S_BCLK
RVSENSE_N BCLK AMP_I2S_BCLK <31>
11 I2S_LRCK
LRCK I2S_LRCK <31>
2

RA63.1 should from RA60.1 directly I2S_OUT


RA79 10K_0402_0.1%

RA78 10K_0402_0.1%

RA77 10K_0402_0.1%

RA82 10K_0402_0.1%

RA81 10K_0402_0.1%

RA80 10K_0402_0.1%

RA64.1 should from RA60.2 directly 32 12


NC DACDAT I2S_OUT <31>
RA65.1 should from JSPK.2 directly 31 13
NC SPDIF_IN
B B
1

36 14 I2S_DATA_OUT
NC SPDIF OUT/I2S DATOUT I2S_DATA_OUT <31>
35 15 CODEC_Mute#
NC PDBJD CODEC_Mute# <31>

Thermal Pad
PGND-CD

PGND-CD

PGND-AB

PGND-AB
Int. Speaker Conn.
DGND
AGND

AGND

AGND

AGND
GND

40 mils = For 4 ohm 3W Speaker


4

34

33

24

20

19

46

45

54

53

57

ALC1309-CG_QFN56_7X7

Close to UA1 Pin42,43,44,45

JSPK
AMP_LDO_A1.5V SPK_R-_CONN 1 7
SPK_R+_CONN 2 1 G1
SPK_L-_CONN 3 2
1 1 SPK_L+_CONN 3
CA77 CA78 4
10U_0402_6.3V6M 0.1U_0402_16V7K 5 4
<43> SPEAKER_SEL 6 5 8
2 2 6 G2
ACES_50278-00601-001

3
Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R- CONN@

AZ5125-02S.R7G_SOT23-3
DA7
@ESD@

AZ5125-02S.R7G_SOT23-3
DA8
@ESD@
CA77, CA78 close to PIN22 Speaker 4 ohm : 40 mil
Speaker 8 ohm : 20 mil

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/09/08 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ALC1309
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 32 of 80
5 4 3 2 1
5 4 3 2 1

+5V_USB_PWR1

JUSB1
1
+3VLP +3VLP +3VLP +3VLP USB20_P1_CONN 3 VBUS
USB20_N1_CONN 2 D+
D-

SDMK0340L-7-F_SOD323-2
4
USB3_CRX_L_DTX_N1 5 GND
SSRX-

1
USB3_CRX_L_DTX_P1

220K_0402_5%
6 11

D
EMI@
LU4
HCM1012GD670A05P
RU4
100K_0402_5% RU5 DU8 1
CU26
USB charge for DC S5 USB3_CTX_C_L_DRX_N1
USB3_CTX_C_L_DRX_P1
7
8
9
SSRX+
GND
SSTX-
GND
GND
GND
12
13
14 D

USB3TP1 2 1 USB3_CTX_C_DRX_P1 4 3 USB3_CTX_C_L_DRX_P1 0.1U_0402_16V7K USBCHG_DET# 10 SSTX+ GND

2
<19> USB3TP1 Plug_DET
CU12 0.1U_0402_10V7K
2 SDAN_608015-010232
USB3TN1 2 1 USB3_CTX_C_DRX_N1 1 2 USB3_CTX_C_L_DRX_N1
CONN@
<19> USB3TN1

5
CU13 0.1U_0402_10V7K
CU27

3
1

P
2 1 2 NC 4
A Y USBCHG_DET_D <63>

G
EMI@ 2.2U_0603_6.3V6K DU1

1
LU5 UU5 L30ESDL5V0C3-2_SOT23-3

3
HCM1012GD670A05P TC7SZ14FU_SSOP5~D RU6 ESD@
USB3RP1 4 3 USB3_CRX_L_DTX_P1 1M_0402_5%
<19> USB3RP1

1
USB3RN1 1 2 USB3_CRX_L_DTX_N1
<19> USB3RN1
USBCHG_DET# 2 1
USBCHG_DET_EC# <43>
1 1
CU28 DU9 CU29
0.1U_0402_16V7K SDMK0340L-7-F_SOD323-2 0.1U_0402_16V7K
+5V_USB_PWR1
2 2
SW_USB20_P1 4 3 USB20_P1_CONN

150U_B15G_6.3VM_R70M

47U_0805_6.3V6M~D

10U_0603_6.3V6M~D
SW_USB20_N1 1 2 USB20_N1_CONN
1
1

1
MCM1012B900F06BP_4P

CU6

CU2

CU3
+
LU3
EMI@

2
2 2
+5VALW

+5V_USB_PWR1
1
CU7
0.1U_0402_10V7K
Power share
C C
2 UU1
1
IN OUT
12 W=80 mils 1
CU47
0.1U_0402_10V7K
13 9
<19> USB_OC0# FAULT# NC 2
2 11 SW_USB20_N1
<19> USB20_N1 3 DM_OUT DM_IN 10 SW_USB20_P1 DU2
<19> USB20_P1 DP_OUT DP_IN USB3_CRX_L_DTX_N1 1 9 USB3_CRX_L_DTX_N1
RU1 1 2 10K_0402_5 4 15 RU2 2 1 19.1K_0402_1%
+3VLP ILIM_SEL ILIM1 USB3_CRX_L_DTX_P1 USB3_CRX_L_DTX_P1
5 16 RU3 2 1 19.1K_0402_1% 2 8
<43> PWRSHARE_EN_EC# EN ILIM0
6 USB3_CTX_C_L_DRX_N1 4 7 USB3_CTX_C_L_DRX_N1
<43> CTL1 7 CTL1 14
<43>1 CTL2 2 8 CTL2 GND 17 USB3_CTX_C_L_DRX_P1 5 6 USB3_CTX_C_L_DRX_P1
+3VLP CTL3 GPAD
RU7 10K_0402_5
TPS2546RTER_QFN16_3X3

TVWDF1004AD0_DFN9
ESD@

+5V_USB_PWR2
+5V_USB_PWR2

+5VALW W=80 mils

150U_B15G_6.3VM_R70M

47U_0805_6.3V6M~D

10U_0603_6.3V6M~D
1
CU45 1
10U_0402_6.3V6M

0.1U_0402_10V7K
0.1U_0402_10V7K 1

1
CU43

CU10

CU11
+
1 1 2
CU48

CU46

B B
UU3

2
5 1 2 2
EMI@ 2 2 IN OUT
LU1 2
USB3TP4 2 1 USB3_CTX_C_DRX_P4 4 3 USB3_CTX_C_L_DRX_P4 GND
<19> USB3TP4 4 3
CU4 0.1U_0402_10V7K
<43> USB_PWR_EN EN OC USB_OC1# <19>
USB3TN4 2 1 USB3_CTX_C_DRX_N4 1 2 USB3_CTX_C_L_DRX_N4
1 SY6288C20AAC_SOT23-5 1
<19> USB3TN4
CU5 0.1U_0402_10V7K CU17
HCM1012GD670A05P CU16 0.1U_0402_16V7K
0.1U_0402_16V7K
2 2

+5V_USB_PWR2

EMI@
LU2
USB3RP4 4 3 USB3_CRX_L_DTX_P4 JUSB2
<19> USB3RP4 USB3_CTX_C_L_DRX_P4 9
1 SSTX+
USB3RN4 1 2 USB3_CRX_L_DTX_N4 USB3_CTX_C_L_DRX_N4 8 VBUS
<19> USB3RN4 USB20_P2_CONN 3 SSTX-
HCM1012GD670A05P 7 D+
DU5 USB20_N2_CONN 2 GND 10
USB3_CRX_L_DTX_N4 1 9 USB3_CRX_L_DTX_N4 USB3_CRX_L_DTX_P4 6 D- GND 11
4 SSRX+ GND 12
USB3_CRX_L_DTX_P4 2 8 USB3_CRX_L_DTX_P4 USB3_CRX_L_DTX_N4 5 GND GND 13
EMI@ SSRX- GND
LU6 USB3_CTX_C_L_DRX_N4 4 7 USB3_CTX_C_L_DRX_N4 TAITW_PUBAUE-09FLBS1FF4H0
USB20_P2 1 2 USB20_P2_CONN
<19> USB20_P2 USB3_CTX_C_L_DRX_P4 USB3_CTX_C_L_DRX_P4 CONN@
5 6
USB20_N2 4 3 USB20_N2_CONN
<19> USB20_N2

2
MCM1012B900F06BP_4P 3

TVWDF1004AD0_DFN9 DU4
ESD@ L30ESDL5V0C3-2_SOT23-3
A ESD@ A

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0/2.0 (Type A) x2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 35 of 80
5 4 3 2 1
5 4 3 2 1

D D

LU7 LU10
2 1 USB3_CTX_C_DRX_P2 4 3 USB3_CTX_C_L_DRX_P2
USB3TP5 2 1 USB3_CTX_C_DRX_P5 1 2 USB3_CTX_C_L_DRX_P5
<19> USB3TP2 <19> USB3TP5
CU31 0.1U_0402_10V7K CU39 0.1U_0402_10V7K

2 1 USB3_CTX_C_DRX_N2 1 2 USB3_CTX_C_L_DRX_N2
USB3TN5 2 1 USB3_CTX_C_DRX_N5 4 3 USB3_CTX_C_L_DRX_N5
<19> USB3TN2 <19> USB3TN5 +5V_USBC_VBUS +5V_USBC_VBUS +5V_USBC_VBUS
CU30 0.1U_0402_10V7K CU38 0.1U_0402_10V7K
HCM1012GD670A05P HCM1012GD670A05P
EMI@ EMI@

150U_B15G_6.3VM_R70M

10U_0805_25V6K

2.2U_0603_25V6K
1
1 1 JUSBC2

CU40

CU37

CU32
+ A1 B12
GND GND
USB3_CTX_C_L_DRX_P2 A2 B11 USB3_CRX_L_DTX_P2
2 2 2 USB3_CTX_C_L_DRX_N2 A3 SSTXP1 SSRXP1 B10 USB3_CRX_L_DTX_N2
LU8 LU11
4 3 USB3_CRX_L_DTX_P2 1 2 USB3_CRX_L_DTX_P5 SSTXN1 SSRXN1
USB3RP2 USB3RP5
<19> USB3RP2 <19> USB3RP5
0.47U_0402_25V6K 2 1 CU18 A4 B9 CU20 1 2 0.47U_0402_25V6K
VBUS VBUS
1 2 USB3_CRX_L_DTX_N2 4 3 USB3_CRX_L_DTX_N5 USB3_CC1 A5 B8 USB3_RUF2
USB3RN2 USB3RN5
<19> USB3RN2 <19> USB3RN5 CC1 RFU2
HCM1012GD670A05P USB20_P8_CONN A6 B7 USB20_N8_CONN
HCM1012GD670A05P
USB20_N8_CONN A7 DP1 DN2 B6 USB20_P8_CONN
EMI@ EMI@
DN1 DP2

Bottom
USB3_RUF1 A8 B5 USB3_CC2
RFU1 CC2

TOP
Close to Pin A4,A9,B4,B9 0.47U_0402_25V6K 2 1 CU19 A9
VBUS VBUS
B4 CU21 1 2 0.47U_0402_25V6K
LU9
1 2 USB20_P8_CONN USB3_CRX_L_DTX_N5 A10 B3 USB3_CTX_C_L_DRX_N5
<19> USB20_P8 USB3_CRX_L_DTX_P5 A11 SSRXN2 SSTXN2 B2 USB3_CTX_C_L_DRX_P5
SSRXP2 SSTXP2
C 4 3 USB20_N8_CONN A12 B1 C
<19> USB20_N8 GND GND
MCM1012B900F06BP_4P +3VALW
EMI@ 1 4
GND GND 6
GND

1
2 3
USB20_P8_CONN RU26 5 GND GND
10K_0201_1% GND
USB20_N8_CONN JAE_DX07S024JJ2R1300
CONN@

2
+5V_USBC_VBUS
2

<43> TYPEC_DET#

1
RU24
ESD@
10K_0201_1%
DU11
L30ESDL5V0C3-2_SOT23-3

1
D

2
QU1 2
2N7002W-T/R7_SOT323-3 G

1
S
1

3
RU25
20K_0201_1% DU12
USB3_CTX_C_L_DRX_N2 1 1 USB3_CTX_C_L_DRX_N2
10 9

2
USB3_CTX_C_L_DRX_P2 2 2 8 USB3_CTX_C_L_DRX_P2
9

USB3_CRX_L_DTX_N2 4 4 7 USB3_CRX_L_DTX_N2
7

USB3_CRX_L_DTX_P2 5 5 6 USB3_CRX_L_DTX_P2
6

3 3

L05ESDL5V0NA-4_SLP2510P8-10-9
ESD@

+5VALW

Close to Pin2,3,4 USB3_CRX_L_DTX_N5


DU13
USB3_CRX_L_DTX_N5
1 1 10 9
USB3_CRX_L_DTX_P5 USB3_CRX_L_DTX_P5
47U_0603_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M

0.1U_0402_16V7K

2 2 9 8
1 1 1 1 USB3_CTX_C_L_DRX_N5 USB3_CTX_C_L_DRX_N5
CU44

CU42

CU33

CU34

B 4 4 7 7 B

USB3_CTX_C_L_DRX_P5 5 5 6 USB3_CTX_C_L_DRX_P5
6
2 2 2 2
+5V_USBC_VBUS 3 3
UU7
+3VALW 8
2 14
3 IN1 OUT 15 L05ESDL5V0NA-4_SLP2510P8-10-9
4 IN1 OUT ESD@
IN2
5
AUX 1 RU15 1 2 100K_0402_5%
FAULTb 20 RU16 1 2 100K_0402_5%
6 LD_DETb
<43> USBC_PWR_EN EN
0.1U_0402_16V7K

1 2 7 11 USB3_CC1
1 RU21 10K_0402_5%
CHG CC1 USB3_CC2
CU35

RU23 1 2 100K_0402_1% 8 13
CHG_HI CC2

2 16 RU17 1 2 100K_0402_5%
RU14 1 2 100K_0402_1% 10 DEBUGb 17 RU18 1 2 100K_0402_5%
REF AUDIOb 18 RU19 1 2 100K_0402_5%
POLb 19 RU20 1 2 100K_0402_5% DU20
9 UFPb USB3_CC1 2
12 GND1 21 2 1
GND2 powerpad USB3_CC2 3 1
3
AZC199-02SPR7G_SOT23-3
TPS25810RVCR_QFN20_4X3 @ESD@

DU21
USB3_RUF1 2
2 1
USB3_RUF2 3 1
3
AZC199-02SPR7G_SOT23-3
@ESD@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2016/01/06 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0/2.0 (TypeC)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 36 of 80
5 4 3 2 1
5 4 3 2 1

+3.3V_F383

0.1U_0402_16V4Z~D

22P_0402_50V8J~D
10P_0402_50V8J

1U_0402_6.3V
1 1 2

CE59
@RF@

CE1

CE3

CE4
D D

2
2 2 1
+3.3V_F383

1
UE1 RE1 RE2
6 2 SPI_MOCLK
VDD P0.0 SPI_MOSO 4.7K_0402_5% 4.7K_0402_5%
1 +3.3V_F383
4 P0.1 32 SPI_MOSI

2
+5VALW <19> USB20_P4 5 D+ P0.2 31 SPI_MOCS#
<19> USB20_N4 D- P0.3 30
P0.4 I2C_DAT <38,39,41>

1
7 29
+3.3V_F383 REGIN P0.5 I2C_CLK <38,39,41>
8 28 RE8
0.1U_0402_16V4Z~D VBUS P0.6 27 CALDERA_PRSNT# <41,43> I2C_CLK
ELC_8051_C2CK_RST# P0.7 CDR_ON_ELC <41> 10K_0402_5%
10P_0402_50V8J

1U_0402_6.3V

1 2 9
+3.3V_F383 ELC_8051_C2D_P3 RST#/C2CK SLP_S3 SPI_MOCLK
@RF@

1 1 10 26

2
P3.0/C2D P1.0
1

BATT_CHG_LED
CE60

CE6

CE7
@
25

10P_0402_50V8J
RE7
18 P1.1 24 VCIN1_AC_IN#

10P_0402_50V8J
1K_0402_1%~D
<43> PCIE_GEN3#_GEN2 P2.0 P1.2

1
LID_SW

@RF@

@RF@
17 23 2 1
2

2 2 <43> AMD#_NV P2.1 P1.3 BATT_LOW_LED LID_SW# <43>

CE57

CE58
16 22
15 P2.2 P1.4 21 SLP_S5

2
14 P2.3 P1.5 20 CE8 @ 1 2 0.1U_0402_16V4Z~D DE1
13 P2.4 P1.6 19 CE9 @ 1 2 0.1U_0402_16V4Z~D SDMK0340L-7-F_SOD323-2~D
12 P2.5 P1.7
11 P2.6 3
P2.7 GND
+3.3V_F383 C8051F383-GQ_LQFP32_7X7

@
CE13

CE14

CE15

CE16

CE17

CE18
JELC
1
1 2
2 1 1 1 1 1 1
3

C
3
4
5
4
5
6 2 2 2 2 2 2
GigaDevice ,GD25Q80CSIGR ,SA000095R10 C
6
MXIC, MX25L8006EM2I-12G , SA000041O00

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
7
GND1 8
GND2
AMPHE_G846A06201EU
CONN@
UE2
SPI_MOSI 15_0402_5% 2 1 RE9 5 2 RE10 1 2 15_0402_5% SPI_MOSO
+3.3V_F383 DI SO
SPI_MOCLK 15_0402_5% 2 1 RE11 6
CLK
1 2 SPI_MOCS# 1
RE12 10K_0402_5%~D CS
1 2 7
RE13 10K_0402_5%~D HOLD
1 2 3
RE14 10K_0402_5%~D WP
+3.3V_F383 8 4
+3.3V_F383 VCC VSS

0.1U_0402_16V4Z~D

22P_0402_50V8J~D
1 GD25Q80CSIGR SOP 8P
1

CE19

CE20
1 SA000095R10
RE15
100K_0402_5%
2
2
2

SLP_S3 +3.3V_F383
3

5
D
G
QE1A
<18,43,45> PM_SLP_S3# S
DMN66D0LDW-7_SOT363-6 RE16
100K_0402_5%
4

SLP_S5
3

5
D
G
QE4A
<18,43> PM_SLP_S5# S
DMN66D0LDW-7_SOT363-6
+3.3V_F383
4

B +3VALW +3.3V_F383 B
1

RE17
100K_0402_5% UE9
5 1
IN OUT
2

VCIN1_AC_IN# 2
1 GND 1 1
+3.3V_F383 CE64 CE65
3

CE22 4 3 1 2 0.1U_0402_16V7K 10U_0402_6.3V6M


EN OC +3VS
5
D
G QE3A 4.7U_0603_10V
<18,43,61,62> VCIN1_AC_IN
1

2 SY6288C20AAC_SOT23-5 RE20 2 2
S
DMN66D0LDW-7_SOT363-6
RE21 10K_0402_5%
4

100K_0402_5%
2

BATT_LOW_LED

<43> 3V_F383_ON
6

2
D
G
QE3B
<43> BATT_LOW_LED#
+3.3V_F383 S
DMN66D0LDW-7_SOT363-6
1
1

RE23
100K_0402_5%
+3.3V_F383 behavior
2

BATT_CHG_LED
S0 S3 S4 S5
6

2 G
D
QE1B
AC IN (bat t ery l o w) ON ON ON ON
<43> BATT_CHG_LED# S
DMN66D0LDW-7_SOT363-6 AC IN (bat t ery f ull) ON ON ON OFF
1

BATT only ON ON OFF OFF

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ELC (1) C8051F383
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 37 of 80
5 4 3 2 1
5 4 3 2 1

+5VALW

1
ELC_EC#
<43> ELC_EC#
RE158

5
10K_0402_5%
+5VALW +5VALW @

2
PWR_R_7313# 4 3 PWR_R# UE7
AD3 0 QE22B
5
IN
OUT
1

1
2
AD2 0 DMN66D0LDW-7_SOT363-6~D
RE157
RE28
100K_0402_5%
4
EN
GND

OCB
3 1 @ 2
+3VS
AD1 1 1K_0402_1%

3
D S D
+3.3V_F383 SY6288D20AAC_SOT23-5 RE651

2
+3.3V_F383 +3.3V_F383 Power_LED G
2 10K_0402_5%
AD0 1 QE8

6
LP2301ALT1G 1P SOT-23-3

6
RE25 1
2
D D
4.7K_0402_1% CE24 QE22A G QE4B

1
2 <43> PWR_LED#
UE3 0.1U_0402_16V4Z DMN66D0LDW-7_SOT363-6~D S
DMN66D0LDW-7_SOT363-6
<43> PWR_R_EC
1

1
RE40 RE43 24 27 2

1
4.7K_0402_1%~D 4.7K_0402_1%~D RESET Vcc
3 ALIEN_LED_R_DRV# JPWR
25 OUT0 4 ALIEN_LED_G_DRV# +5VALW_LED 1 2 +5VALW_LED
2

<37,39,41> I2C_CLK 26 SCL OUT1 5 ALIEN_LED_B_DRV# 3 1 2 4


ON/OFF# ON/OFF#
<37,39,41> I2C_DAT SDA OUT2 6 LOGO_LED_R_DRV# <43> ON/OFF# PWR_G# 5 3 4 6 PWR_G#
AD0_2 31 OUT3 8 LOGO_LED_G_DRV# PWR_B# 7 5 6 8 PWR_B#
AD1_2 32 A0 OUT4 9 LOGO_LED_B_DRV# +5VALW PWR_R# 9 7 8 10 PWR_R#
AD2_2 1 A1 OUT5 10 TP_LED_R# 11 9 10 12
AD3_2 2 A2 OUT6 11 TP_LED_G# 11 12
A3 OUT7

1
14 TP_LED_B# ELC_EC# ACES_85203-0602N-10
OUT8
1

12 15 PWR_R_7313#
N.C. OUT9 PWR_G_7313# CONN@
13 16 RE156
N.C. OUT10

5
RE42 RE44 28 17 PWR_B_7313# 10K_0402_5%
4.7K_0402_1%~D 4.7K_0402_1%~D 29 N.C. OUT11 19

2
30 N.C. OUT12 20 PWR_G_7313# 4 3 PWR_G#
2

N.C. OUT13 21
OUT14
1

22
OUT15 QE21B
To power board

1
RE31
10K_0402_5%~D 7 23 DMN66D0LDW-7_SOT363-6~D
18 GND GND 33 RE155
GND GND 1K_0402_1%
2

2
TLC59116FIRHBR_VQFN32_5X5

6
QE21A
2 DMN66D0LDW-7_SOT363-6~D
<43> PWR_G_EC
+5VALW

1
C C

0.1U_0402_16V4Z
1
To logo board

CE61
+5VALW

1
ELC_EC# 2
JLOGO
RE154 1
1

5
10K_0402_5% 2
ALIEN_LED_R_DRV# 3 2

2
PWR_B_7313# 4 3 PWR_B# ALIEN_LED_G_DRV# 4 3
ALIEN_LED_B_DRV# 5 4
LOGO_LED_R_DRV# 6 5
QE13B 6

1
LOGO_LED_G_DRV# 7
DMN66D0LDW-7_SOT363-6~D LOGO_LED_B_DRV# 8 7
RE153 9 8 11
1K_0402_1% 10 9 G11 12
10 G12

2
ACES_50228-01071-P01
CONN@

6
QE13A
2 DMN66D0LDW-7_SOT363-6~D
<43> PWR_B_EC

1
+5VS_TP_LED

+5VS_TP_LED
1

R144 TP_LED_B#_DRV#
1

B B
2.2K_0402_5%
R146
To touchpad module
6
2.2K_0402_5%
2

TP_LED_B#_DRV 2 G
D

S Q28B
2

DMN66D0LDW-7_SOT363-6

1
3

+5VS_TP_LED
TP_LED_B# 5 G
D

Q28A JTP
Touchpad LED circuit
S

DMN66D0LDW-7_SOT363-6 1
4

2 1
TP_LED_B#_DRV# 3 2
TP_LED_G#_DRV# 4 3
Q2409 +5VS_TP_LED TP_LED_R#_DRV# 5 4
SI3456DDV-T1-GE3_TSOP6~D 6 5
B+_BIAS +5VS +5VS_TP_LED +5VS_TP_LED 7 6
7
1

+3VS +3VS_TOUCH 8
8
D

6 R150 TP_LED_G#_DRV# 9
S

9
300K_0402_5%~D

5 4 2.2K_0402_5% 10
10
2

1
0.1U_0402_16V4Z

2 1 @ 2 11
11
6

TP_CLK
R179

1U_0402_6.3V

1 1 R154 12
2

TP_LED_G#_DRV <43> TP_CLK TP_DATA 12


C29

2
D
R2 13

0.1U_0402_10V6K
1 2.2K_0402_5% 1
G

G
<43> TP_DATA 13
C2508

S Q29B 0_0603_5% 14
3

PCH_SMBCLK 14

C2
DMN66D0LDW-7_SOT363-6 15 17
1

<14,15,18> PCH_SMBCLK 15 G17


3

2 PCH_SMBDATA 16 18
2 TP_LED_G# 5 G
D
2 <14,15,18> PCH_SMBDATA 16 G18
EN_TPLED S Q29A ACES_51522-01601-P01
DMN66D0LDW-7_SOT363-6 CONN@
4
L2N7002WT1G 1N SC-70-3

1.5M_0402_5%~D

0.1U_0402_25V6K~D

1
1

D
R180

C2509

2 @
<43> TP_LED_EN +5VS_TP_LED
G
Q2410 S 2
3

+5VS_TP_LED
R145 TP_LED_R#_DRV#
2.2K_0402_5%
1

R147
2

A
TP_LED_R#_DRV 2
D
A
2.2K_0402_5%
G

S Q34B
DMN66D0LDW-7_SOT363-6
2

1
3

TP_LED_R# 5 G
D

S Q34A
DMN66D0LDW-7_SOT363-6
4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ELC (2)/TP/PWR/LOGO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 38 of 80
5 4 3 2 1
5 4 3 2 1

KB Backlight
D AD3 0 D

+3.3V_F383
AD2 0
+3.3V_F383

1 RE32
AD1 1 +3.3V_F383

4.7K_0402_1%
AD0 0
UE4
1
CE25
0.1U_0402_16V4Z
1

RE26 24 27 2
4.7K_0402_1%~D RESET Vcc
3 KB_LED_R1_DRV#
25 OUT0 4 KB_LED_G1_DRV#
<37,38,41> I2C_CLK
2

26 SCL OUT1 5 KB_LED_B1_DRV#


<37,38,41> I2C_DAT SDA OUT2 6 KB_LED_R2_DRV#
AD0_1 31 OUT3 8 KB_LED_G2_DRV#
AD1_1 32 A0 OUT4 9 KB_LED_B2_DRV#
AD2_1 1 A1 OUT5 10 KB_LED_R3_DRV#
AD3_1 2 A2 OUT6 11 KB_LED_G3_DRV#
A3 OUT7 14 KB_LED_B3_DRV#
OUT8
1

12 15 KB_LED_R4_DRV#
13 N.C. OUT9 16 KB_LED_G4_DRV#
4.7K_0402_1% RE30

4.7K_0402_1% RE27

RE29 28 N.C. OUT10 17 KB_LED_B4_DRV#


4.7K_0402_1%~D 29 N.C. OUT11 19
30 N.C. OUT12 20
2

N.C. OUT13 21
OUT14
1

RE37 22
OUT15
10K_0402_5%
7 23
18 GND GND 33
C GND GND C
2

TLC59116FIRHBR_VQFN32_5X5

KB BL LED
JKBBL
1
2 1
KB_LED_R1_DRV# 3 2
KB_LED_G1_DRV# 4 3
KB_LED_B1_DRV# 5 4
KB_LED_R2_DRV# 6 5
KB_LED_G2_DRV# 7 6
KB_LED_B2_DRV# 8 7
KB_LED_R3_DRV# 9 8
B KB_LED_G3_DRV# 10 9 B
KB_LED_B3_DRV# 11 10
KB_LED_R4_DRV# 12 11
KB_LED_G4_DRV# 13 12
KB_LED_B4_DRV# 14 13
15 14
+5VS 15
16
17 16
18 17
19 18
20 19
20

21
22 GND
GND
ACES_51522-02001-P02
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KBBL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 39 of 80
5 4 3 2 1
A B C D E

+5VALW +5VALW

+3VALW +3VALW +3VALW +3VALW

1
1

1
RE449 RE533

4
1 10K_0201_1% 10K_0201_1% 1

E1

E2
RE469 RE470 RE475 RE477

2
1M_0201_1% 1M_0201_1% 1M_0201_1% 1M_0201_1% 2B1 QE54A 5 QE54B
BC857BS_SOT363-6 B2 BC857BS_SOT363-6

C1

C2
6

3
KSI0 <43> KSI1 <43> KSI10 <43> KSI11 <43>

1
3

6
RE543 JKSO0 RE544 JKSO1
JKSI0 1 2 5 QE42B JKSI1 1 2 2 QE42A JKSI10 1 2 5 QE43B JKSI11 1 2 2 QE43A 10K_0201_1% 10K_0201_1%
MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6

2
1

1
RE471 RE474 RE476 RE480
4

1
10K_0201_1% RE473 10K_0201_1% RE472 10K_0201_1% RE478 10K_0201_1% RE479

6
1M_0201_1% 1M_0201_1% 1M_0201_1% 1M_0201_1%
2 2
D D
G QE49B G QE50B
S DMN66D0LDW-7_SOT363-6 S DMN66D0LDW-7_SOT363-6
2

1
3

3
1 2 5 1 2 5
D D
G G
<43> KSO0 S
<43> KSO1 S

RE513 QE49A RE531 QE50A

4
1

1
1K_0201_1% DMN66D0LDW-7_SOT363-6 1K_0201_1% DMN66D0LDW-7_SOT363-6
RE512 RE532
1M_0201_1% 1M_0201_1%

+3VALW +3VALW +3VALW +3VALW

2
1

1
RE464 RE463 RE481 RE483
1M_0201_1% 1M_0201_1% 1M_0201_1% 1M_0201_1%
2

2
KSI2 <43> KSI3 <43> KSI12 <43> KSI13 <43>
3

6
JKSI2 1 2 5 QE41B JKSI3 1 2 2 QE41A JKSI12 1 2 5 QE44B JKSI13 1 2 2 QE44A
MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6
1

1
RE466 RE467 RE482 RE486 +5VALW +5VALW
4

1
10K_0201_1% RE468 10K_0201_1% RE465 10K_0201_1% RE484 10K_0201_1% RE485
1M_0201_1% 1M_0201_1% 1M_0201_1% 1M_0201_1%
2

1
2 RE539 RE538 2

4
10K_0201_1% 10K_0201_1%

E1

E2
2

2
2B1 QE55A 5 QE55B
+3VALW +3VALW +3VALW +3VALW BC857BS_SOT363-6 B2 BC857BS_SOT363-6

C1

C2
6

3
1

1
RE459 RE457 RE487 RE489
1M_0201_1% 1M_0201_1% 1M_0201_1% 1M_0201_1% RE545 JKSO2 RE546 JKSO3
10K_0201_1% 10K_0201_1%
2

2
KSI4 <43> KSI5 <43> KSI14 <43> KSI15 <43>

6
2 2
D D
G QE51B G QE52B
3

6
S DMN66D0LDW-7_SOT363-6 S DMN66D0LDW-7_SOT363-6
JKSI4 1 2 5 QE40B JKSI5 1 2 2 QE40A JKSI14 1 2 5 QE45B JKSI15 1 2 2 QE45A

1
3

3
MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6
1

1
1 2 5 1 2 5
D D
RE461 RE460 RE488 RE492 G G
4

1
<43> KSO2 <43> KSO3
10K_0201_1% RE462 10K_0201_1% RE458 10K_0201_1% RE490 10K_0201_1% RE491 S S

1M_0201_1% 1M_0201_1% 1M_0201_1% 1M_0201_1% RE534 QE51A RE536 QE52A

4
1

1
1K_0201_1% DMN66D0LDW-7_SOT363-6 1K_0201_1% DMN66D0LDW-7_SOT363-6
RE535 RE537
2

2
1M_0201_1% 1M_0201_1%

2
+3VALW +3VALW +3VALW +3VALW
1

1
RE452 RE451 RE493 RE494
1M_0201_1% 1M_0201_1% 1M_0201_1% 1M_0201_1%
2

2
KSI6 <43> KSI7 <43> KSI16 <43> KSI17 <43>
+5VALW
3

6
JKSI6 1 2 5 QE39B JKSI7 1 2 2 QE39A JKSI16 1 2 5 QE46B JKSI17 1 2 2 QE46A
MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6
1

1
RE455 RE454 RE495 RE498
4

1
10K_0201_1% RE456 10K_0201_1% RE453 10K_0201_1% RE497 10K_0201_1% RE496
3 1M_0201_1% 1M_0201_1% 1M_0201_1% 1M_0201_1% 3
RE542

4
10K_0201_1%
2

E1

E2
2
2B1 QE56A 5 QE56B
BC857BS_SOT363-6 B2 BC857BS_SOT363-6

C1

C2
6

3
1
+3VALW +3VALW +3VALW +3VALW
RE547 JKSO4
10K_0201_1%
1

2
RE398 RE400 RE500 RE499

6
1M_0201_1% 1M_0201_1% 1M_0201_1% 1M_0201_1%
2
D
G QE53B
2

2
S DMN66D0LDW-7_SOT363-6
+5VALW

1
KSI8 <43> KSI9 <43> KSI18 <43> KSI19 <43>

3
1 2 5
D
G
<43> KSO4 S
3

6
RE540 QE53A JKB

4
1
JKSI8 1 2 5 QE29B JKSI9 1 2 2 QE29A JKSI18 1 2 5 QE47B JKSI19 1 2 2 QE47A 1K_0201_1% DMN66D0LDW-7_SOT363-6 1
MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6 RE541 2 1
1

1
RE396 RE399 RE502 RE503 1M_0201_1% CAPS 3 2
4

1
10K_0201_1% RE397 10K_0201_1% RE401 10K_0201_1% RE504 10K_0201_1% RE501 JKSO4 4 3
1M_0201_1% 1M_0201_1% 1M_0201_1% 1M_0201_1% JKSO3 5 4

2
5

1
JKSO2 6
RE639 JKSO1 7 6

G
2

2
1 6 JKSO0 8 7
1.1K_0402_1% 8

D
JKSI21 9
QE57B JKSI20 10 9

2
DMN66D0LDW-7_SOT363-6 JKSI19 11 10
JKSI18 12 11
JKSI17 13 12
+3VALW +3VALW JKSI16 14 13

3
JKSI15 15 14
1 2 5 G
D
JKSI14 16 15
<43> CAPS_LED 16
1

1
S JKSI13 17
RE640 QE57A JKSI12 18 17

4
18

1
RE505 RE506 1K_0201_1% DMN66D0LDW-7_SOT363-6 JKSI11 19
1M_0201_1% 1M_0201_1% JKSI10 20 19
RE641 JKSI9 21 20
2

1M_0201_1% JKSI8 22 21
JKSI7 23 22
KSI20 <43> KSI21 <43>

2
JKSI6 24 23
JKSI5 25 24
JKSI4 26 25
26
3

4 JKSI3 27 4
JKSI20 1 2 5 QE48B JKSI21 1 2 2 QE48A JKSI2 28 27
MMDT3904-7-F_SOT363-6 MMDT3904-7-F_SOT363-6 JKSI1 29 28 31
1

RE507 RE510 JKSI0 30 29 GND 32


4

10K_0201_1% RE509 10K_0201_1% RE508 30 GND


1M_0201_1% 1M_0201_1% ACES_51522-03001-P01
CONN@
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NKRO KB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 40 of 80
A B C D E
5 4 3 2 1

+5VALW

1
RM91
+5VALW 549_0402_1%

2
CDRA_LED WHITE_R

1
RM92
100K_0402_5%~D
+3VALW
CDRA_LED WHITE 20 mils

3
S

2
CDRA_LED WHITE_R 20 mils
G
D 2 D

0.1U_0402_10V7K
1 QM1

CM70
LP2301ALT1G 1P SOT-23-3

6
QM2B
D

1
2
D
G
2 <43> CDRA_LED WHITE_MOS S
CDRA_LED WHITE
DMN66D0LDW-7_SOT363-6

1
5
1

P
+3VALW <43> CDR_TXRX_GOOD B 4
2 O CDR_ON_ELC <37>
A

G
+5VALW

Caldera connector

1
RM41 TC7SH08FU_SSOP5~D +5VALW
100K_0402_5% UM7 RM93
JCDRA 100_0402_1%

1
1
Caldera_ON 2 CALDERA_ON <43> 221 ohm for white LED RM94

2
Caldera_PWRGD CALDERA_ PWRGD <43> CDRA_LED RED_R
3
PEG_CTX_C_GRX_P8 <7> 316 ohm for red LED 100K_0402_5%~D

1
T0+ 4
T0- PEG_CTX_C_GRX_N8 <7> on dock cable side

3
S
5
CDRA_LED RED 20 mils

2
GND 6 RM42 2
G
T1+ PEG_CTX_C_GRX_P9 <7>
T1-
7
8
PEG_CTX_C_GRX_N9 <7>
470K_0402_5%
QM3
CDRA_LED RED_R 20 mils

2
GND 9 LP2301ALT1G 1P SOT-23-3
T2+ PEG_CTX_C_GRX_P10 <7>

3
10 QM2A
D

1
T2- 11 PEG_CTX_C_GRX_N10 <7> 5
D
+3VALW G
GND 12 +3VALW <43> CDRA_LED RED_MOS S
PEG_CTX_C_GRX_P11 <7>

0.1U_0402_10V7K
T3+ 13 CDRA_LED RED
DMN66D0LDW-7_SOT363-6

4
T3- 14 PEG_CTX_C_GRX_N11 <7>
GND CRX_P8 1

1
15 2 1

CM23
R0+ 16 CRX_N8
RM5
R0- 17 RM6
GND CRX_P9 10K_0402_5%
18 2 10K_0402_5%
R1+ 19 CRX_N9

2
R1-

5
20
GND 21 CALDERA_PRSNT# 1

P
CALDERA_PRSNT# 22 CDRA_RST# CALDERA_PRSNT# <37,43> 4 B CALDERA_RST# <43>
PLTRST# 23 O 2
CRX_P10 PCH_PLTRST# <17,46>

G
GND 24 A
R2+ 25 CRX_N10
UM3

3
R2- 26 TC7SH08FU_SSOP5
BUTTON# 27 CDRA_LED WHITE CDR_BTN# <43>
LED_WHITE CDRA_LED RED

2
28
LED_RED 29 RM17
GND 30 CRX_P11
R3+ CRX_N11 100K_0402_5%
31
R3- 32
PCIE_CLK_BUFFER

1
C GND 33 CLK_PCIE_DGPU_C C
REFCLK+ 34 CLK_PCIE_DGPU#_C
REFCLK- 35
GND 36 USB3RN3_C 2 1 CI38
0.1U_0402_10V6K EMI@
SSTX+ 37 USB3RP3_C 2 1 CI39 USB3RN3 <19> +3VS
0.1U_0402_10V6K LM1
SSTX- USB3RP3 <19>
38 MCM1012B900F06BP_4P
GND 39 USB20_P3_CONN 3 4 +3VS +3VS
USBD+ USB20_N3_CONN USB20_P3 <19>
40 2 1

0.1U_0402_10V7K

0.1U_0402_10V7K
USBD- 41

CM16

CM17
GND 1 1

1
42 2 1 RM18 CM19
SSRX+ USB3TN3 <19> USB20_N3 <19>
43 RM20 2.2_0402_1% 22U_0603_6.3V6M
USB3TP3 <19>

1
SSRX- 44 RM96 1K_0402_1%

2
GND 45 CDR_I2C_CLK 2 1 RM97 2 2
0_0402_5% @ 4.7K_0402_5%
I2C_CLK 46 CDR_I2C_DAT 2 1 RM98 I2C_CLK <37,38,39>
0_0402_5% RM21

2
I2C_DATA 47 I2C_DAT <37,38,39>
1K_0402_1%
GND 48 UM4

2
GND 49 1 20
GND 50 2 1 RM89 EC_SMB_CK2 2 PLL_BW_SEL VDDA 19
0_0402_5% @
GND 2 1 RM90 EC_SMB_DA2 <17> CLK_PCIE_P6 3 SRCIN GNDA 18
0_0402_5% @ RM25 2 1 475_0402_1%
<17> CLK_PCIE_N6 4 SRCIN# IRef 17
OE_0# OE_1# CLKREQ#_DGPU <17,43>
TE_2260531-1 5 16
+3VS VDD VDD +3VS
CONN@ 6 15
7 GND GND 14 2 1 CLK_PCIE_DGPU_C
CM98 1 2 0.01U_0402_16V7K
8 CLK0 CLK1 13 2 RM27 1 33_0402_1% CLK_PCIE_DGPU#_C
CM99 1 2 0.01U_0402_16V7K
9 CLK0# CLK1# 12 RM28 33_0402_1%
10 VDD VDD 11

0.1U_0402_10V7K

0.1U_0402_10V7K

1
1
SDATA SCLK

1U_0402_6.3V

49.9_0402_1%
RM29

49.9_0402_1%
RM38
CM18

CM20
1 1
1

CM21
PI6CEQ20200LIEX
2 2

2
2
2

<18> SML0DATA

<18> SML0CLK

+2.5VOUT
B 20mil B

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
1 1 1 1 1

CM9

CM32

CM34

CM35

CM36
2 2 2 2 2
14
41
36
51
9

UM8
VDD
VDD
VDD
VDD
VDD

1 2 PEG_CRX_GTX_C_P11 1 45 CRX_P11
CM67 0.22U_0201_6.3V6M
<7>
<7>
<7>
PEG_CRX_GTX_P11
PEG_CRX_GTX_N11
PEG_CRX_GTX_P8
CM69
CM63
1
1
2
2
0.22U_0201_6.3V6M
0.22U_0201_6.3V6M
PEG_CRX_GTX_C_N11
PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_N8
2
3
OUTB_0+
OUTB_0-
OUTB_1+
INB_0+
INB_0-
INB_1+
44
43
CRX_N11
CRX_P8
CRX_N8
@ EQ*MB @
DEM*EGPU
CM66 1 2 0.22U_0201_6.3V6M 4 42 RM76 RM26 +3VS
To CPU <7>
<7>
<7>
PEG_CRX_GTX_N8
PEG_CRX_GTX_P10
PEG_CRX_GTX_N10
CM68
CM62
1
1
1
2
2
2
0.22U_0201_6.3V6M
0.22U_0201_6.3V6M
PEG_CRX_GTX_C_P10
PEG_CRX_GTX_C_N10
PEG_CRX_GTX_C_P9
5
6
7
OUTB_1-
OUTB_2+
OUTB_2-
INB_1-
INB_2+
INB_2-
40
39
38
CRX_P10
CRX_N10
CRX_P9
Form Caldera +3VS
1
1K_0201_1%
2
+3VS
1
1K_0201_1%
2
CM64 0.22U_0201_6.3V6M RM86
<7> PEG_CRX_GTX_P9 PEG_CRX_GTX_C_N9 OUTB_3+ INB_3+ CRX_N9
CM65 1 2 0.22U_0201_6.3V6M 8 37 1K_0201_1%
<7> PEG_CRX_GTX_N9 OUTB_3- INB_3- 1 2 1 2 1 2
EQA1 EQB1 DEMB1
10 35
11 INA_0+ OUTA_0+ 34 RM70 RM23 1 2
12 INA_0- OUTA_0- 33 1K_0201_1% 1K_0201_1%
13 INA_1+ OUTA_1+ 32 RM62
INA_1- OUTA_1- +3VS
15 31 1K_0201_1%
16 INA_2+ OUTA_2+ 30
INA_2- OUTA_2- @ @ @
17 29
18 INA_3+ OUTA_3+ 28 RM81 RM85
INA_3- OUTA_3- +3VS

2
1K_0201_1% 1K_0201_1%
54 1 2 1 2 @
DEMB1 RM61 RM66 +3VS +3VS
EQA1 19 DEMB1/AD0 53 DEMB0 20K_0402_5% RM79
EQA1 DEMB0/AD1 CALDERA_PRSNT# 1K_0201_1%
EQA0 20 52 2 1 1K_0201_1%
21 EQA0 PRSNT 50 2 1 RM99 EC_SMB_CK2 1 2 1 2 1 2
0_0402_5% EQA0 EQB0 DEMB0
EC_SMB_CK2 <18,42,43,46,58>

1
22 RATE DEMA1/SCL 49 2 1 RM100 EC_SMB_DA2
+3VS 0_0402_5%
RXDET DEMA0/SDA 48 EC_SMB_DA2 <18,42,43,46,58> 1 2
RM84 RM82
ENSMB 47 EQB1 1K_0201_1% 1K_0201_1%
+3VS
W=20 mils 23 EQB1/AD2 46 EQB0 RM75

1
24 LPBK EQB0/AD3 1K_0201_1%
25 VIN @
VGA_EN VGA_EN VDD_SEL
10U_0603_6.3V6M

1U_0402_6.3V

10U_0603_6.3V6M

1U_0402_6.3V

1 2 26 RM64
27 SD_TH/READ_EN 55 1K_0201_1%
1 1 1 1 ALL_DONE DAP_GND
CM29

CM30

CM31

CM33

RM14

2
1

1K_0201_1%
@
RM87 2 2 2 2 RM72 DS80PCI402SQNOPB_WQFN54_10X5P5
10K_0201_1% 10K_0201_1%
A A
2

Tie 1kΩ t o VDD = Regi st er Access S MBus Sl ave mode


FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ t o GND = Pi n Mode

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Caldera docking
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Monday, September 26, 2016 Sheet 41 of 80
5 4 3 2 1
5 4 3 2 1

+3VS +5VS

22U_0805_6.3VAM
1

CF4
10K_0402_5%

10K_0402_5%

10K_0402_5%
2

2
2

RF1

RF2

RF3
CONN@
D JFAN1 D
6

1
5 GND
GND
4
3 4
<43> CPU_FAN_PWM 2 1 2 3
<43> CPU_FAN_FB 2
DF1 1
SDMK0340L-7-F_SOD323-2 1
CVILU_CI1804M1VRA-NH

CPU FAN Control circuit

+3VS +5VS

22U_0805_6.3VAM
1

CF5
10K_0402_5%

10K_0402_5%

10K_0402_5%
2

2
2

RF4

RF5

RF6
CONN@
JFAN2
6

Fintek thermal sensor---> CPU core, DIMM

1
5 GND
GND
4
3 4
+3VS <43> GPU_FAN_PWM 2 1 2 3
+3VS <43> GPU_FAN_FB 1 2
DF2
SDMK0340L-7-F_SOD323-2 1

1
CVILU_CI1804M1VRA-NH
1 R181
C2498 U2407 10K_0402_5%
0.1U_0402_10V6K @

GPU FAN Control circuit

2
2 1 10 EC_SMB_CK2
VCC SCL EC_SMB_CK2 <18,41,43,46,58>
2 9 EC_SMB_DA2
REMOTE1+
DP1 SDA EC_SMB_DA2 <18,41,43,46,58>
C REMOTE1- 1 @ 2 REMOTE2- 3 8 C
DN ALERT#
REMOTE2+ R368 4 7
0_0402_5% DP2 THERM#
REMOTE3+ 5 6 1 @ 2 REMOTE3-
DN3 DP3 GND/DN3
R185
F75305M_MSOP10 0_0402_5%

Address 1001_101xb
2nd source
SA000029210-->EMC1403-2-AIZL-TR

REMOTE1+ TOP CPU PWR


Close U2407
1

C
REMOTE1+ @ C2500 2 Q2407
2200P_0402_25V7K B S TR METR3904W-G NPN SOT323-3
1
2

E
3

C2502 REMOTE1-
2200P_0402_25V7K
2 REMOTE1-

REMOTE2+
1 REMOTE2+ BOTTOM GPU PWR
1

C2504 C
2200P_0402_25V7K @ C2505 2 Q2408
2 REMOTE2- 2200P_0402_25V7K B S TR METR3904W-G NPN SOT323-3
2

E
3

B REMOTE2- B
REMOTE3+
1
C2510
2200P_0402_25V7K
2 REMOTE3- REMOTE3+ Reserved
1

C
@ C2511 2 Q2411
2200P_0402_25V7K B S TR METR3904W-G NPN SOT323-3
2

E
3

REMOTE3-

A A

Security Classification
2015/09/18
Compal Secret Data
2016/09/18 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN/Thermal
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 42 of 80
5 4 3 2 1
5 4 3 2 1

+3VALW
SD028000080 0_0402_5%
SD034120280 12K_0402_1%

1
47K_0402_5%
SD034150280 15K_0402_1%

RE530
UE10
Power ON circuit SD028200280
SD034270280
20K_0402_1%
27K_0402_1%
EC_ESB_CLK 1

2
ESB_CLK TEST_EN#
13

14 EN_WOL#
<32> SPEAKER_SEL EN_WOL# <30>

2
+3VLP GPIO00 GPIO08/CAS_DAT
EMI@ SD034330280 33K_0402_1% 3 15
RST# GPIO09 EC_NVVDD1_EN <55>
+EC_VCCA SD034430280 43K_0402_1%

0.1U_0402_16V7K~D
LE1
+3VALW FBMA-L11-160808-800LMT_0603 EC_ESB_DAT 4 16
SD034560280 56K_0402_1% ESB_DAT GPIO0A EC_FBVDD/Q_EN <55>

2
+EC_VCCA 2 USBC_PWR_EN
SD034750280 75K_0402_1%

CE63
RE63 1 2 5 17
<36> USBC_PWR_EN GPIO01 GPIO0B EC_PEX_VDD_EN <68>
100K_0402_5% 1 1 2 2
@
SW1
CE29 CE30 @EMI@ @EMI@ 1 SD034100380 100K_0402_1% <38> ELC_EC#
6
GPIO02 GPIO0C/PWM0
18
TYPEC_DET# <36>
+3VLP 1
D 1 0.1U_0402_10V7K 0.1U_0402_10V7K CE31
1000P_0402_50V7K
CE32
1000P_0402_50V7K
CE33
0.1U_0402_10V7K
SD034130380 130K_0402_1% 7 19
D
EC_NVVDD2_EN <55>
1 2 ON/OFF#
ON/OFF# <38>
2 2 1 1
2
SD034160380 160K_0402_1% GPIO03 GPIO0D/PWM1
8 20
SD034200380 200K_0402_1% <58> PD_RESET GPIO04 GPIO0E/PWM2 EC_3V3_SYS_EN <55>
TST71A-N-220-S017 SPST
ECAGND
SD000001B80 240K_0402_1% <20,46> GC6_FB_EN
9
GPIO05 GPIO0F/PWM3
21
@
SW2 ECAGND <61> SD00000G280 270K_0402_1% <46> GPU_ALERT#
10 22
EC_1V8_AON_EN <55>
GPIO06 GPIO10/ESB_RUN#

111
125
SD034330380 330K_0402_1%

22
33
96

67
9
1 2 UE5 11 23
SD028430380 430K_0402_1% <31> EC_MUTE# GPIO07/CAS_CLK GPIO11/BaseAddOpt

VCC0
VCC_LPC
VCC
VCC
VCC

VCC

AVCC
12 24

GND
GND VCC +3VALW
TST71A-N-220-S017 SPST

0.1U_0402_16V4Z
1 RE646 1

CE62
0_0201_5% 1 21 KC3810_QFN24_4X4
<20,55> DGPU_PWR_EN CDRA_LED WHITE_MOS <41>

25
CE27 2 @ 1 2 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F 23
0.1U_0402_16V7K <19> KB_RST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 BEEP# <31>
2 <19> SERIRQ 4 SERIRQ EC_FAN_PWM/GPIO12 27 CPU_FAN_PWM <42> 2
<19> LPC_FRAME# LPC_FRAME# PWM Output AC_OFF/GPIO13 GPU_FAN_PWM <42>
5
<19> LPC_AD3 7 LPC_AD3 2 1 100P_0402_50V8J
@EMI@ @EMI@ CE35 ECAGND
<19> LPC_AD2 8 LPC_AD2 63
CE36 RE89
<19> LPC_AD1 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 VCIN_ BATT_TEMP <61,62>
0.1U_0402_10V7K 0_0402_5% LPC & MISC
2 1 1 2 <19> LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 65 PCIE_WAKE# <18,30>
12 ADP_I/AD2/GPIO3A 66 AD_BID ADP_I <61,62>
<19> CLK_PCI_LPC CLK_PCI_EC AD Input AD_BID/AD3/GPIO3B
13 75 +3VALW
<6,17,28,29,30,56> PCIRST# PCIRST#/GPIO05 AD4/GPIO42 USBCHG_DET_EC# <35>
1 37 76
EC_RST# AD5/GPIO43 ENBKL <24>
ESD@ 20
<20> EC_SCI# EC_SCI#/GPIO0E

2
CE34 38
<18> PM_SLP_SUS# CLKRUN#/GPIO1D
0.047U_0402_16V4Z RE64
2 68 100K_0402_1%
DA0/GPIO3C EN_INVPWR <25> Ra
DA Output EN_DFAN1/DA1/GPIO3D 70
55 71 TBT_PCIE_WAKE# <56>
<40> KSI0 ME_SUS_PWR_ACK <18>

1
+3VALW 56 KSI0/GPIO30 DA2/GPIO3E 72 AD_BID
<40>
<40>
KSI1
KSI2
57 KSI1/GPIO31
KSI2/GPIO32
DA3/GPIO3F LCD_TEST <25>
Board ID
58 83 1
<40> KSI3 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A I2C0_SCL_EC <31,32>

1
KSI4 59 84
<40> KSI4 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B I2C0_SDA_EC <31,32>
KSI5 60 85 +3VALW Rb RE66 CE28
1 2 EN_WOL# <40> KSI5 61 KSI5/GPIO35 PSCLK2/GPIO4C 86 KSI20 <40>
C RE79 10K_0402_5% KSI6 PS2 Interface 33K_0402_1% 0.1U_0402_10V7K C
<40> KSI6 62 KSI6/GPIO36 PSDAT2/GPIO4D 87 TP_CLK KSI21 <40> 2
KSI7
1 2 LID_SW# <40> KSI7 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK <38>
RE70 10K_0402_5%
<40> KSO0 TP_DATA <38>

2
40 KSO0/GPIO20 TP_DATA/GPIO4F
1 2 EC_ESB_CLK <40> KSO1 41 KSO1/GPIO21
RE642 4.7K_0402_5%
<40> KSO2 KSO2/GPIO22

0.1U_0402_16V4Z~D
KSO3 42 97
1 2 EC_ESB_DAT <40> KSO3 43 KSO3/GPIO23 ENKBL/GPXIOA00 98 SUSACK# <18>
RE643 4.7K_0402_5% 1 UH5
<40> KSO4 KSO4/GPIO24 WOL_EN/GPXIOA01 EDP_SW <20,24>

2
44 99 AH1806-W-7 SC59 3P OMNIPOLAR SW
GPU_ALERT# KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 ME_EN <18>

CH2
RE644 2 1 100K_0402_5% 45 109
KSO6/GPIO26 Matrix

VDD
<40> KSI16 46 VCIN0_PH1/GPXIOD00 VCIN0_PH1 <61>
1 2 USB_PWR_EN <40> KSI17 47 KSO7/GPIO27 2
RE645 10K_0402_5% SPI Device Interface
<40> KSI8 48 KSO8/GPIO28 119 3 LID_SW# +3VS_TOUCH
1 2 USBC_PWR_EN <40> KSI9 49 KSO9/GPIO29 MISO/GPIO5B 120 PWRSHARE_EN_EC# <35> OUTPUT LID_SW# <37>
RE647 10K_0402_5% CDR_BTN# <41>
<40> KSI10 50 KSO10/GPIO2A MOSI/GPIO5C 126
SPI Flash ROM SPICLK/GPIO58

GND
2 1 PCH_PWROK <40> KSI11 51 KSO11/GPIO2B 128 3V_F383_ON CDRA_LED RED_MOS <41> TP_CLK 2 1
RE75 10K_0402_5% 1
<40> KSI12 52 KSO12/GPIO2C SPICS#/GPIO5A 3V_F383_ON <37>
4.7K_0402_5% RE100
2 1 3V_F383_ON <40> KSI13 53 KSO13/GPIO2D TP_DATA 2 1
RE83 10K_0402_5% CH1
<40> KSI14

1
54 KSO14/GPIO2E 73 10P_0402_50V8J~D 4.7K_0402_5% RE101
<40> KSI15 81 KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 74 SYS_PWROK PM_SLP_S4# <18,45,65> 2
<40> KSI18 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89 SYS_PWROK <18>
<40> KSI19 KSO17/GPIO49 GPIO50 90 PD_IRQ# <58>
BATT_CHG_LED#/GPIO52 91 BATT_CHG_LED# <37>
EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 CAPS_LED <40>
<61,62> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CLK1/GPIO44 GPIO PWR_LED#/GPIO54 PWR_LED# <38>
78 93
<61,62> EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <37>
79 95 SYSON
<18,41,42,46,58> EC_SMB_CK2 EC_SMB_DA2 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 SYSON <45,64>
<18,41,42,46,58> EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 127 IMVP_VR_ON <45,73>
DPWROK_EC/GPIO59 PCH_DPWROK <18> 1
SM Bus 1
ESD@ CE42
PM_SLP_S3# 6 100 CE38 0.1U_0402_10V7K
<18,37,45> PM_SLP_S3# PM_SLP_S5# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# <18> 2
0.1U_0402_10V7K
+3VALW <18,37> PM_SLP_S5# 15 GPIO07 GPXIOA04 102 VR_PWRGD <73> 2
<56> TBT_RESET_N_EC 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCOUT1_PROCHOT# VCIN1_ADP_PROCHOT <61>
+3VS <61> PS_ID EC_ESB_CLK 17 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 104
1 2 EC_SMB_CK1 EC_ESB_DAT 18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 VCOUT0_MAIN_PWR_ON# <63>
RE92 2.2K_0201_5% RE74 ESD@
1 2 EC_SMB_DA1 19 GPIO0C BKOFF#/GPXIOA08 106 BKOFF# <25> LID_SW# 1 2
RE93 2.2K_0201_5% GPIO GPO 43_0402_1%
1 2 EC_SMB_CK2 <17,41> CLKREQ#_DGPU 25 AC_PRESENT/GPIO0D GPXIOA09 107 PBTN_OUT# <9,18> 2 1
RE94 2.2K_0201_5% CE43 0.1U_0402_10V7K
1 2 EC_SMB_DA2 <38> TP_LED_EN 28 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 108 PCH_PWR_EN <45,66>
B RE95 2.2K_0201_5% ESD@ B
<42> CPU_FAN_FB 29 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 CALDERA_ON <41> PCH_PWROK 1 2
<42> GPU_FAN_FB EC_TX 30 FANFB1/GPIO15 CE44 0.1U_0402_10V7K
<28> EC_TX EC_RX EC_TX/GPIO16
31 110 ESD@
<28> EC_RX PCH_PWROK 32 EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 112 VCIN1_AC_IN <18,37,61,62> SYS_PWROK 1 2
<18> PCH_PWROK EC_RTCRST PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <63> 2
34 114 ON/OFF# EMI@ CE46 0.1U_0402_10V7K
36 SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 115 LID_SW# CE40
NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04 116 100P_0402_50V8J
SUSP#/GPXIOD05 117 SUSP# <29,45,56,64,67,76> 1
GPXIOD06 118 PECI_KB9012 USB_PWR_EN
1 <35> 2
122 PECI/GPXIOD07 H_PECI <9,16>
2 1 PM_SLP_S3# <66> +1VALWP_PGOOD 123 PBTN_OUT#/GPIO5D 124 1 2
+V18R @ +3VALW RE76
<9,45> H_VCCST_PWRGD PM_SLP_S4#/GPIO5E V18R/VCC_IO2 43_0402_1% UE6
EC_ESB_CLK
AGND

CE41 ESD@ RE24 1 13


GND
GND
GND
GND
GND

0.1U_0402_10V7K 0_0603_5% ESB_CLK TEST_EN#


2 14 TS_EN
PM_SLP_S5# <18> PCH_RTCRST# <31> DEPOP#_EC GPIO00 GPIO08/CAS_DAT TS_EN <25>
2 1 KB9022QD_LQFP128_14X14
11
24
35
94
113

69

LE2 RST# 3 15
RST# GPIO09 CALDERA_ PWRGD <41>
CE45 ESD@ FBMA-L11-160808-800LMT_0603
1

0.1U_0402_10V7K D ECAGND 2 1 EC_ESB_DAT 4 16


2 EC_RTCRST ESB_DAT GPIO0A CALDERA_RST# <41>
QE5
2N7002W-T/R7_SOT323-3 G +3VALW 5 17
Please close to EC <37,41> CALDERA_PRSNT# GPIO01 GPIO0B
1

S
3

47K_0402_5%
RE650 JEC 6 18
<38> PWR_R_EC GPIO02 GPIO0C/PWM0 CDR_TXRX_GOOD <41>

1
10K_0402_5% KSO3 1
KSI6 2 1 7 19

RE91
3 2 <35> CTL1 GPIO03 GPIO0D/PWM1 DGPU_PWROK <20>
KSI7
2

KSI4 4 3 8 20
4 <35> CTL2 GPIO04 GPIO0E/PWM2 AMD#_NV <37>
<9,61,62> H_PROCHOT# KSI5 5
2
EC_TX 6 5 9 21
+3VS EC_RX 7 6 <46> EC_AC_BAT# GPIO05 GPIO0F/PWM3 GPU_OVERT# <55>
RST#
8 7 10 22
8 <38> PWR_G_EC GPIO06 GPIO10/ESB_RUN# PWR_B_EC <38>
0.1U_0402_16V7K~D

1 @ 2
<73> VR_HOT#
1

2 11 23
9 <37> PCIE_GEN3#_GEN2 GPIO07/CAS_CLK GPIO11/BaseAddOpt
RE78 RE84
GND1
CE55

0_0402_5% 10K_0402_5% 10 12 24

GND
GND2 GND VCC +3VALW

0.1U_0402_16V4Z
ACES_50521-0084N-P01 1
A 1 A
2
1

CE56
CONN@ KC3810_QFN24_4X4

25
QE2 2 1 2 VCOUT1_PROCHOT#
2N7002W-T/R7_SOT323-3 G
S RE85 2

Reserve for abnormal shutdown


3

1 53.6K_0402_5%
CE51
0.033U_0402_25V @
1 2 EC_RSMRST#
2 <61,63> POK
DE2 RB751V-40_SOD323-2
@
1
DE3
2 PCH_PWROK
RB751V-40_SOD323-2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title
@
1 2 PCH_DPWROK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB9022/KB3810
DE4 RB751V-40_SOD323-2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 43 of 80
5 4 3 2 1
A B C D E

20m ohm/6A per channel


+VCCST switch
1
4.4mohm/6A 1
+5VALW

@
+5VS

+1VALW
TR=12.5us@Vin=1.05V
U17 J4
1 14 5VS 2 1 U19 +VCCST
2 VIN1 VOUT1 13 2 1 1
VIN1 VOUT1 C2506 JUMP_43X79 2 VIN1
+5VALW VIN2

C2523

0.1U_0402_10V7K

C256

10U_0603_6.3V6M

C257

10U_0603_6.3V6M
SUSP# 3 12 1 2
<29,43,56,64,67,76> SUSP# ON1 CT1 +5VALW 7 6
220P_0402_50V8J 1 1 1
W=10 mils 4
VBIAS GND
11 1
VIN thermal VOUT
1
C2507 3

1U_0402_6.3V6K
3VS_GATE 1 VBIAS
1 2 5 10 1 2 C2521 C6
ON2 CT2 2 2 2

C4
470P_0402_50V7K 0.1U_0402_10V7K 4 5 0.1U_0402_10V7K
R174 6 9 3VS 2 ON GND 2
1 VIN2 VOUT2
10K_0402_5% C258 +3VALW 7 8 2
0.1U_0402_16V7K VIN2 VOUT2 TPS22961DNYR_WSON8
15
2 GPAD
AOZ1331_SON14_2X3 +3VS
@ SYSON
<43,64> SYSON
J5
2 1

TI S A00007XR00 ( S I C TPS22961 DNYR WS ON 8P L OAD S WITCH)


+5VALW +3VALW +5VALW 2 1

 AOS S A00008A800 ( S I C AOZ1334 DI- 01 DF N 8P SI NGLE L OAD S W)


JUMP_43X79
Main source

C2524

0.1U_0402_10V7K

C260

10U_0603_6.3V6M

C261

10U_0603_6.3V6M
 E MC S A00008R600 ( S I C E M5201V DF N3X3 8P L OAD S WITCH)
1 1 1 2nd source

 APEC S A00006V300 ( S I C APE8939 GN3 DF N 8P L OAD S WITCH)


C2525 3rd source
0.1U_0402_10V7K

C262

10U_0603_6.3V6M

C263

0.1U_0402_10V7K

C264

10U_0603_6.3V6M

C265

0.1U_0402_10V7K
2 2 2 4st source
1 1 1 1 1

2 2 2 2 2

2 2

+VCCSTG switch
4.4mohm/6A
+1VALW
TR=12.5us@Vin=1.05V
+3VALW
U20 +VCCSTG
1
2 VIN1
VIN2
+5VALW +5VALW 7 6
VIN thermal VOUT
1
C269

10U_0603_6.3V6M

C270

0.1U_0402_10V7K

1 1 3
VBIAS

1U_0402_6.3V6K
1 1 C10

20m ohm/6A

C7
C2520 4 5 0.1U_0402_10V7K
+3V_PCH ON GND 2
0.1U_0402_10V7K
2 2
2 2 @ TPS22961DNYR_WSON8
U18 J6
5 1 +3VALW_PCH 2 1
IN OUT 2 1
2 JUMP_43X79
GND

C2522

0.1U_0402_10V7K

C266

10U_0603_6.3V6M

C267

10U_0603_6.3V6M
<43,66> PCH_PWR_EN
W=10 mils 4
EN OC
3 1 2
+3V_PCH 1 1 1
SUSP#
SY6288C20AAC_SOT23-5 R367

TI S A00007XR00 ( S I C TPS22961 DNYR WS ON 8P L OAD S WITCH)


10K_0402_5%
1

2 2 2

 AOS S A00008A800 ( S I C AOZ1334 DI- 01 DF N 8P SI NGLE L OAD S W)


C268
0.01U_0402_16V Main source

 E MC S A00008R600 ( S I C E M5201V DF N3X3 8P L OAD S WITCH)


2nd source
2

 APEC S A00006V300 ( S I C APE8939 GN3 DF N 8P L OAD S WITCH)


3rd source
4st source
3 3

add for power down sequence For meet tPLT17 & tCPU28 power down sequence.
IMVP_VR_ON <43,73> tPLT17 : 1us (Max) +1.2V_VCCPLL_OC switch
tCPU28 : 1us (Max)
6

@
Q7A
DMN65D8LDW-7_SOT363-6
22mohm/4A
2
For meet tPLT15 power down sequence(Un-Stuf f) TR=520us@Vin=0.8V
tPLT15 : 1us (Max)
1

+1.2V_DDR +1.2V_VCCPLL_OC
UZ21
+3VALW
+3VALW 1 7
2 VIN VOUT 8
VIN VOUT
1

@ 1
1

R307 @ SYSON SUSP# 3 6 C3 1 2


H_VCCST_PWRGD <9,43> ON CT
100K_0402_1% R325 @ C11
100K_0402_1% 2200P_0402_25V7K 0.1U_0402_10V7K
3

@ 4 2
+5VALW
2

Q9B VBIAS 5
1
2

GND 9
DMN65D8LDW-7_SOT363-6 GND
PM_SLP_S3_H 5 @ PM_SLP_S4_H 5 C2518
Q7B 0.1U_0402_10V7K
6

@ 2 TPS22967DSGR_SON8_2X2
DMN65D8LDW-7_SOT363-6
4

Q9A
6

DMN65D8LDW-7_SOT363-6
2
<18,43,65> PM_SLP_S4# +5VALW
PM_SLP_S3# 2 @
1

<18,37,43> PM_SLP_S3# Q8A 1


4 DMN65D8LDW-7_SOT363-6 SUSP# 4
1

C2519
0.1U_0402_10V7K
3

5 @
Q8B
DMN65D8LDW-7_SOT363-6
4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 45 of 80
A B C D E
5 4 3 2 1

+1V8_AON +1V8_AON

2
1 RG2 UG9A
CG483 10K_0201_5% 1/23 PCI_EXPRESS
0.1U_0201_6.3V6K +PEX_VDD

1
5
2 BB33
DGPU_PEX_RST# BK26 PEX_DVDD_1 BB35

GND VCC

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

22U_0805_6.3V6M
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
1 PEX_RST* PEX_DVDD_2 BB36
<55,71> +1.35VS_VGA_PGOOD IN B PEX_CLKREQ# PEX_DVDD_3 1 1 1 1 1 1 2 1
4 BL26 BC33

CG2

CG3

CG4

CG5

CG6

CG7
CG13

CG14
2 OUT Y PEX_CLKREQ* PEX_DVDD_4 BC35
<55,69,70> NVVDD1_PGOOD IN A PEX_DVDD_5
BM26 BC36
<17> CLK_PEG_GPU BM27 PEX_REFCLK PEX_DVDD_6 BD33 2 2 2 2 2 2 1 2
UG29
<17> CLK_PEG_GPU# PEX_REFCLK* PEX_DVDD_7 BD36
NL17SZ08DFT2G_SC70-5

3
PEG_CRX_GTX_P0_C PEX_DVDD_8

2
D CG8 1 2 0.22U_0201_6.3V BG26 D
<7> PEG_CRX_GTX_P0 1 2 0.22U_0201_6.3V PEG_CRX_GTX_N0_C BH26 PEX_TX0
RG1 CG9
<7> PEG_CRX_GTX_N0 PEX_TX0*
0_0201_5%
<7> PEG_CTX_C_GRX_P0
BL27
BK27 PEX_RX0 Under GPU

1
<7> PEG_CTX_C_GRX_N0 PEX_RX0* +1V8_MAIN
1 2 0.22U_0201_6.3V PEG_CRX_GTX_P1_C BF26
CG10
<7> PEG_CRX_GTX_P1 PEG_CRX_GTX_N1_C PEX_TX1
CG16 1 2 0.22U_0201_6.3V BE26 BB26
<7> PEG_CRX_GTX_N1 PEX_TX1* PEX_HVDD_1 BB27

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
PEX_HVDD_2

2
BK29 BB29

G
<7> PEG_CTX_C_GRX_P1 PEX_RX1 PEX_HVDD_3 1 1 1 1 1 1 2 2 1
BL29 BB32

CG23

CG17

CG18

CG19

CG20

CG11

CG12

CG21

CG24
1 3 <7> PEG_CTX_C_GRX_N1 PEX_RX1* PEX_HVDD_4 BC26
<17> CLKREQ#_GPU PEG_CRX_GTX_P2_C PEX_HVDD_5
CG22 1 2 0.22U_0201_6.3V BF27 BC27

S
<7> PEG_CRX_GTX_P2 1 2 0.22U_0201_6.3V PEG_CRX_GTX_N2_C BG27 PEX_TX2 PEX_HVDD_6 BC29 2 2 2 2 2 2 1 1 2
CG25
<7> PEG_CRX_GTX_N2 PEX_TX2* PEX_HVDD_7 BC30
QG510 BM29 PEX_HVDD_8 BC32
<7> PEG_CTX_C_GRX_P2 BM30 PEX_RX2 PEX_HVDD_9 BD27
MESS138W-G_SOT323-3
<7> PEG_CTX_C_GRX_N2 PEX_RX2* PEX_HVDD_10 BD30
<7>
<7>
PEG_CRX_GTX_P3
PEG_CRX_GTX_N3
CG26
CG27
1
1
2 0.22U_0201_6.3V
2 0.22U_0201_6.3V
PEG_CRX_GTX_P3_C
PEG_CRX_GTX_N3_C
BG29
BH29 PEX_TX3
PEX_TX3*
PEX_HVDD_11
Under GPU
BL30
<7> PEG_CTX_C_GRX_P3 PEX_RX3
BK30
<7> PEG_CTX_C_GRX_N3 PEX_RX3*
1 2 0.22U_0201_6.3V PEG_CRX_GTX_P4_C BF29
CG28
<7> PEG_CRX_GTX_P4 PEG_CRX_GTX_N4_C PEX_TX4
CG29 1 2 0.22U_0201_6.3V BE29
<7> PEG_CRX_GTX_N4 PEX_TX4*
BK32
<7> PEG_CTX_C_GRX_P4 BL32 PEX_RX4
<7> PEG_CTX_C_GRX_N4 PEX_RX4*
1 2 0.22U_0201_6.3V PEG_CRX_GTX_P5_C BF30
CG30
<7> PEG_CRX_GTX_P5 1 2 0.22U_0201_6.3V PEG_CRX_GTX_N5_C BG30 PEX_TX5
CG31
<7> PEG_CRX_GTX_N5 PEX_TX5* +PEX_PLL_HVDD
BB30 1 2
PEX_PLL_HVDD +1V8_MAIN
BM32
<7> PEG_CTX_C_GRX_P5 BM33 PEX_RX5
1 LG1
<7> PEG_CTX_C_GRX_N5 PEX_RX5* CG34 PBY160808T-301Y-N
1 2 0.22U_0201_6.3V PEG_CRX_GTX_P6_C BG32
CG32 0.1U_0201_6.3V6K
<7> PEG_CRX_GTX_P6 PEG_CRX_GTX_N6_C PEX_TX6
CG33 1 2 0.22U_0201_6.3V BH32
<7> PEG_CRX_GTX_N6 PEX_TX6* 2
BL33
<7> PEG_CTX_C_GRX_P6 PEX_RX6
+3V3_SYS BK33
<7> PEG_CTX_C_GRX_N6 PEX_RX6*
+1V8_AON
1 2 0.22U_0201_6.3V PEG_CRX_GTX_P7_C BF32
CG35
<7> PEG_CRX_GTX_P7 1 2 0.22U_0201_6.3V PEG_CRX_GTX_N7_C BE32 PEX_TX7
CG36
<7> PEG_CRX_GTX_N7 PEX_TX7*

1
1 @ BK35
1 2 <7> PEG_CTX_C_GRX_P7 BL35 PEX_RX7
CG1 RG6
<7> PEG_CTX_C_GRX_N7 PEX_RX7*
0.1U_0201_6.3V6K 10K_0201_5%
RG3 @ BF33

2
2 GPU_PEX_RST_HOLD# 3 BG33 PEX_TX8
10K_0201_5%
PEX_TX8*
5

C @ C
1 DGPU_PEX_RST# BM35
RG537
GND VCC

DGPU_HOLD_RST# DGPU_PEX_RST# <26,27,55> PEX_RX8


1 0_0201_5% BM36
<20> DGPU_HOLD_RST# IN B 4 1 2 SYS_PEX_RST_MON# 2 PEX_RX8*
PCH_PLTRST# 2 OUT Y BG35
<17,41> PCH_PLTRST# IN A PEX_TX9
DG1 BH35
1

BAT54A-7-F_SOT23-3 PEX_TX9*
UG10 @ BL36
3

NL17SZ08DFT2G_SC70-5 RG562 BK36 PEX_RX9


100K_0402_5% +1V8_AON PEX_RX9*
1 2 BF35
22uF 10uF 4.7uF 1uF 0.1uF
2

BE35 PEX_TX10
PEX_TX10*

1
RG7 RG500 BK38
0_0201_5% 10K_0201_5% BL38 PEX_RX10
PEX_RX10* PEX_DVDD 1 1 2 4
BF36

2
BG36 PEX_TX11
EDP_HPD_GPU# PEX_TX11*
BM38 PEX_HVDD 1 2 2 4
BM39 PEX_RX11

3
PEX_RX11*
5 BG38
D
QG500A G
EDP_HPD_GPU <24> BH38 PEX_TX12
DMN66D0LDW-7_SOT363-6 S
PEX_TX12*

1
BL39
RG519 BK39 PEX_RX12
PEX_RX12*

6
100K_0201_5%
2 BF38
D
G

S BE38 PEX_TX13

2
DMN66D0LDW-7_SOT363-6 PEX_TX13*

1
DGPU_PEX_RST# BK41
DGPU_PEX_RST# QG500B PEX_RX13
BL41
QG6B PEX_RX13*
5

QG501B DMN53D0LDW-7 2N SOT363-6 BF39


PEX_TX14
5

DMN53D0LDW-7 2N SOT363-6 BG39


VGA_SMB_CK2 4 3 DGPU_ENVDD PEX_TX14*
EC_SMB_CK2 <18,41,42,43,58>
ALERT# 4 3 BM41
GPU_ALERT# <43>
2

QG6A BM42 PEX_RX14


PEX_RX14*
2

QG501A DMN53D0LDW-7 2N SOT363-6


VGA_SMB_DA2 1 6 +1V8_AON +3VS BH41
DMN53D0LDW-7 2N SOT363-6
1 6 EC_SMB_DA2 <18,41,42,43,58> BG41 PEX_TX15
PEX_TX15*
PEX_TERMP

1
BL42 BL44 2 1
RG502 RG517 BK42 PEX_RX15 PEX_TERMP
10K_0201_5% 10K_0201_5% PEX_RX15* RG23
2.49K_0402_1%

2
G
2

2
FRAME_LOCK# 3 1 N17E-G1_BGA2152~D
B G-SYNC# <25> B

D
+1V8_AON

QG506
DGPU_PEX_RST#
MESS138W-G_SOT323-3

UG9W
1.8K_0402_1%

1.8K_0402_1%
1

13/23 MISC 1
RG11

RG12

VGA_SMB_CK2
OVERT# BG5 BJ8 QG7B
<55> OVERT# VGA_SMB_DA2
5

OVERT I2CS_SCL BH8 DMN53D0LDW-7 2N SOT363-6


2

I2CS_SDA
BF12 I2CC_SCL_R 4 3
TS_VREF I2CC_SCL I2CC_SCL <49>
BG9
I2CC_SCL I2CC_SDA
2

BH9 +1V8_AON QG7A +3VS


I2CC_SDA DMN53D0LDW-7 2N SOT363-6
I2CC_SDA_R 1 6
I2CC_SDA <49>
BG8 RG19 1 2 1.8K_0402_5%

1
I2CB_SCL BF8 RG20 1 2 1.8K_0402_5% +3VS
I2CB_SDA RG536
2.2K_0201_5%
BJ1
THERMDN

2
BJ2 +1V8_AON RG535
THERMDP 100K_0201_5%
DGPU_INV_PWM <24>
@
GC6_EVENT#_D 1 2
RG563 RG8 10K_0201_5%

6
BD6 +1V8_AON +3VS D
0_0201_5%
GPIO0 BB5 GPU_GC6_FB_EN NVVDD_VID <69> 2 1 1 2 2
OVERT# RG9 10K_0201_5% UG24A
GPIO1 GC6_EVENT#_D GPU_GC6_FB_EN_R <17>
BD1 2 1 G BSS138DW_SC88-6
GPIO2 BE4 GC6_EVENT# <20> DGPU_HOLD_RST# 1 2
RG13 @ 10K_0201_5%
GPIO3 NVVDDS_VID <70>

3
BE1 D
DG2 S

1
GPIO4 FRAME_LOCK# 1V8_MAIN_EN <55> GPU_PEX_RST_HOLD# GPU_INV_PWM
BG2 RB751S40T1G_SOD523-2 RG14 1 2 10K_0201_5% RG561 5 UG24B
GPIO5 BD2 1 2 NVVDD_PSI G
RG566 0_0201_5% 100K_0201_5% BSS138DW_SC88-6
GPIO6 GPU_INV_PWM NVVDD_PSI <69> EC_AC_BAT#
BD7 RG16 1 2 100K_0201_5%
JTAG_TCLK MEM_VDD_CTL

2
GPIO7

G
@ T10 PAD~D BK24 BH4 S

4
JTAG_TMS BL23 JTAG_TCK GPIO8 BJ3 MEM_VDD_CTL <71> VGA_SMB_CK2 1 2
@ T11 PAD~D ALERT# RG17 1.8K_0402_5%
JTAG_TDI BM23 JTAG_TMS GPIO9 BD3 MEM_VREF GPU_GC6_FB_EN 3 1
@ T12 PAD~D
JTAG_TDO BM24 JTAG_TDI GPIO10 BH3 DGPU_ENVDD MEM_VREF <52,53,54> VGA_SMB_DA2 1 2 <55> GPU_GC6_FB_EN GC6_FB_EN <20,43>
@ T13 PAD~D RG18 1.8K_0402_5%

D
JTAG_TRST# JTAG_TDO GPIO11 DGPU_ENVDD <24>
BL24 BE6
JTAG_TRST* GPIO12 BB1 DGPU_ENBKL EC_AC_BAT# <43> SYS_PEX_RST_MON# 1 2
RG21 10K_0201_5%
GPIO13 BG4 DGPU_ENBKL <24>
RG555 1 @ 2 QG511
GPIO14 BG1 NVVDD_PSI 1 2
0_0402_5% RG15 10K_0201_5% MESS138W-G_SOT323-3
SYS_PEX_RST_MON#
1

BK23 GPIO15 BE2


NVJTAG_SEL GPIO16 BH1 EDP_HPD_GPU# NVVDDS_PSI
RG518 RG556 1 2 RG565 1 2 0_0201_5% RG503 1 @ 2 10K_0201_5%
10K_0201_5% GPIO17 BE3 0_0402_5%
GPIO18 BD4 DP_HPD_GPU# <26> 1 2
ALERT# RG504 10K_0201_5%
GPIO19 NVVDDS_PSI
1

A BE5 RG564 1 @ 2 A
2

GPIO20 BA5 NVVDDS_PSI <70> GPIO3_OC_WARN# 1 2


RG26 0_0201_5% RG522 10K_0201_5%
10K_0201_5% GPIO21 BB6
GPIO22 BG3 GPU_PEX_RST_HOLD#
GPIO23 BD5
2

GPIO24 BB2
GPIO25 BE7
GPIO26 BA4 GPU_GC6_FB_EN 1 2
RG22 10K_0201_5%
GPIO27 BB4 GPIO3_OC_WARN# HDMI_HPD_GPU# <27>
GPIO28 BA3 GPIO3_OC_WARN# <49> MEM_VREF 1 2
RG24 100K_0201_5%
GPIO29 BB3
GPIO30 BA2 DGPU_PEX_RST# 1 2
RG25 1M_0201_1%
GPIO31 BA1
GPIO32 GPU_INV_PWM 1 2
RG150 100K_0201_5%
DGPU_ENVDD 1 2
N17E-G1_BGA2152~D RG151 100K_0201_5%
DGPU_ENBKL
RG501 1 2 100K_0201_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2016/01/06 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17E-G1(1/6) PCIE,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 46 of 80
5 4 3 2 1
5 4 3 2 1

UG9V UG9U
11/23 MIOA 12/23 MIOB

UG9N AN9 AT3


MIOA_D0 AM2 MIOB_D0 AV6
7/23 IFPAB
MIOA_D1 AN7 MIOB_D1 AT2
MIOA_D2 AN6 MIOB_D2 AT1
MIOA_D3 AR1 MIOB_D3 AW6
DL-DVI DVI/HDMI DP
MIOA_D4 AR6 MIOB_D4 AV2
MIOA_D5 AR5 MIOB_D5 AV1
BH11 MIOA_D6 AM8 MIOB_D6 AV3
SDA SDA IFPA_AUX_SDA* BG11 MIOA_D7 AN3 MIOB_D7 AW3
SCL SCL IFPA_AUX_SCL MIOA_D8 MIOB_D8
AR8 BA8
RG36 MIOA_D9 AR3 MIOB_D9 AW7
1K_0402_1% BF21 AM5 MIOA_D10 AR2 AV7 MIOB_D10 BB8
D
2 1 IFPAB_RSET BD23 TX C TX C IFPA_L3* BG21 MIOA_CAL_PD_VDDQ MIOA_D11 MIOB_CAL_PD_VDDQ MIOB_D11 D
IFPAB_RSET TX C TX C IFPA_L3 AM6 AV8
MIOA_CAL_PU_GND MIOB_CAL_PU_GND

TXD0 TXD0
BG23
IFPA_L2* BH23
TXD0 TXD0 IFPA_L2
BD21 AM7 AW9
+1V8_MAIN IFPAB_PLLVDD MIOA_VREF MIOB_VREF
BF23

0.1U_0402_10V7K
TXD1 TXD1 IFPA_L1* BE23
1 TXD1 TXD1 IFPA_L1

CG312
TXD2 TXD2
BF24 AT7 BB7
2 IFPA_L0* BG24 MIOA_CTL3 AM1 MIOB_CTL3 AV5
TXD2 TXD2 IFPA_L0 MIOA_HSYNC MIOB_HSYNC
AR7 BA7
MIOA_VSYNC AN1 MIOB_VSYNC AW2
MIOA_DE MIOB_DE

GP104 GP106
Under GPU SDA IFPB_AUX_SDA*
BG12
BH12
MIOA_CLKOUT
AN2

AM3
MIOB_CLKOUT
AW1

AT6
+PEX_VDD SCL IFPB_AUX_SCL MIOA_CLKIN MIOB UNUSED MIOB_CLKIN

BL18 N17E-G1_BGA2152~D N17E-G1_BGA2152~D


BB17 TX C IFPB_L3* BK18
BB15 IFP_IOVDD_2 TX C IFPB_L3
1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K
4.7U_0603_6.3V6M

IFP_IOVDD_1
1 1 1 1
BB18 BK20
CG311

CG310

CG309

CG308

IFP_IOVDD_3 TXD3 TXD0 IFPB_L2*


BB20 TXD3 TXD0
BL20
IFP_IOVDD_4 IFPB_L2
2 2 2 2 UG9O
BM20 6/23 IFPF
TXD4 TXD1 IFPB_L1* BM21
TXD4 TXD1 IFPB_L1
DVI/HDMI DP

TXD5 TXD2
BL21
IFPB_L0* BK21 BC21 BM9
TXD5 TXD2 IFPB_L0 IFP_IOVDD_11 SDA IFPF_AUX_SDA*
C +PEX_VDD BC23 SCL
BM8 C
IFPAB IFP_IOVDD_12 IFPF_AUX_SCL

0.1U_0402_10V7K
Under GPU 1
BK11

CG40
TXC IFPF_L3*
N17E-G1_BGA2152~D TXC
BL11
IFPF_L3
2 BM11
TXD0 IFPF_L2*
TXD0
BM12
IFPF_L2
TXD1
BL12
IFPF_L1* BK12
TXD1 IFPF_L1

RG37
UG9R
8/23 IFPC
Under GPU IFPF
TXD2
TXD2
IFPF_L0*
IFPF_L0
BK14
BL14

1K_0402_1%
2 1 IFPCD_RSET BD20
IFPCD_RSET
DVI/HDMI DP
N17E-G1_BGA2152~D

+IFPX_PLLVDD BD18 BL9


IFPCD_PLLVDD SDA IFPC_AUX_SDA* BK9 HDMI_CTRLDAT <27>
SCL IFPC_AUX_SCL HDMI_CTRLCLK <27>
0.1U_0402_10V7K

1
BF17
CG47

TXC
TXC
IFPC_L3* BE17
TMDS_TXCN
TMDS_TXCP
<27>
<27>
22uF 10uF 4.7uF 1uF 0.1uF
IFPC_L3
2 BF18 TMDS_TX0N <27>

IFPC
TXD0
TXD0
IFPC_L2*
IFPC_L2
BG18

BG20
TMDS_TX0P <27> HDMI 2.0 IFPx_IOVDD 2 4
TXD1 IFPC_L1* TMDS_TX1N <27>
TXD1 BH20
IFPC_L1 TMDS_TX1P <27>
IFPx_PLLVDD 1 2
Under GPU TXD2
TXD2
IFPC_L0*
IFPC_L0
BF20
BE20
TMDS_TX2N
TMDS_TX2P
<27>
<27>

+PEX_VDD BB21
B
BB23 IFP_IOVDD_5 B
IFP_IOVDD_6 UG9P
0.1U_0402_10V7K

1 10/23 IFPE
N17E-G1_BGA2152~D
CG48

DVI/HDMI DP
RG38
1K_0402_1%
2 2 1 IFPEF_RSET BD17 BL8
IFPEF_RSET SDA IFPE_AUX_SDA* mDP_AUX#_SDA <26>
UG9Q SCL BK8
+1V8_MAIN +IFPX_PLLVDD IFPE_AUX_SCL mDP_AUX_SCL <26>
9/23 IFPD

1 2
Under GPU BD15
TXC IFPE_L3*
BG14
BH14
GPU_mDP_N3 <26>
DVI/HDMI DP GPU_mDP_P3 <26>
Under GPU LG5
IFPEF_PLLVDD TXC IFPE_L3
BF14
GPU_mDP_N2 <26> mini DP

22U_0805_6.3VAM

0.1U_0402_10V7K
TXD0 IFPE_L2*
BF11 PBY160808T-300Y-N_2P 1 1 TXD0 BE14 GPU_mDP_P2 <26>
SDA IFPD_AUX_SDA* GPU_AUXN/DDC <24> IFPE_L2
BE11

CG49
CG247
SCL IFPD_AUX_SCL GPU_AUXP/DDC <24> BF15
TXD1 IFPE_L1* GPU_mDP_N1 <26>
TXD1 BG15 GPU_mDP_P1 <26>
BM14 2 2 IFPE IFPE_L1
TXC IFPD_L3* GPU_TX3N <24>
TXC BM15 GPU_TX3P <24> TXD2
BG17 GPU_mDP_N0 <26>
IFPD_L3 IFPE_L0* BH17
TXD2 GPU_mDP_P0 <26>
TXD0
TXD0
IFPD_L2*
IFPD_L2
BL15
BK15
GPU_TX2N
GPU_TX2P
<24>
<24>
eDP IFPE_L0

IFPD BK17 BC18


TXD1 IFPD_L1* GPU_TX1N <24> IFP_IOVDD_9
TXD1 BL17 BC20
IFPD_L1 GPU_TX1P <24> +PEX_VDD IFP_IOVDD_10
0.1U_0402_10V7K
4.7U_0603_6.3V6M

TXD2
BM17 GPU_TX0N <24> 1 1
IFPD_L0* BM18
CG43

CG51

TXD2 IFPD_L0 GPU_TX0P <24>


N17E-G1_BGA2152~D

BC15 2 2
BC17 IFP_IOVDD_7
+PEX_VDD IFP_IOVDD_8
0.1U_0402_10V7K
4.7U_0603_6.3V6M

1 1
N17E-G1_BGA2152~D
CG42

CG53

A A
2 2

Under GPU

Under GPU Security Classification Compal Secret Data


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17E-G1(2/6) eDP,HDMI,mDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 47 of 80
5 4 3 2 1
5 4 3 2 1

D D

UG9B
2/23 FBA UG9C UG9D
3/23 FBB 4/23 FBC UG9E
U51 Y51 5/23 FBD
<52> FBA_D0 FBA_D0 FBA_CMD0 FBA_CMD1 FBA_CMD0 <52>
U48 Y52 H32 B35 C6 C11
<52> FBA_D1 FBA_D1 FBA_CMD1 FBA_CMD2 FBA_CMD1 <52> <53> FBB_D0 FBB_D0 FBB_CMD0 FBB_CMD1 FBB_CMD0 <53> <54> FBC_D0 FBC_D0 FBC_CMD0 FBC_CMD1 FBC_CMD0 <54>
U50 Y49 D32 A35 D6 B11 AK8 AD2
<52> FBA_D2 FBA_D2 FBA_CMD2 FBA_CMD2 <52> <53> FBB_D1 FBB_D1 FBB_CMD1 FBB_CMD2 FBB_CMD1 <53> <54> FBC_D1 FBC_D1 FBC_CMD1 FBC_CMD2 FBC_CMD1 <54> FBD_D0 FBD_CMD0
U49 AA52 A33 D35 A6 A11 AK4 AD1
<52> FBA_D3 R51 FBA_D3 FBA_CMD3 AA51 FBA_CMD3 <52> <53> FBB_D2 B32 FBB_D2 FBB_CMD2 A36 FBB_CMD2 <53> <54> FBC_D2 B6 FBC_D2 FBC_CMD2 D11 FBC_CMD2 <54> AK2 FBD_D1 FBD_CMD1 AD4
<52> FBA_D4 R50 FBA_D4 FBA_CMD4 AA50 FBA_CMD4 <52> <53> FBB_D3 E32 FBB_D3 FBB_CMD3 B36 FBB_CMD3 <53> <54> FBC_D3 B4 FBC_D3 FBC_CMD3 A12 FBC_CMD3 <54> AK3 FBD_D2 FBD_CMD2 AC1
<52> FBA_D5 R47 FBA_D5 FBA_CMD5 AC50 FBA_CMD5 <52> <53> FBB_D4 G32 FBB_D4 FBB_CMD4 C36 FBB_CMD4 <53> <54> FBC_D4 A4 FBC_D4 FBC_CMD4 B12 FBC_CMD4 <54> AK5 FBD_D3 FBD_CMD3 AC2
<52> FBA_D6 U46 FBA_D6 FBA_CMD6 AC51 FBA_CMD6 <52> <53> FBB_D5 J30 FBB_D5 FBB_CMD5 C38 FBB_CMD5 <53> <54> FBC_D5 B3 FBC_D5 FBC_CMD5 C12 FBC_CMD5 <54> AK6 FBD_D4 FBD_CMD4 AC3
<52> FBA_D7 V46 FBA_D7 FBA_CMD7 AC52 FBA_CMD7 <52> <53> FBB_D6 F32 FBB_D6 FBB_CMD6 B38 FBB_CMD6 <53> <54> FBC_D6 C4 FBC_D6 FBC_CMD6 C14 FBC_CMD6 <54> AK9 FBD_D5 FBD_CMD5 AA3
<52> FBA_D8 Y45 FBA_D8 FBA_CMD8 AC49 FBA_CMD8 <52> <53> FBB_D7 H36 FBB_D7 FBB_CMD7 A38 FBB_CMD7 <53> <54> FBC_D7 D9 FBC_D7 FBC_CMD7 B14 FBC_CMD7 <54> AK7 FBD_D6 FBD_CMD6 AA2
<52> FBA_D9 Y47 FBA_D9 FBA_CMD9 AD52 FBA_CMD9 <52> <53> FBB_D8 G36 FBB_D8 FBB_CMD8 D38 FBB_CMD8 <53> <54> FBC_D8 C9 FBC_D8 FBC_CMD8 A14 FBC_CMD8 <54> AG4 FBD_D7 FBD_CMD7 AA1
<52> FBA_D10 Y46 FBA_D10 FBA_CMD10 AD51 FBA_CMD10 <52> <53> FBB_D9 J36 FBB_D9 FBB_CMD9 A39 FBB_CMD9 <53> <54> FBC_D9 E9 FBC_D9 FBC_CMD9 D14 FBC_CMD9 <54> AF9 FBD_D8 FBD_CMD8 AA4
<52> FBA_D11 V50 FBA_D11 FBA_CMD11 AD50 FBA_CMD11 <52> <53> FBB_D10 F36 FBB_D10 FBB_CMD10 B39 FBB_CMD10 <53> <54> FBC_D10 B9 FBC_D10 FBC_CMD10 A15 FBC_CMD10 <54> AG6 FBD_D9 FBD_CMD9 Y1
<52> FBA_D12 V47 FBA_D12 FBA_CMD12 AF50 FBA_CMD12 <52> <53> FBB_D11 F33 FBB_D11 FBB_CMD11 C39 FBB_CMD11 <53> <54> FBC_D11 B8 FBC_D11 FBC_CMD11 B15 FBC_CMD11 <54> AG7 FBD_D10 FBD_CMD10 Y2
<52> FBA_D13 U52 FBA_D13 FBA_CMD13 AF51 FBA_CMD13 <52> <53> FBB_D12 D33 FBB_D12 FBB_CMD12 C41 FBB_CMD12 <53> <54> FBC_D12 A8 FBC_D12 FBC_CMD12 C15 FBC_CMD12 <54> AJ4 FBD_D11 FBD_CMD11 Y3
<52> FBA_D14 V51 FBA_D14 FBA_CMD14 AF52 FBA_CMD14 <52> <53> FBB_D13 J32 FBB_D13 FBB_CMD13 B41 FBB_CMD13 <53> <54> FBC_D13 F6 FBC_D13 FBC_CMD13 C17 FBC_CMD13 <54> AJ5 FBD_D12 FBD_CMD12 V3
<52> FBA_D15 AJ44 FBA_D15 FBA_CMD15 AN50 FBA_CMD15 <52> <53> FBB_D14 G33 FBB_D14 FBB_CMD14 A41 FBB_CMD14 <53> <54> FBC_D14 E6 FBC_D14 FBC_CMD14 B17 FBC_CMD14 <54> AJ6 FBD_D13 FBD_CMD13 V2
<52> FBA_D16 FBA_D16 FBA_CMD16 FBA_CMD17 FBA_CMD16 <52> <53> FBB_D15 FBB_D15 FBB_CMD15 FBB_CMD15 <53> <54> FBC_D15 FBC_D15 FBC_CMD15 FBC_CMD15 <54> FBD_D14 FBD_CMD14
AG48 AN51 E45 B49 F18 B24 AG5 V1
<52> FBA_D17 FBA_D17 FBA_CMD17 FBA_CMD18 FBA_CMD17 <52> <53> FBB_D16 FBB_D16 FBB_CMD16 FBB_CMD17 FBB_CMD16 <53> <54> FBC_D16 FBC_D16 FBC_CMD16 FBC_CMD17 FBC_CMD16 <54> FBD_D15 FBD_CMD15
AJ45 AN52 D45 A49 G18 A24 Y6 L3
<52> FBA_D18 FBA_D18 FBA_CMD18 FBA_CMD18 <52> <53> FBB_D17 FBB_D17 FBB_CMD17 FBB_CMD18 FBB_CMD17 <53> <54> FBC_D17 FBC_D17 FBC_CMD17 FBC_CMD18 FBC_CMD17 <54> FBD_D16 FBD_CMD16
AG49 AM49 F45 A48 E18 D23 Y5 L2
<52> FBA_D19 AF46 FBA_D19 FBA_CMD19 AM52 FBA_CMD19 <52> <53> FBB_D18 G45 FBB_D18 FBB_CMD18 D47 FBB_CMD18 <53> <54> FBC_D18 H18 FBC_D18 FBC_CMD18 A23 FBC_CMD18 <54> V5 FBD_D17 FBD_CMD17 L1
<52> FBA_D20 AF47 FBA_D20 FBA_CMD20 AM51 FBA_CMD20 <52> <53> FBB_D19 D42 FBB_D19 FBB_CMD19 A47 FBB_CMD19 <53> <54> FBC_D19 D15 FBC_D19 FBC_CMD19 B23 FBC_CMD19 <54> Y4 FBD_D18 FBD_CMD18 M4
<52> FBA_D21 AF48 FBA_D21 FBA_CMD21 AM50 FBA_CMD21 <52> <53> FBB_D20 E42 FBB_D20 FBB_CMD20 B47 FBB_CMD20 <53> <54> FBC_D20 E15 FBC_D20 FBC_CMD20 C23 FBC_CMD20 <54> AA6 FBD_D19 FBD_CMD19 M1
<52> FBA_D22 AD47 FBA_D22 FBA_CMD22 AK50 FBA_CMD22 <52> <53> FBB_D21 F42 FBB_D21 FBB_CMD21 C47 FBB_CMD21 <53> <54> FBC_D21 G17 FBC_D21 FBC_CMD21 C21 FBC_CMD21 <54> AA5 FBD_D20 FBD_CMD20 M2
<52> FBA_D23 AD49 FBA_D23 FBA_CMD23 AK51 FBA_CMD23 <52> <53> FBB_D22 H41 FBB_D22 FBB_CMD22 C45 FBB_CMD22 <53> <54> FBC_D22 H17 FBC_D22 FBC_CMD22 B21 FBC_CMD22 <54> AC5 FBD_D21 FBD_CMD21 M3
<52> FBA_D24 AD48 FBA_D24 FBA_CMD24 AK52 FBA_CMD24 <52> <53> FBB_D23 E41 FBB_D23 FBB_CMD23 B45 FBB_CMD23 <53> <54> FBC_D23 J15 FBC_D23 FBC_CMD23 A21 FBC_CMD23 <54> AC4 FBD_D22 FBD_CMD22 P3
<52> FBA_D25 AC46 FBA_D25 FBA_CMD25 AJ49 FBA_CMD25 <52> <53> FBB_D24 F39 FBB_D24 FBB_CMD24 A45 FBB_CMD24 <53> <54> FBC_D24 H15 FBC_D24 FBC_CMD24 D20 FBC_CMD24 <54> AD7 FBD_D23 FBD_CMD23 P2
<52> FBA_D26 AC47 FBA_D26 FBA_CMD26 AJ52 FBA_CMD26 <52> <53> FBB_D25 E39 FBB_D25 FBB_CMD25 D44 FBB_CMD25 <53> <54> FBC_D25 E14 FBC_D25 FBC_CMD25 A20 FBC_CMD25 <54> AC6 FBD_D24 FBD_CMD24 P1
<52> FBA_D27 AA47 FBA_D27 FBA_CMD27 AJ51 FBA_CMD27 <52> <53> FBB_D26 D39 FBB_D26 FBB_CMD26 A44 FBB_CMD26 <53> <54> FBC_D26 F14 FBC_D26 FBC_CMD26 B20 FBC_CMD26 <54> AF6 FBD_D25 FBD_CMD25 R4
<52> FBA_D28 AA46 FBA_D28 FBA_CMD28 AJ50 FBA_CMD28 <52> <53> FBB_D27 F38 FBB_D27 FBB_CMD27 B44 FBB_CMD27 <53> <54> FBC_D27 H11 FBC_D27 FBC_CMD27 C20 FBC_CMD27 <54> AD6 FBD_D26 FBD_CMD26 R1
<52> FBA_D29 AA45 FBA_D29 FBA_CMD29 AG50 FBA_CMD29 <52> <53> FBB_D28 E38 FBB_D28 FBB_CMD28 C44 FBB_CMD28 <53> <54> FBC_D28 G11 FBC_D28 FBC_CMD28 C18 FBC_CMD28 <54> AF7 FBD_D27 FBD_CMD27 R2
<52> FBA_D30 Y44 FBA_D30 FBA_CMD30 AG51 FBA_CMD30 <52> <53> FBB_D29 D36 FBB_D29 FBB_CMD29 C42 FBB_CMD29 <53> <54> FBC_D29 F11 FBC_D29 FBC_CMD29 B18 FBC_CMD29 <54> AF8 FBD_D28 FBD_CMD28 R3
<52> FBA_D31 AW51 FBA_D31 FBA_CMD31 AG52 FBA_CMD31 <52> <53> FBB_D30 E36 FBB_D30 FBB_CMD30 B42 FBB_CMD30 <53> <54> FBC_D30 E11 FBC_D30 FBC_CMD30 A18 FBC_CMD30 <54> AF2 FBD_D29 FBD_CMD29 U3
<52> FBA_D32 BA52 FBA_D32 FBA_CMD32 AF49 <53> FBB_D31 M50 FBB_D31 FBB_CMD31 A42 FBB_CMD31 <53> <54> FBC_D31 J29 FBC_D31 FBC_CMD31 D17 FBC_CMD31 <54> AF3 FBD_D30 FBD_CMD30 U2
<52> FBA_D33 AW50 FBA_D33 FBA_CMD33 Y50 <53> FBB_D32 P48 FBB_D32 FBB_CMD32 D41 <54> FBC_D32 F30 FBC_D32 FBC_CMD32 A17 F4 FBD_D31 FBD_CMD31 U1
<52> FBA_D34 BA51 FBA_D34 FBA_CMD34 AR50 <53> FBB_D33 M51 FBB_D33 FBB_CMD33 C35 <54> FBC_D33 H29 FBC_D33 FBC_CMD33 A9 E1 FBD_D32 FBD_CMD32 V4
<52> FBA_D35 BA50 FBA_D35 FBA_CMD35 <53> FBB_D34 M49 FBB_D34 FBB_CMD34 B50 <54> FBC_D34 G30 FBC_D34 FBC_CMD34 C24 F3 FBD_D33 FBD_CMD33 AD3
<52> FBA_D36 BB50 FBA_D36 <53> FBB_D35 P47 FBB_D35 FBB_CMD35 <54> FBC_D35 B30 FBC_D35 FBC_CMD35 F5 FBD_D34 FBD_CMD34 J3
<52> FBA_D37 BA49 FBA_D37 <53> FBB_D36 P52 FBB_D36 <54> FBC_D36 A30 FBC_D36 D2 FBD_D35 FBD_CMD35
<52> FBA_D38 AW49 FBA_D38 AA44 <53> FBB_D37 R46 FBB_D37 <54> FBC_D37 H30 FBC_D37 D1 FBD_D36
<52> FBA_D39 AV48 FBA_D39 FBA_DBG_RFU1 AN44 <53> FBB_D38 P46 FBB_D38 J35 <54> FBC_D38 C30 FBC_D38 J14 C3 FBD_D37
<52> FBA_D40 AT49 FBA_D40 FBA_DBG_RFU2 <53> FBB_D39 L50 FBB_D39 FBB_DBG_RFU1 J41 <54> FBC_D39 D27 FBC_D39 FBC_DBG_RFU1 J23 C2 FBD_D38 AC9
<52> FBA_D41 AT47 FBA_D41 <53> FBB_D40 L51 FBB_D40 FBB_DBG_RFU2 <54> FBC_D40 J26 FBC_D40 FBC_DBG_RFU2 J5 FBD_D39 FBD_DBG_RFU1 P9
<52> FBA_D42 AT48 FBA_D42 <53> FBB_D41 L52 FBB_D41 <54> FBC_D41 F27 FBC_D41 J4 FBD_D40 FBD_DBG_RFU2
C <52> FBA_D43 AT46 FBA_D43 AG45 <53> FBB_D42 L49 FBB_D42 <54> FBC_D42 G27 FBC_D42 L8 FBD_D41 C
<52> FBA_D44 AV51 FBA_D44 FBA_CLK0 AG46 FBA_CLK0 <52> <53> FBB_D43 M46 FBB_D43 H42 <54> FBC_D43 C27 FBC_D43 G15 J2 FBD_D42
<52> FBA_D45 AV52 FBA_D45 FBA_CLK0* AK46 FBA_CLK0# <52> <53> FBB_D44 L47 FBB_D44 FBB_CLK0 G42 FBB_CLK0 <53> <54> FBC_D44 B27 FBC_D44 FBC_CLK0 F15 FBC_CLK0 <54> F1 FBD_D43 Y8
<52> FBA_D46 AV49 FBA_D46 FBA_CLK1 AK45 FBA_CLK1 <52> <53> FBB_D45 M48 FBB_D45 FBB_CLK0* F47 FBB_CLK0# <53> <54> FBC_D45 A27 FBC_D45 FBC_CLK0* H21 FBC_CLK0# <54> F2 FBD_D44 FBD_CLK0 Y7
<52> FBA_D47 AJ48 FBA_D47 FBA_CLK1* FBA_CLK1# <52> <53> FBB_D46 M47 FBB_D46 FBB_CLK1 E47 FBB_CLK1 <53> <54> FBC_D46 G29 FBC_D46 FBC_CLK1 J21 FBC_CLK1 <54> H4 FBD_D45 FBD_CLK0* R8
<52> FBA_D48 AJ46 FBA_D48 <53> FBB_D47 D48 FBB_D47 FBB_CLK1* FBB_CLK1# <53> <54> FBC_D47 H20 FBC_D47 FBC_CLK1* FBC_CLK1# <54> H5 FBD_D46 FBD_CLK1 R7
<52> FBA_D49 AJ47 FBA_D49 <53> FBB_D48 C50 FBB_D48 <54> FBC_D48 D18 FBC_D48 V7 FBD_D47 FBD_CLK1*
<52> FBA_D50 AK49 FBA_D50 <53> FBB_D49 C48 FBB_D49 <54> FBC_D49 G20 FBC_D49 V8 FBD_D48
<52> FBA_D51 AM47 FBA_D51 <53> FBB_D50 C49 FBB_D50 <54> FBC_D50 E20 FBC_D50 V6 FBD_D49
<52> FBA_D52 AM46 FBA_D52 <53> FBB_D51 E49 FBB_D51 <54> FBC_D51 F23 FBC_D51 V9 FBD_D50
<52> FBA_D53 AN48 FBA_D53 <53> FBB_D52 E50 FBB_D52 <54> FBC_D52 E21 FBC_D52 U4 FBD_D51
<52> FBA_D54 AN49 FBA_D54 <53> FBB_D53 F49 FBB_D53 <54> FBC_D53 D21 FBC_D53 R5 FBD_D52
<52> FBA_D55 AM44 FBA_D55 U45 <53> FBB_D54 F48 FBB_D54 <54> FBC_D54 E23 FBC_D54 R6 FBD_D53
<52> FBA_D56 AM45 FBA_D56 FBA_WCK01 U44 FBA_WCK01 <52> <53> FBB_D55 F50 FBB_D55 J33 <54> FBC_D55 G24 FBC_D55 F8 U8 FBD_D54
<52> FBA_D57 AN45 FBA_D57 FBA_WCK01* V45 FBA_WCK01# <52> <53> FBB_D56 D52 FBB_D56 FBB_WCK01 H33 FBB_WCK01 <53> <54> FBC_D56 H26 FBC_D56 FBC_WCK01 G8 FBC_WCK01 <54> P6 FBD_D55 AJ8
<52> FBA_D58 AN46 FBA_D58 FBA_WCKB01 V44 <53> FBB_D57 J50 FBB_D57 FBB_WCK01* G35 FBB_WCK01# <53> <54> FBC_D57 F24 FBC_D57 FBC_WCK01* G9 FBC_WCK01# <54> R9 FBD_D56 FBD_WCK01 AJ7
<52> FBA_D59 AR48 FBA_D59 FBA_WCKB01* AC45 <53> FBB_D58 H48 FBB_D58 FBB_WCKB01 H35 <54> FBC_D58 G26 FBC_D58 FBC_WCKB01 F9 P4 FBD_D57 FBD_WCK01* AG8
<52> FBA_D60 AN47 FBA_D60 FBA_WCK23 AC44 FBA_WCK23 <52> <53> FBB_D59 H51 FBB_D59 FBB_WCKB01* J39 <54> FBC_D59 F26 FBC_D59 FBC_WCKB01* H12 P5 FBD_D58 FBD_WCKB01 AG9
<52> FBA_D61 AR47 FBA_D61 FBA_WCK23* AD46 FBA_WCK23# <52> <53> FBB_D60 J51 FBB_D60 FBB_WCK23 H39 FBB_WCK23 <53> <54> FBC_D60 D26 FBC_D60 FBC_WCK23 G12 FBC_WCK23 <54> L7 FBD_D59 FBD_WCKB01* AD8
<52> FBA_D62 AR46 FBA_D62 FBA_WCKB23 AD45 <53> FBB_D61 H49 FBB_D61 FBB_WCK23* F41 FBB_WCK23# <53> <54> FBC_D61 B26 FBC_D61 FBC_WCK23* G14 FBC_WCK23# <54> L6 FBD_D60 FBD_WCK23 AD9
<52> FBA_D63 FBA_D63 FBA_WCKB23* AV47 <53> FBB_D62 H52 FBB_D62 FBB_WCKB23 G41 <54> FBC_D62 C26 FBC_D62 FBC_WCKB23 H14 L4 FBD_D61 FBD_WCK23* AC7
FBA_WCK45 AV46 FBA_WCK45 <52> <53> FBB_D63 FBB_D63 FBB_WCKB23* L46 <54> FBC_D63 FBC_D63 FBC_WCKB23* J27 L5 FBD_D62 FBD_WCKB23 AC8
U47 FBA_WCK45* AW48 FBA_WCK45# <52> FBB_WCK45 L45 FBB_WCK45 <53> FBC_WCK45 H27 FBC_WCK45 <54> FBD_D63 FBD_WCKB23* J6
<52> FBA_DBI0 Y48 FBA_DQM0 FBA_WCKB45 AW47 C32 FBB_WCK45* M44 FBB_WCK45# <53> A5 FBC_WCK45* E29 FBC_WCK45# <54> FBD_WCK45 J7
<52> FBA_DBI1 AG47 FBA_DQM1 FBA_WCKB45* AR45 <53> FBB_DBI0 E33 FBB_DQM0 FBB_WCKB45 M45 <54> FBC_DBI0 C8 FBC_DQM0 FBC_WCKB45 F29 AJ1 FBD_WCK45* H7
<52> FBA_DBI2 AC48 FBA_DQM2 FBA_WCK67 AR44 FBA_WCK67 <52> <53> FBB_DBI1 E44 FBB_DQM1 FBB_WCKB45* H47 <54> FBC_DBI1 J18 FBC_DQM1 FBC_WCKB45* G23 AG1 FBD_DQM0 FBD_WCKB45 H6
<52> FBA_DBI3 BB51 FBA_DQM3 FBA_WCK67* AT45 FBA_WCK67# <52> <53> FBB_DBI2 G39 FBB_DQM2 FBB_WCK67 H46 FBB_WCK67 <53> <54> FBC_DBI2 F12 FBC_DQM2 FBC_WCK67 H23 FBC_WCK67 <54> AA7 FBD_DQM1 FBD_WCKB45* P8
<52> FBA_DBI4 AV50 FBA_DQM4 FBA_WCKB67 AT44 <53> FBB_DBI3 P49 FBB_DQM3 FBB_WCK67* J47 FBB_WCK67# <53> <54> FBC_DBI3 D29 FBC_DQM3 FBC_WCK67* H24 FBC_WCK67# <54> AD5 FBD_DQM2 FBD_WCK67 P7
<52> FBA_DBI5 AM48 FBA_DQM5 FBA_WCKB67* <53> FBB_DBI4 L48 FBB_DQM4 FBB_WCKB67 J46 <54> FBC_DBI4 E27 FBC_DQM4 FBC_WCKB67 J24 D3 FBD_DQM3 FBD_WCK67* M7
<52> FBA_DBI6 AR49 FBA_DQM6 <53> FBB_DBI5 D50 FBB_DQM5 FBB_WCKB67* <54> FBC_DBI5 F20 FBC_DQM5 FBC_WCKB67* H3 FBD_DQM4 FBD_WCKB67 M8
<52> FBA_DBI7 FBA_DQM7 <53> FBB_DBI6 H50 FBB_DQM6 <54> FBC_DBI6 E26 FBC_DQM6 U5 FBD_DQM5 FBD_WCKB67*
+1V8_MAIN <53> FBB_DBI7 FBB_DQM7 <54> FBC_DBI7 FBC_DQM7 M9 FBD_DQM6
R48 FBD_DQM7
<52> FBA_EDC0 V48 FBA_DQS_WP0 B33 D5
<52> FBA_EDC1 AF44 FBA_DQS_WP1 +FBX_PLLAVDD <53> FBB_EDC0 E35 FBB_DQS_WP0 <54> FBC_EDC0 D8 FBC_DQS_WP0 AJ3
<52> FBA_EDC2 AA48 FBA_DQS_WP2 1 2 <53> FBB_EDC1 G44 FBB_DQS_WP1 +FBX_PLLAVDD <54> FBC_EDC1 E17 FBC_DQS_WP1 +FBX_PLLAVDD AG2 FBD_DQS_WP0
<52> FBA_EDC3 BB52 FBA_DQS_WP3 <53> FBB_EDC2 H38 FBB_DQS_WP2 <54> FBC_EDC2 E12 FBC_DQS_WP2 AA9 FBD_DQS_WP1 +FBX_PLLAVDD
@
<52> FBA_EDC4 AT50 FBA_DQS_WP4 <53> FBB_EDC3 P50 FBB_DQS_WP3 <54> FBC_EDC3 E30 FBC_DQS_WP3 AF4 FBD_DQS_WP2
LG6
<52> FBA_EDC5 AK48 FBA_DQS_WP5 <53> FBB_EDC4 J48 FBB_DQS_WP4 <54> FBC_EDC4 B29 FBC_DQS_WP4 E3 FBD_DQS_WP3
PBY160808T-300Y-N_2P
<52> FBA_EDC6 AR51 FBA_DQS_WP6 AN42 1 2 <53> FBB_EDC5 D51 FBB_DQS_WP5 <54> FBC_EDC5 G21 FBC_DQS_WP5 H2 FBD_DQS_WP4
<52> FBA_EDC7 FBA_DQS_WP7 FBA_PLL_AVDD <53> FBB_EDC6 F51 FBB_DQS_WP6 L38 <54> FBC_EDC6 E24 FBC_DQS_WP6 L17 U6 FBD_DQS_WP5
22U_0805_6.3V6M
0.1U_0402_16V7K

<53> FBB_EDC7 FBB_DQS_WP7 FBB_PLL_AVDD <54> FBC_EDC7 FBC_DQS_WP7 FBC_PLL_AVDD M5 FBD_DQS_WP6 V11
1 1 LG2
W47 PBY160808T-300Y-N_2P FBD_DQS_WP7 FBD_PLL_AVDD
CG54

CG55

GND_694

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
W49 Y17 Y25
GND_695 GND_702 GND_710

0.1U_0402_16V4Z~D
W51 Y18 1 Y26 1 Y33
GND_696 2 2 GND_703 GND_711 GND_0718

CG56

CG57
W6 Y19 Y27 Y34 1
GND_697 GND_704 GND_712 GND_0719

CG58
W8 Y20 Y28 Y35
Y14 GND_698 Y21 GND_705 Y29 GND_713 Y36 GND_0720
Y15 GND_699 Y22 GND_706 2 Y30 GND_714 2 Y37 GND_0721
+FBX_PLLAVDD Y16 GND_700 Y23 GND_707 Y31 GND_715 Y38 GND_0722 2
GND_701 Y24 GND_708 Y32 GND_716 Y39 GND_0723
GND_709 GND_717 Y9 GND_0724
GND_0725
AF42
L29 FB_REFPLL_AVDD0
0.1U_0402_10V7K

0.1U_0402_10V7K

FB_REFPLL_AVDD1 GP10 4 GP10 6


1 1
Under GPU
CG59

CG60

2 2 N17E-G1_BGA2152~D N17E-G1_BGA2152~D
Under GPU N17E-G1_BGA2152~D
Under GPU FBD UNUSED
Under GPU
N17E-G1_BGA2152~D

B +1.35VS_VGA +1.35VS_VGA +1.35VS_VGA B


1

1
RG47 RG48 RG49 RG50 RG51 RG52
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

FBA_CMD1 FBB_CMD1 FBC_CMD1


2

2
FBA_CMD17 FBB_CMD17 FBC_CMD17

FBA_CMD2 FBB_CMD2 FBC_CMD2

FBA_CMD18 FBB_CMD18 FBC_CMD18


1

1
RG53 RG54 RG55 RG56 RG57 RG58
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
2

2
22uF 10uF 4.7uF 1uF 0.1uF

FBx_PLL_AVDD 4

A A

Security Classification Compal Secret Data


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17E-G1(3/6) MEM interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 48 of 80
5 4 3 2 1
5 4 3 2 1

+3V3_SYS

+NVVDD1 +NVVDD1

100P_0402_50V8J~D
1
UG9G +NVVDD2 +NVVDD2
+1.35VS_VGA +1.35VS_VGA

CG61
19/23 VDD_2/2 UG9J

1.8K_0402_1%

1.8K_0402_1%
23/23 VDDS UG9H

1
AP21 BB45 2
20/23 FBVDDQ
VDD_145 VDD_219

RG60

RG61
AP22 BB46 1 2
VDD_146 VDD_220 <69> CSSN_B+ +3V3_SYS

10U_0603_25V6M
AP23 BB47 AP27 AC14 AA10 AT43
AP30 VDD_147 VDD_221 BB48 AP28 VDDS_057 VDDS_001 AC15 AA11 FBVDDQ_01 FBVDDQ_32 K12

CG62
RG59 2
AP31 VDD_148 VDD_222 BC38 AP29 VDDS_058 VDDS_002 AC16 AA42 FBVDDQ_02 FBVDDQ_33 K14 10_0402_1% UG11

2
D
AP32 VDD_149 VDD_223 BC39 AP35 VDDS_059 VDDS_003 AC17 AA43 FBVDDQ_03 FBVDDQ_34 K15 4 16 D
AP33 VDD_150 VDD_224 BC40 AP36 VDDS_060 VDDS_004 AC18 AC10 FBVDDQ_04 FBVDDQ_35 K17 VS VPU
VDD_151 VDD_225 VDDS_061 VDDS_005 FBVDDQ_05 FBVDDQ_36 1

10K_0402_1%
AP34 BC41 AP37 AC24 AC11 K18 RG62
VDD_152 VDD_226 VDDS_062 VDDS_006 FBVDDQ_06 FBVDDQ_37

RG63
AR13 BC45 AP38 AC25 AC42 K20 10_0402_1% VIN1N 11 13
AR40 VDD_153 VDD_227 BC47 AP39 VDDS_063 VDDS_007 AC26 AC43 FBVDDQ_07 FBVDDQ_38 K21 1 2 VIN1P 12 IN-1 TC
VDD_154 VDD_228 VDDS_064 VDDS_008 FBVDDQ_08 FBVDDQ_39 <69> CSSP_B+ IN+1
AT14 BC49 AV14 AC27 AD10 K23 10 RG529
AT15 VDD_155 VDD_229 BD39 AV15 VDDS_065 VDDS_009 AC28 AD11 FBVDDQ_09 FBVDDQ_40 K24 1 2 VIN2N 14 PV 0_0201_5%
VDD_156 VDD_230 VDDS_066 VDDS_010 FBVDDQ_10 FBVDDQ_41 <69> CSSN_NVVDD IN-2

2
G
10U_0603_25V6M
AT16 BD41 AV16 AC29 AD42 K26 VIN2P 15 9 1 2

2
AT17 VDD_157 VDD_231 BD46 AV17 VDDS_067 VDDS_011 AC35 AD43 FBVDDQ_11 FBVDDQ_42 K27 IN+2 Critical

CG63
RG64 2
AT18 VDD_158 VDD_232 BD47 AV18 VDDS_068 VDDS_012 AC36 AF10 FBVDDQ_12 FBVDDQ_43 K29 10_0402_1% 1 8 3 1
VDD_159 VDD_233 VDDS_069 VDDS_013 FBVDDQ_13 FBVDDQ_44 IN-3 Warning GPIO3_OC_WARN# <46>
AT19 BD48 AV24 AC37 AF43 K30 2

D
AT20 VDD_160 VDD_234 BD49 AV25 VDDS_070 VDDS_014 AC38 AG10 FBVDDQ_14 FBVDDQ_45 K32 IN+3 5 2 1
AT21 VDD_161 VDD_235 BD50 AV26 VDDS_071 VDDS_015 AC39 AG11 FBVDDQ_15 FBVDDQ_46 K33 RG66 1 6 A0
AT22 VDD_162 VDD_236 BD51 AV27 VDDS_072 VDDS_016 AF14 AG42 FBVDDQ_16 FBVDDQ_47 K35 <46> I2CC_SCL 7 SCL 3 QG5
10_0402_1% RG65
AT23 VDD_163 VDD_237 BE41 AV28 VDDS_073 VDDS_017 AF15 AG43 FBVDDQ_17 FBVDDQ_48 K36 1 2 <46> I2CC_SDA SDA GND 2N7002W-T/R7_SOT323-3
10K_0402_1%
VDD_164 VDD_238 VDDS_074 VDDS_018 FBVDDQ_18 FBVDDQ_49 <69> CSSP_NVVDD
AT24 BE42 AV29 AF16 AJ10 K38 INA3221AIRGVR_VQFN16_4X4
AT25 VDD_165 VDD_239 BE43 AV35 VDDS_075 VDDS_019 AF17 AJ11 FBVDDQ_19 FBVDDQ_50 K39 1 2 VIN3N
VDD_166 VDD_240 VDDS_076 VDDS_020 FBVDDQ_20 FBVDDQ_51 <70> CSSN_NVVDDS

10U_0603_25V6M
AT26 BE46 AV36 AF18 AJ42 K41
VDD_167 VDD_241 VDDS_077 VDDS_021 FBVDDQ_21 FBVDDQ_52

CG183
AT27 BE47 AV37 AF24 AJ43 L14 RG138 2
AT28 VDD_168 VDD_242 BE48 AV38 VDDS_078 VDDS_022 AF25 AK10 FBVDDQ_22 FBVDDQ_53 L15 10_0402_1%
AT29 VDD_169 VDD_243 BE49 AV39 VDDS_079 VDDS_023 AF26 AK11 FBVDDQ_23 FBVDDQ_54 L18
AT30 VDD_170 VDD_244 BE50 R14 VDDS_080 VDDS_024 AG27 AK42 FBVDDQ_24 FBVDDQ_55 L20
AT31 VDD_171 VDD_245 BE51 R15 VDDS_081 VDDS_025 AG28 AK43 FBVDDQ_25 FBVDDQ_56 L21 RG137 1
AT32 VDD_172 VDD_246 BE52 R16 VDDS_082 VDDS_026 AG29 AM42 FBVDDQ_26 FBVDDQ_57 L23 10_0402_1%
AT33 VDD_173 VDD_247 BF42 R17 VDDS_083 VDDS_027 AG35 AM43 FBVDDQ_27 FBVDDQ_58 L24 1 2 VIN3P
VDD_174 VDD_248 VDDS_084 VDDS_028 FBVDDQ_28 FBVDDQ_59 <70> CSSP_NVVDDS
AT34 BF44 R18 AG36 AN43 L26
AT35 VDD_175 VDD_249 BF45 R24 VDDS_085 VDDS_029 AG37 AR42 FBVDDQ_29 FBVDDQ_60 L27
AT36 VDD_176 VDD_250 BF47 R25 VDDS_086 VDDS_030 AG38 AR43 FBVDDQ_30 FBVDDQ_61 L30
AT37 VDD_177 VDD_251 BF49 R26 VDDS_087 VDDS_031 AG39 R42 FBVDDQ_31 FBVDDQ_62 L32
AT38 VDD_178 VDD_252 BF51 R27 VDDS_088 VDDS_032 AK14 R43 FBVDDQ_76 FBVDDQ_63 L33
AT39 VDD_179 VDD_253 BG43 R28 VDDS_089 VDDS_033 AK15 U10 FBVDDQ_77 FBVDDQ_64 L35
AT42 VDD_180 VDD_254 BG44 R29 VDDS_090 VDDS_034 AK16 U11 FBVDDQ_78 FBVDDQ_65 L36
AU43 VDD_181 VDD_255 U16 R35 VDDS_091 VDDS_035 AK17 U43 FBVDDQ_79 FBVDDQ_66 L39
AV19 VDD_182 VDD_321 U17 R36 VDDS_092 VDDS_036 AK18 V10 FBVDDQ_80 FBVDDQ_67 M10
AV20 VDD_183 VDD_322 U18 R37 VDDS_093 VDDS_037 AK24 V42 FBVDDQ_81 FBVDDQ_68 M43
AV21 VDD_184 VDD_323 U19 R38 VDDS_094 VDDS_038 AK25 V43 FBVDDQ_82 FBVDDQ_69 P10
AV22 VDD_185 VDD_324 U20 R39 VDDS_095 VDDS_039 AK26 Y10 FBVDDQ_83 FBVDDQ_70 P11
C AV23 VDD_186 VDD_325 U21 W14 VDDS_096 VDDS_040 AK27 Y11 FBVDDQ_84 FBVDDQ_71 P42 C
AV30 VDD_187 VDD_326 U22 W15 VDDS_097 VDDS_041 AK28 Y42 FBVDDQ_85 FBVDDQ_72 P43
AV31 VDD_188 VDD_327 U23 W16 VDDS_098 VDDS_042 AK29 Y43 FBVDDQ_86 FBVDDQ_73 R10
VDD_189 VDD_328 VDDS_099 VDDS_043 FBVDDQ_87 FBVDDQ_74

470U_D2E_2VM_R9M
AV32 U24 W17 AK35 R11
VDD_190 VDD_329 VDDS_100 VDDS_044 FBVDDQ_75

10U_0603_6.3V6M
AV33 U25 W18 AK36 1 @
AV34 VDD_191 VDD_330 U26 W24 VDDS_101 VDDS_045 AK37
VDD_192 VDD_331 VDDS_102 VDDS_046 1

CG242

CG243
AV42 U27 W25 AK38 +
AV43 VDD_193 VDD_332 U28 W26 VDDS_103 VDDS_047 AK39
AV44 VDD_194 VDD_333 U29 W27 VDDS_104 VDDS_048 AP14 E52
VDD_195 VDD_334 VDDS_105 VDDS_049 2 2 FBVDDQ_SENSE FB_VDDQ_SENSE <71>
AW13 U30 W28 AP15
AW40 VDD_196 VDD_335 U31 W29 VDDS_106 VDDS_050 AP16
AW42 VDD_197 VDD_336 U32 W35 VDDS_107 VDDS_051 AP17
AW43 VDD_198 VDD_337 U33 W36 VDDS_108 VDDS_052 AP18 P45
AW44 VDD_199 VDD_338 U34 W37 VDDS_109 VDDS_053 AP24 FB_VREF
AW45 VDD_200 VDD_339 U35 W38 VDDS_110 VDDS_054 AP25 +1.35VS_VGA
AY14 VDD_201 VDD_340 U36 W39 VDDS_111 VDDS_055 AP26
AY18 VDD_202 VDD_341 U37 VDDS_112 VDDS_056
AY22 VDD_203 VDD_342 U38
AY26 VDD_204 VDD_343 U39 R44 FBCAL_VDDQ RG67 1 2 40.2_0402_1%
AY27 VDD_205 VDD_344 V13 FB_CAL_PD_VDDQ
AY31 VDD_206 VDD_345 V40 P44 FBCAL_GND RG68 1 2 40.2_0402_1%
AY35 VDD_207 VDD_346 W19 FB_CAL_PU_GND
AY39 VDD_208 VDD_347 W20 BM45 R45 FBCAL_TERM RG69 1 2 60.4_0402_1%
VDD_209 VDD_348 VDDS_SENSE NVVDDS_VCC_SENSE <70> FB_CAL_TERM_GND
AY43 W21 BM44
VDD_210 VDD_349 GNDS_SENSE NVVDDS_VSS_SENSE <70>
AY45 W22
BA43 VDD_211 VDD_350 W23
BA44 VDD_212 VDD_351 W30 N17E-G1_BGA2152~D
BA45 VDD_213 VDD_352 W31 N17E-G1_BGA2152~D
BA46 VDD_214 VDD_353 W32
BA47 VDD_215 VDD_354 W33
BB38 VDD_216 VDD_355 W34
BB39 VDD_217 VDD_356
VDD_218
470U_D2_2VM_R4.5M~D

10U_0603_6.3V6M

1
1
CG244

CG245

B 2 2 B

470uF 22uF 10uF 4.7uF 1uF 0.1uF

BK45
VDD_SENSE BL45 NVVDD_VCC_SENSE <69>
FBVDDQ 1 9 13 24
GND_SENSE NVVDD_VSS_SENSE <69>

N17E-G1_BGA2152~D

Place under GPU


+1.35VS_VGA +1.35VS_VGA
CG184

CG185

CG186

CG187

CG188

CG189

CG190

CG191

CG192

CG193

CG194

CG195

CG196

CG197

CG198

CG199

CG200

CG201

CG202

CG203

CG204

CG205

CG206

CG207

CG208

CG209

CG210

CG211

CG212

CG213

CG214

CG215

CG216

CG217

CG218

CG219

CG220

CG221

CG222

CG223

CG224

CG225

CG226

CG227

CG228
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

A A

Security Classification Compal Secret Data


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17E-G1(4/6) Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 49 of 80
5 4 3 2 1
5 4 3 2 1

UG9K UG9L UG9M


+NVVDD1 +NVVDD1 16/23 GND_1/3 17/23 GND_2/3 22/23 GND_3/3

UG9F A2 AH6 AR20 B52 BL43 N6


A26 GND_001 GND_122 AH8 AR21 GND_238 GND_361 B7 BL5 GND_482 GND_592 N8
18/21 VDD_1/2
A29 GND_002 GND_123 AJ14 AR22 GND_239 GND_362 BA48 BL7 GND_483 GND_593 P14
UG9I +1V8_AON AA14 AG22 A3 GND_003 GND_124 AJ15 AR23 GND_240 GND_363 BB49 BM2 GND_484 GND_594 P15
AA15 VDD_001 VDD_076 AG23 A32 GND_004 GND_125 AJ16 AR24 GND_241 GND_364 BC13 BM3 GND_485 GND_595 P16
21/23 NC/1V8
AA16 VDD_002 VDD_077 AG40 A50 GND_005 GND_126 AJ17 AR25 GND_242 GND_365 BC16 C1 GND_486 GND_596 P17
AT9 BA10 AA17 VDD_003 VDD_078 AH14 A51 GND_006 GND_127 AJ18 AR26 GND_243 GND_366 BC19 C29 GND_487 GND_597 P18
BA6 NC_1 1V8_AON_1 BB14 AA18 VDD_004 VDD_079 AH15 AA49 GND_007 GND_128 AJ19 AR27 GND_244 GND_367 BC2 C33 GND_488 GND_598 P19
BA9 NC_2 1V8_AON_2 BC14 AA19 VDD_005 VDD_080 AH16 AA8 GND_008 GND_129 AJ2 AR28 GND_245 GND_368 BC22 C5 GND_489 GND_599 P20
D
BD14 NC_3 1V8_AON_3 AA20 VDD_006 VDD_081 AH17 AB10 GND_009 GND_130 AJ20 AR29 GND_246 GND_369 BC25 C51 GND_490 GND_600 P21 D
BE12 NC_4 AA21 VDD_007 VDD_082 AH18 AB14 GND_010 GND_131 AJ21 AR30 GND_247 GND_370 BC28 C52 GND_491 GND_601 P22
BG6 NC_5 AA22 VDD_008 VDD_083 AH19 AB15 GND_011 GND_132 AJ22 AR31 GND_248 GND_371 BC31 D10 GND_492 GND_602 P23
BH6 NC_6 AA23 VDD_009 VDD_084 AH20 AB16 GND_012 GND_133 AJ23 AR32 GND_249 GND_372 BC34 D12 GND_493 GND_603 P24
BJ11 NC_7 +1V8_MAIN AA24 VDD_010 VDD_085 AH21 AB17 GND_013 GND_134 AJ24 AR33 GND_250 GND_373 BC37 D13 GND_494 GND_604 P25
BJ9 NC_8 AA25 VDD_011 VDD_086 AH22 AB18 GND_014 GND_135 AJ25 AR34 GND_251 GND_374 BC4 D16 GND_495 GND_605 P26
BK44 NC_9 AA26 VDD_012 VDD_087 AH23 AB19 GND_015 GND_136 AJ26 AR35 GND_252 GND_375 BC51 D19 GND_496 GND_606 P27
NC_10 AM10 AA27 VDD_013 VDD_088 AH24 AB2 GND_016 GND_137 AJ27 AR36 GND_253 GND_376 BC6 D22 GND_497 GND_607 P28
VDD18_01 AM11 AA28 VDD_014 VDD_089 AH25 AB20 GND_017 GND_138 AJ28 AR37 GND_254 GND_377 BC8 D24 GND_498 GND_608 P29
VDD18_02 AN10 AA29 VDD_015 VDD_090 AH26 AB21 GND_018 GND_139 AJ29 AR38 GND_255 GND_378 BD26 D25 GND_499 GND_609 P30
VDD18_03 AN11 AA30 VDD_016 VDD_091 AH27 AB22 GND_019 GND_140 AJ30 AR39 GND_256 GND_379 BD29 D28 GND_500 GND_610 P31
VDD18_04 AR10 AA31 VDD_017 VDD_092 AH28 AB23 GND_020 GND_141 AJ31 AR4 GND_257 GND_380 BD32 D30 GND_501 GND_611 P32
VDD18_05 AR11 AA32 VDD_018 VDD_093 AH29 AB24 GND_021 GND_142 AJ32 AR52 GND_258 GND_381 BD35 D31 GND_502 GND_612 P33
VDD18_06 AT10 AA33 VDD_019 VDD_094 AH30 AB25 GND_022 GND_143 AJ33 AR9 GND_259 GND_382 BD38 D34 GND_503 GND_613 P34
VDD18_07 AT11 AA34 VDD_020 VDD_095 AH31 AB26 GND_023 GND_144 AJ34 AT4 GND_260 GND_383 BD52 D37 GND_504 GND_614 P35
VDD18_08 AV10 AA35 VDD_021 VDD_096 AH32 AB27 GND_024 GND_145 AJ35 AT5 GND_261 GND_384 BE10 D4 GND_505 GND_615 P36
VDD18_09 AV11 AA36 VDD_022 VDD_097 AH33 AB28 GND_025 GND_146 AJ36 AT51 GND_262 GND_385 BE13 D40 GND_506 GND_616 P37
VDD18_10 AW10 AA37 VDD_023 VDD_098 AH34 AB29 GND_026 GND_147 AJ37 AT52 GND_263 GND_386 BE15 D43 GND_507 GND_617 P38
VDD18_11 AW11 AA38 VDD_024 VDD_099 AH35 AB30 GND_027 GND_148 AJ38 AT8 GND_264 GND_387 BE16 D46 GND_508 GND_618 P39
VDD18_12 AA39 VDD_025 VDD_100 AH36 AB31 GND_028 GND_149 AJ39 AU10 GND_265 GND_388 BE18 D49 GND_509 GND_619 P51
AB13 VDD_026 VDD_101 AH37 AB32 GND_029 GND_150 AJ9 AU14 GND_266 GND_389 BE19 D7 GND_510 GND_620 R49
AB40 VDD_027 VDD_102 AH38 AB33 GND_030 GND_151 AK1 AU15 GND_267 GND_390 BE21 E2 GND_511 GND_621 R52
N17E-G1_BGA2152~D AC19 VDD_028 VDD_103 AH39 AB34 GND_031 GND_152 AK44 AU16 GND_268 GND_391 BE22 E4 GND_512 GND_622 T10
AC20 VDD_029 VDD_104 AK19 AB35 GND_032 GND_153 AK47 AU17 GND_269 GND_392 BE24 E48 GND_513 GND_623 T14
AC21 VDD_030 VDD_105 AK20 AB36 GND_033 GND_154 AL10 AU18 GND_270 GND_393 BE25 E5 GND_514 GND_624 T15
AC22 VDD_031 VDD_106 AK21 AB37 GND_034 GND_155 AL14 AU19 GND_271 GND_394 BE27 E51 GND_515 GND_625 T16
AC23 VDD_032 VDD_107 AK22 AB38 GND_035 GND_156 AL15 AU2 GND_272 GND_395 BE28 E8 GND_516 GND_626 T17
AC30 VDD_033 VDD_108 AK23 AB39 GND_036 GND_157 AL16 AU20 GND_273 GND_396 BE30 F10 GND_517 GND_627 T18
AC31 VDD_034 VDD_109 AK30 AB4 GND_037 GND_158 AL17 AU21 GND_274 GND_397 BE31 F13 GND_518 GND_628 T19
AC32 VDD_035 VDD_110 AK31 AB43 GND_038 GND_159 AL18 AU22 GND_275 GND_398 BE33 F16 GND_519 GND_629 T2
AC33 VDD_036 VDD_111 AK32 AB45 GND_039 GND_160 AL19 AU23 GND_276 GND_399 BE34 F17 GND_520 GND_630 T20
AC34 VDD_037 VDD_112 AK33 AB47 GND_040 GND_161 AL2 AU24 GND_277 GND_400 BE36 F19 GND_521 GND_631 T21
AE14 VDD_038 VDD_113 AK34 AB49 GND_041 GND_162 AL20 AU25 GND_278 GND_401 BE37 F21 GND_522 GND_632 T22
AE15 VDD_039 VDD_114 AL13 AB51 GND_042 GND_163 AL21 AU26 GND_279 GND_402 BE39 F22 GND_523 GND_633 T23
AE16 VDD_040 VDD_115 AL40 AB6 GND_043 GND_164 AL22 AU27 GND_280 GND_403 BE40 F25 GND_524 GND_634 T24
AE17 VDD_041 VDD_116 AM14 AB8 GND_044 GND_165 AL23 AU28 GND_281 GND_404 BF2 F28 GND_525 GND_635 T25
AE18 VDD_042 VDD_117 AM15 AD14 GND_045 GND_166 AL24 AU29 GND_282 GND_405 BF4 F31 GND_526 GND_636 T26
AE19 VDD_043 VDD_118 AM16 AD15 GND_046 GND_167 AL25 AU30 GND_283 GND_406 BF41 F34 GND_527 GND_637 T27
C C
AE20 VDD_044 VDD_119 AM17 AD16 GND_047 GND_168 AL26 AU31 GND_284 GND_407 BF6 F35 GND_528 GND_638 T28
AE21 VDD_045 VDD_120 AM18 AD17 GND_048 GND_169 AL27 AU32 GND_285 GND_408 BG10 F37 GND_529 GND_639 T29
+1V8_AON AE22 VDD_046 VDD_121 AM19 AD18 GND_049 GND_170 AL28 AU33 GND_286 GND_409 BG13 F40 GND_530 GND_640 T30
AE23 VDD_047 VDD_122 AM20 AD19 GND_050 GND_171 AL29 AU34 GND_287 GND_410 BG16 F43 GND_531 GND_641 T31
AE24 VDD_048 VDD_123 AM21 AD20 GND_051 GND_172 AL30 AU35 GND_288 GND_411 BG19 F44 GND_532 GND_642 T32
AE25 VDD_049 VDD_124 AM22 AD21 GND_052 GND_173 AL31 AU36 GND_289 GND_412 BG22 F46 GND_533 GND_643 T33
AE26 VDD_050 VDD_125 AM23 AD22 GND_053 GND_174 AL32 AU37 GND_290 GND_413 BG25 F52 GND_534 GND_644 T34
VDD_051 VDD_126 GND_054 GND_175 GND_291 GND_414 GND_535 GND_645
4.7U_0402_6.3V6M

1U_0402_6.3V4Z

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

AE27 AM24 AD23 AL33 AU38 BG28 F7 T35


AE28 VDD_052 VDD_127 AM25 AD24 GND_055 GND_176 AL34 AU39 GND_292 GND_415 BG31 G2 GND_536 GND_646 T36
1 1 1 1 VDD_053 VDD_128 GND_056 GND_177 GND_293 GND_416 GND_537 GND_647
CG291

CG292

CG293

CG294

AE29 AM26 AD25 AL35 AU4 BG34 G38 T37


AE30 VDD_054 VDD_129 AM27 AD26 GND_057 GND_178 AL36 AU45 GND_294 GND_417 BG37 G4 GND_538 GND_648 T38
AE31 VDD_055 VDD_130 AM28 AD27 GND_058 GND_179 AL37 AU47 GND_295 GND_418 BG40 G47 GND_539 GND_649 T39
2 2 2 2 AE32 VDD_056 VDD_131 AM29 AD28 GND_059 GND_180 AL38 AU49 GND_296 GND_419 BG42 G49 GND_540 GND_650 T4
AE33 VDD_057 VDD_132 AM30 AD29 GND_060 GND_181 AL39 AU51 GND_297 GND_420 BG7 G51 GND_541 GND_651 T43
AE34 VDD_058 VDD_133 AM31 AD30 GND_061 GND_182 AL4 AU6 GND_298 GND_421 BH15 G6 GND_542 GND_652 T45
AE35 VDD_059 VDD_134 AM32 AD31 GND_062 GND_183 AL43 AU8 GND_299 GND_422 BH18 H1 GND_543 GND_653 T47
AE36 VDD_060 VDD_135 AM33 AD32 GND_063 GND_184 AL45 AV4 GND_300 GND_423 BH2 H10 GND_544 GND_654 T49
AE37 VDD_061 VDD_136 AM34 AD33 GND_064 GND_185 AL47 AV45 GND_301 GND_424 BH21 H13 GND_545 GND_655 T51
Under GPU AE38
AE39
AF13
VDD_062
VDD_063
VDD_064
VDD_137
VDD_138
VDD_139
AM35
AM36
AM37
AD34
AD35
AD36
GND_065
GND_066
GND_067
GND_186
GND_187
GND_188
AL49
AL51
AL6
AV9
AW14
AW15
GND_302
GND_303
GND_304
GND_425
GND_426
GND_427
BH24
BH27
BH30
H16
H19
H22
GND_546
GND_547
GND_548
GND_656
GND_657
GND_658
T6
T8
U7
AF30 VDD_065 VDD_140 AM38 AD37 GND_068 GND_189 AL8 AW16 GND_305 GND_428 BH33 H25 GND_549 GND_659 U9
AF31 VDD_066 VDD_141 AM39 AD38 GND_069 GND_190 AM4 AW17 GND_306 GND_429 BH36 H28 GND_550 GND_660 V14
AF32 VDD_067 VDD_142 AP19 AD39 GND_070 GND_191 AM9 AW18 GND_307 GND_430 BH39 H31 GND_551 GND_661 V15
AF33 VDD_068 VDD_143 AP20 AD44 GND_071 GND_192 AN14 AW19 GND_308 GND_431 BH42 H34 GND_552 GND_662 V16
AF34 VDD_069 VDD_144 BK52 AE10 GND_072 GND_193 AN15 AW20 GND_309 GND_432 BH5 H37 GND_553 GND_663 V17
AF40 VDD_070 VDD_286 BL46 AE2 GND_073 GND_194 AN16 AW21 GND_310 GND_433 BJ10 H40 GND_554 GND_664 V18
+1V8_MAIN AG13 VDD_071 VDD_287 BL47 AE4 GND_074 GND_195 AN17 AW22 GND_311 GND_434 BJ12 H43 GND_555 GND_665 V19
AG19 VDD_072 VDD_288 BL48 AE43 GND_075 GND_196 AN18 AW23 GND_312 GND_435 BJ13 J1 GND_556 GND_666 V20
AG20 VDD_073 VDD_289 BL49 AE45 GND_076 GND_197 AN19 AW24 GND_313 GND_436 BJ14 J12 GND_557 GND_667 V21
AG21 VDD_074 VDD_290 BL50 AE47 GND_077 GND_198 AN20 AW25 GND_314 GND_437 BJ15 J17 GND_558 GND_668 V22
BG45 VDD_075 VDD_291 BL51 AE49 GND_078 GND_199 AN21 AW26 GND_315 GND_438 BJ16 J20 GND_559 GND_669 V23
VDD_256 VDD_292 GND_079 GND_200 GND_316 GND_439 GND_560 GND_670
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

BG46 BL52 AE51 AN22 AW27 BJ17 J38 V24


BG47 VDD_257 VDD_293 BM47 AE6 GND_080 GND_201 AN23 AW28 GND_317 GND_440 BJ18 J49 GND_561 GND_671 V25
1 1 1 1 1 1 VDD_258 VDD_294 GND_081 GND_202 GND_318 GND_441 GND_562 GND_672
CG295

CG296

CG297

CG298

CG299

CG300

BG48 BM48 AE8 AN24 AW29 BJ19 J52 V26


BG49 VDD_259 VDD_295 BM49 AF1 GND_082 GND_203 AN25 AW30 GND_319 GND_442 BJ20 K13 GND_563 GND_673 V27
BG50 VDD_260 VDD_296 BM50 AF19 GND_083 GND_204 AN26 AW31 GND_320 GND_443 BJ21 K16 GND_564 GND_674 V28
B 2 2 2 2 2 2 BG51 VDD_261 VDD_297 BM51 AF20 GND_084 GND_205 AN27 AW32 GND_321 GND_444 BJ22 K19 GND_565 GND_675 V29 B
BG52 VDD_262 VDD_298 N14 AF21 GND_085 GND_206 AN28 AW33 GND_322 GND_445 BJ23 K2 GND_566 GND_676 V30
BH44 VDD_263 VDD_299 N18 AF22 GND_086 GND_207 AN29 AW34 GND_323 GND_446 BJ24 K22 GND_567 GND_677 V31
BH45 VDD_264 VDD_300 N22 AF23 GND_087 GND_208 AN30 AW35 GND_324 GND_447 BJ25 K25 GND_568 GND_678 V32
BH47 VDD_265 VDD_301 N26 AF27 GND_088 GND_209 AN31 AW36 GND_325 GND_448 BJ26 K28 GND_569 GND_679 V33
BH48 VDD_266 VDD_302 N27 AF28 GND_089 GND_210 AN32 AW37 GND_326 GND_449 BJ27 K31 GND_570 GND_680 V34
BH49 VDD_267 VDD_303 N31 AF29 GND_090 GND_211 AN33 AW38 GND_327 GND_450 BJ28 K34 GND_571 GND_681 V35
BH50 VDD_268 VDD_304 N35 AF35 GND_091 GND_212 AN34 AW39 GND_328 GND_451 BJ29 K37 GND_572 GND_682 V36
BH51 VDD_269 VDD_305 N39 AF36 GND_092 GND_213 AN35 AW4 GND_329 GND_452 BJ30 K4 GND_573 GND_683 V37
BH52 VDD_270 VDD_306 P13 AF37 GND_093 GND_214 AN36 AW46 GND_330 GND_453 BJ31 K40 GND_574 GND_684 V38
BJ44 VDD_271 VDD_307 P40 AF38 GND_094 GND_215 AN37 AW5 GND_331 GND_454 BJ32 K45 GND_575 GND_685 V39
BJ45 VDD_272 VDD_308 R19 AF39 GND_095 GND_216 AN38 AW52 GND_332 GND_455 BJ33 K47 GND_576 GND_686 V49
BJ46 VDD_273 VDD_309 R20 AF45 GND_096 GND_217 AN39 AW8 GND_333 GND_456 BJ34 K49 GND_577 GND_687 V52
+1V8_MAIN BJ47 VDD_274 VDD_310 R21 AF5 GND_097 GND_218 AN4 AY10 GND_334 GND_457 BJ35 K51 GND_578 GND_688 W10
BJ48 VDD_275 VDD_311 R22 AG14 GND_098 GND_219 AN5 AY2 GND_335 GND_458 BJ36 K6 GND_579 GND_689 W2
BJ49 VDD_276 VDD_312 R23 AG15 GND_099 GND_220 AN8 AY4 GND_336 GND_459 BJ37 K8 GND_580 GND_690 W4
BJ50 VDD_277 VDD_313 R30 AG16 GND_100 GND_221 AP10 AY47 GND_337 GND_460 BJ38 M52 GND_581 GND_691 W43
BJ51 VDD_278 VDD_314 R31 AG17 GND_101 GND_222 AP2 AY49 GND_338 GND_461 BJ39 M6 GND_582 GND_692 W45
VDD_279 VDD_315 GND_102 GND_223 GND_339 GND_462 GND_583 GND_693
0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

BJ52 R32 AG18 AP4 AY51 BJ40 N10


BK47 VDD_280 VDD_316 R33 AG24 GND_103 GND_224 AP43 AY6 GND_340 GND_463 BJ41 N2 GND_584
1 1 1 1 1 1 1 VDD_281 VDD_317 GND_104 GND_225 GND_341 GND_464 GND_585
CG301

CG302

CG303

CG304

CG305

CG306

CG307

BK48 R34 AG25 AP45 AY8 BJ42 N4


BK49 VDD_282 VDD_318 U14 AG26 GND_105 GND_226 AP47 B1 GND_342 GND_465 BJ43 N43 GND_586
BK50 VDD_283 VDD_319 U15 AG3 GND_106 GND_227 AP49 B10 GND_343 GND_466 BJ7 N45 GND_587
2 2 2 2 2 2 2 BK51 VDD_284 VDD_320 AG30 GND_107 GND_228 AP51 B13 GND_344 GND_467 BK1 N47 GND_588
VDD_285 AG31 GND_108 GND_229 AP6 B16 GND_345 GND_468 BL1 N49 GND_589
AG32 GND_109 GND_230 AP8 B19 GND_346 GND_469 BL10 N51 GND_590
AG33 GND_110 GND_231 AR14 B2 GND_347 GND_470 BL13 BL40 GND_591
N17E-G1_BGA2152~D AG34 GND_111 GND_232 AR15 B22 GND_348 GND_471 BL16 GND_481
AG44 GND_112 GND_233 AR16 B25 GND_349 GND_472 BL19
AH10 GND_113 GND_234 AR17 B28 GND_350 GND_473 BL2 N17E-G1_BGA2152~D
AH2 GND_114 GND_235 AR18 B31 GND_351 GND_474 BL22
AH4 GND_115 GND_236 AR19 B34 GND_352 GND_475 BL25
AH43 GND_116 GND_237 BL37 B37 GND_353 GND_476 BL28
Under GPU AH45
AH47
AH49
GND_117
GND_118
GND_119
GND_480
GND_H
GND_F
BD24
BC24
B40
B43
B46
GND_354
GND_355
GND_356
GND_477
GND_478
GND_479
BL31
BL34
B5
AH51 GND_120 B48 GND_357 GND_359 B51
GND_121 GND_358 GND_360
A A

N17E-G1_BGA2152~D N17E-G1_BGA2152~D

Security Classification Compal Secret Data


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17E-G1(5/6) Power,GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 50 of 80
5 4 3 2 1
5 4 3 2 1

+1V8_AON

+1V8_AON

2
UG9T
47uF 22uF 10uF 4.7uF 1uF 0.1uF @ @ @ @ @ 15/23 MISC 2 @ @ @
D D
RG78 RG79 RG80 RG81 RG82 RG83 RG84 RG85 RG86
100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% BJ4 ROM_CS# 10K_0402_1% 10K_0402_1% 10K_0402_1%
ROM_CS*
VID_PLLVDD 1 1 1

1
BK2 ROM_SI
ROM_SI BK4 ROM_SO
STRAP0 BL3 ROM_SO BK3 ROM_SCLK
STRAP1 BL4 STRAP0 ROM_SCLK
SP_PLLVDD 1 6 STRAP2 BM4 STRAP1
STRAP2
STRAP3 BM5
GPCPLL_AVDD STRAP3

2
STRAP4 BK5
STRAP5 BJ5 STRAP4
STRAP5 RG87 RG88 RG89
10K_0402_1% 10K_0402_1% 10K_0402_1%

2
@

1
@ BF9 GPU_BUFRST# T6
RG90 RG91 RG92 RG93 RG94 RG95 BUFRST* PAD~D
100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1%

1
N17E-G1_BGA2152~D

+3V_PCH +3V_PCH
+3VS +3VS
1

1
RG558 RG559
10K_0201_1% 10K_0201_1% 1 1
CG437 CG436
C 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D C
2

2
1 2 STRAP3 1 2 STRAP5
<16> STRAP3_PCH <16> STRAP5_PCH 2 2
UG16
12 9
DG8 DG9 VDD VCC
RB751S40T1G_SOD523-2 RB751S40T1G_SOD523-2 ROM_CS# 1 10
COM1 IN1 VROM_SEL <20> Funct i on VROM_SEL
ROM_SO 4 7
COM2 IN2 COM = NC L
IGPU_ROM_CS# 2 11 DGPU_ROM_CS# RG538 1 @ 2 0_0201_5% ROM_CS#
NC1 NO1 COM = NO H
IGPU_ROM_SO 5 8 DGPU_ROM_SO RG539 1 @ 2 0_0201_5% ROM_SO
NC2 NO2
6 3
GND GND
PI5A3158BZAEX_TDFN12_1X3
UG9S
14/23 XTAL/PLL
+1V8_MAIN
Under GPU BD12
SP_PLLVDD
1 2 BC12
VID_PLLVDD
47U_0805_6.3V6M~D

10U_0603_6.3V6M

0.1U_0402_10V7K

LG4 +1V8_AON
1 1
1

CG232

CG231

CG230

PBY160808T-301Y-N
+1V8_AON
2

2 2

1
1
+1V8_MAIN RG74 CG66
U42 10K_0402_5% 0.1U_0402_16V4Z~D
GPCPLL_AVDD0

2
1 2 AF11 UG13 2
GPCPLL_AVDD1 DGPU_ROM_CS#
22U_0805_6.3VAM

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1 8 RG75
LG3 BB24 DGPU_ROM_SO 1 2 DGPU_ROM_SO_R 2 CS# VCC 7 33_0402_5%~D
1 1 1 1 1 1 1 XS_PLLVDD DO(IO1) HOLD#(IO3) DGPU_ROM_SCLK ROM_SCLK
CG239

CG238

CG237

CG236

CG235

CG234

CG233

PBY160808T-300Y-N_2P 3 6 1 2
RG76 4 WP#(IO2) CLK 5 DGPU_ROM_SI 1 2 ROM_SI
B
33_0402_5%~D GND DI(IO0) B
2 2 2 2 2 2 2 W25Q80EWSSIG_SO8 RG77
33_0402_5%~D

BJ6 BK6 XTALOUTBUFF_R


DGPU VBIOS ROM
Under GPU BL6
XTAL_SSIN

XTAL_IN
XTAL_OUTBUFF

XTAL_OUT
BM6
1

RG98
1

N17E-G1_BGA2152~D 100K_0402_5%~D
RG101 +1V8_AON
10K_0402_5% RG99
2

10M_0402_5% +1V8_AON
1 2
2

YG1

1
1
XTALIN 1 3 XTALOUT RG147 CG241
1 3 10K_0402_5% 0.1U_0402_16V4Z~D
GND GND

2
CG75 CG76 UG15 2
22P_0402_50V8J 2 4 22P_0402_50V8J IGPU_ROM_CS# 1 8 RG148
IGPU_ROM_SO 1 2 IGPU_ROM_SO_R 2 CS# VCC 7 33_0402_5%~D
3 DO(IO1) HOLD#(IO3) 6 IGPU_ROM_SCLK 1 2 ROM_SCLK
27MHZ 16PF +-30PPM 7M27070004F50Q5 RG146 4 WP#(IO2) CLK 5 IGPU_ROM_SI 1 2 ROM_SI
33_0402_5%~D GND DI(IO0)
W25Q80EWSSIG_SO8 RG149
33_0402_5%~D
N17E VRAM Strap0 Strap1 Strap2 Strap3 Strap4 Strap5 RAMCFG
SAMSUNG , K4G80325FB-HC25 L L L H L L 0 Opt i mus VBI OS R O M
MICRON , MT51J256M32HF-80:A H L L H L L 1
A HYNIX , H5GQ8H24MJR-R4C L H L H L L 2 A

N17P VRAM Strap0 Strap1 Strap2 Strap3 Strap4 Strap5 RAMCFG


SAMSUNG , K4G80325FB-HC28 L L L H L L 0
MICRON , MT51J256M32HF-70:A H L L H L L 1
HYNIX , H5GC8H24MJR-R0C L H L H L L 2 Security Classification Compal Secret Data
SAMSUNG , K4G41325FE-HC28 H H H H L L 7 Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

HYNIX , H5GC4H24AJR-R0C L H H H L L 6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17E-G1(6/6) strap pin,ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Monday, September 26, 2016 Sheet 51 of 80
5 4 3 2 1
5 4 3 2 1

UG1 MF=1 UG2 MF=0


MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 A4
DQ24 DQ0 FBA_D24 <48> DQ24 DQ0 FBA_D32 <48>
C2 A2 C2 A2
<48> FBA_EDC3 EDC0 EDC3 DQ25 DQ1 FBA_D25 <48> <48> FBA_EDC4 EDC0 EDC3 DQ25 DQ1 FBA_D33 <48>
C13 B4 C13 B4
<48> FBA_EDC2 EDC1 EDC2 DQ26 DQ2 FBA_D26 <48> <48> FBA_EDC5 EDC1 EDC2 DQ26 DQ2 FBA_D34 <48>
R13 B2 R13 B2
<48> FBA_EDC1 EDC2 EDC1 DQ27 DQ3 FBA_D27 <48> <48> FBA_EDC6 EDC2 EDC1 DQ27 DQ3 FBA_D35 <48>
R2 E4 R2 E4
<48> FBA_EDC0 EDC3 EDC0 DQ28 DQ4 FBA_D28 <48> <48> FBA_EDC7 EDC3 EDC0 DQ28 DQ4 FBA_D36 <48>
E2 E2
DQ29 DQ5 FBA_D29 <48> DQ29 DQ5 FBA_D37 <48>
F4 F4
DQ30 DQ6 FBA_D30 <48> DQ30 DQ6 FBA_D38 <48>
D
D2 F2 D2 F2 D
<48> FBA_DBI3 DBI0# DBI3# DQ31 DQ7 FBA_D31 <48> <48> FBA_DBI4 DBI0# DBI3# DQ31 DQ7 FBA_D39 <48>
D13 A11 D13 A11
<48> FBA_DBI2 DBI1# DBI2# DQ16 DQ8 FBA_D16 <48> <48> FBA_DBI5 DBI1# DBI2# DQ16 DQ8 FBA_D40 <48>
P13 A13 P13 A13
<48> FBA_DBI1 DBI2# DBI1# DQ17 DQ9 FBA_D17 <48> <48> FBA_DBI6 DBI2# DBI1# DQ17 DQ9 FBA_D41 <48>
P2 B11 P2 B11
<48> FBA_DBI0 DBI3# DBI0# DQ18 DQ10 FBA_D18 <48> <48> FBA_DBI7 DBI3# DBI0# DQ18 DQ10 FBA_D42 <48>
B13 B13
DQ19 DQ11 FBA_D19 <48> DQ19 DQ11 FBA_D43 <48>
J12 E11 J12 E11
<48> FBA_CLK0 CK DQ20 DQ12 FBA_D20 <48> <48> FBA_CLK1 CK DQ20 DQ12 FBA_D44 <48>
J11 E13 J11 E13
<48> FBA_CLK0# CK# DQ21 DQ13 FBA_D21 <48> <48> FBA_CLK1# CK# DQ21 DQ13 FBA_D45 <48>
J3 F11 J3 F11
<48> FBA_CMD1 CKE# DQ22 DQ14 FBA_D22 <48> <48> FBA_CMD17 CKE# DQ22 DQ14 FBA_D46 <48>
F13 F13
DQ23 DQ15 FBA_D23 <48> DQ23 DQ15 FBA_D47 <48>
U11 U11
DQ8 DQ16 FBA_D8 <48> DQ8 DQ16 FBA_D48 <48>

1
40.2_0402_1%

40.2_0402_1%

40.2_0402_1%

40.2_0402_1%
H11 U13 H11 U13
<48> FBA_CMD12 BA0/A2 BA2/A4 DQ9 DQ17 FBA_D9 <48> <48> FBA_CMD29 BA0/A2 BA2/A4 DQ9 DQ17 FBA_D49 <48>

RG523

RG102

RG524

RG103
K10 T11 K10 T11
<48> FBA_CMD14 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D10 <48> <48> FBA_CMD27 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D50 <48>
K11 T13 K11 T13
<48> FBA_CMD13 BA2/A4 BA0/A2 DQ11 DQ19 FBA_D11 <48> <48> FBA_CMD28 BA2/A4 BA0/A2 DQ11 DQ19 FBA_D51 <48>
H10 N11 H10 N11
<48> FBA_CMD11 BA3/A3 BA1/A5 DQ12 DQ20 FBA_D12 <48> <48> FBA_CMD30 BA3/A3 BA1/A5 DQ12 DQ20 FBA_D52 <48>
N13 N13
FBA_D13 <48> FBA_D53 <48>

2
DQ13 DQ21 M11 DQ13 DQ21 M11
DQ14 DQ22 FBA_D14 <48> DQ14 DQ22 FBA_D54 <48>
K4 M13 K4 M13
<48> FBA_CMD5 A8/A7 A10/A0 DQ15 DQ23 FBA_D15 <48> <48> FBA_CMD25 A8/A7 A10/A0 DQ15 DQ23 FBA_D55 <48>
H5 U4 H5 U4
<48> FBA_CMD8 A9/A1 A11/A6 DQ0 DQ24 FBA_D0 <48> <48> FBA_CMD20 A9/A1 A11/A6 DQ0 DQ24 FBA_D56 <48>

0.01U_0402_16V7K

0.01U_0402_16V7K
1 H4 U2 1 H4 U2
<48> FBA_CMD9 A10/A0 A8/A7 DQ1 DQ25 FBA_D1 <48> <48> FBA_CMD21 A10/A0 A8/A7 DQ1 DQ25 FBA_D57 <48>

CG313

CG314
K5 T4 K5 T4
<48> FBA_CMD4 A11/A6 A9/A1 DQ2 DQ26 FBA_D2 <48> <48> FBA_CMD24 A11/A6 A9/A1 DQ2 DQ26 FBA_D58 <48>
J5 T2 J5 T2
<48> FBA_CMD6 A12/RFU/NC DQ3 DQ27 FBA_D3 <48> <48> FBA_CMD22 A12/RFU/NC DQ3 DQ27 FBA_D59 <48>
N4 N4
2 DQ4 DQ28 FBA_D4 <48> 2 DQ4 DQ28 FBA_D60 <48>
A5 N2 A5 N2
+1.35VS_VGA VPP/NC DQ5 DQ29 FBA_D5 <48> VPP/NC DQ5 DQ29 FBA_D61 <48>
U5 M4 U5 M4
VPP/NC DQ6 DQ30 FBA_D6 <48> VPP/NC DQ6 DQ30 FBA_D62 <48>
M2 M2
DQ7 DQ31 FBA_D7 <48> DQ7 DQ31 FBA_D63 <48>
RG104 2 1 1K_0402_1% J1 +1.35VS_VGA RG105 2 1 1K_0402_1% J1 +1.35VS_VGA
RG106 2 1 1K_0402_1% J10 MF RG107 2 1 1K_0402_1% J10 MF
RG108 2 1 121_0402_1% J13 SEN B1 RG109 2 1 121_0402_1% J13 SEN B1
ZQ VDDQ D1 ZQ VDDQ D1
VDDQ F1 VDDQ F1
J4 VDDQ M1 J4 VDDQ M1
<48> FBA_CMD7 ABI# VDDQ <48> FBA_CMD23 ABI# VDDQ
G3 P1 G3 P1
<48> FBA_CMD0 RAS# CAS# VDDQ <48> FBA_CMD19 RAS# CAS# VDDQ
G12 T1 G12 T1
+1.35VS_VGA
GDDR5_A <48>
<48>
<48>
FBA_CMD10
FBA_CMD3
FBA_CMD15
L3
L12
CS#
CAS#
WE#
WE#
RAS#
CS#
VDDQ
VDDQ
VDDQ
G2
L2
B3
<48>
<48>
<48>
FBA_CMD31
FBA_CMD16
FBA_CMD26
L3
L12
CS#
CAS#
WE#
WE#
RAS#
CS#
VDDQ
VDDQ
VDDQ
G2
L2
B3
VDDQ D3 VDDQ D3
C VDDQ VDDQ C
F3 F3
D5 VDDQ H3 D5 VDDQ H3
CG388

CG389

CG390

CG391

CG392

CG393

CG394

CG395

CG396

CG397

CG398

CG399

CG400

CG401

CG402

CG403

<48> FBA_WCK23# WCK01# WCK23# VDDQ <48> FBA_WCK45# WCK01# WCK23# VDDQ
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 K3 D4 K3
<48> FBA_WCK23 WCK01 WCK23 VDDQ <48> FBA_WCK45 WCK01 WCK23 VDDQ
M3 M3
P5 VDDQ P3 P5 VDDQ P3
<48> FBA_WCK01# WCK23# WCK01# VDDQ <48> FBA_WCK67# WCK23# WCK01# VDDQ
P4 T3 P4 T3
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 <48> FBA_WCK01 WCK23 WCK01 VDDQ <48> FBA_WCK67 WCK23 WCK01 VDDQ
E5 E5
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

VDDQ N5 VDDQ N5
A10 VDDQ E10 A10 VDDQ E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FBA_VREFC J14 VREFD VDDQ B12 +FBA_VREFC J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
VDDQ H12 VDDQ H12
J2 VDDQ K12 J2 VDDQ K12
<48> FBA_CMD2 RESET# VDDQ <48> FBA_CMD18 RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
K1 VSS VDDQ B14 K1 VSS VDDQ B14
B5 VSS VDDQ D14 B5 VSS VDDQ D14
G5 VSS VDDQ F14 +1.35VS_VGA G5 VSS VDDQ F14
L5 VSS VDDQ M14 L5 VSS VDDQ M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
B10 VSS VDDQ T14 B10 VSS VDDQ T14
+1.35VS_VGA D10 VSS VDDQ D10 VSS VDDQ

CG324

CG325

CG326

CG327

CG328

CG329

CG330

CG331

CG332

CG333
G10 VSS G10 VSS
VSS 1 1 1 1 1 1 1 1 1 1 VSS
L10 A1 L10 A1
VSS VSSQ VSS VSSQ
1

P10 C1 P10 C1
RG110 T10 VSS VSSQ E1 T10 VSS VSSQ E1
549_0402_1% H14 VSS VSSQ N1 2 2 2 2 2 2 2 2 2 2 H14 VSS VSSQ N1

22U_0603_6.3V6M

10U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
+1.35VS_VGA K14 VSS VSSQ R1 K14 VSS VSSQ R1
VSS VSSQ U1 +1.35VS_VGA VSS VSSQ U1
2

VSSQ H2 VSSQ H2
1 2 +FBA_VREFC W=16mils G1
VDD
VSSQ
VSSQ
K2 G1
VDD
VSSQ
VSSQ
K2
B
L1 A3 L1 A3 B
VDD VSSQ VDD VSSQ
1

RG111 G4 C3 G4 C3
RG112

CG78

CG79
820P_0402_25V7

820P_0402_25V7
1.33K_0402_1%

1 1 VDD VSSQ VDD VSSQ


931_0402_1% L4 E3 L4 E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
2 2 C10 VDD VSSQ U3 C10 VDD VSSQ U3
2

VDD VSSQ VDD VSSQ


1

D R10 C4 R10 C4
2 QG2 D11 VDD VSSQ R4 D11 VDD VSSQ R4
<46,53,54> MEM_VREF VDD VSSQ VDD VSSQ
G MESS138W-G_SOT323-3 G11 F5 G11 F5
S L11 VDD VSSQ M5 L11 VDD VSSQ M5
3

P11 VDD VSSQ F10 P11 VDD VSSQ F10


G14 VDD VSSQ M10 +1.35VS_VGA G14 VDD VSSQ M10
L14 VDD VSSQ C11 L14 VDD VSSQ C11
VDD VSSQ R11 VDD VSSQ R11
VSSQ A12 VSSQ A12
VSSQ C12 VSSQ C12

CG334

CG335

CG336

CG337

CG338

CG339

CG340

CG341

CG342

CG343
VSSQ E12 VSSQ E12
VSSQ 1 1 1 1 1 1 1 1 1 1 VSSQ
N12 N12
VSSQ R12 VSSQ R12
170-BALL VSSQ U12 170-BALL VSSQ U12
VSSQ H13 2 2 2 2 2 2 2 2 2 2 VSSQ H13

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
X76@ X76@

+1.35VS_VGA
Under VRAM +1.35VS_VGA
CG80

CG81

CG82

CG83

CG84

CG85

CG86

CG87

CG88

CG89

CG90

CG91

CG97

CG98

CG99

CG100

CG101

CG102

CG103

CG104

CG105

CG106

A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A

22uF 10uF 1uF


2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
10U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

VDD/VDDQ 10 12 36

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GDDR5_A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 52 of 80
5 4 3 2 1
5 4 3 2 1

UG3 MF=1 UG4 MF=0


MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 A4
DQ24 DQ0 FBB_D24 <48> DQ24 DQ0 FBB_D32 <48>
C2 A2 C2 A2
<48> FBB_EDC3 EDC0 EDC3 DQ25 DQ1 FBB_D25 <48> <48> FBB_EDC4 EDC0 EDC3 DQ25 DQ1 FBB_D33 <48>
C13 B4 C13 B4
<48> FBB_EDC2 EDC1 EDC2 DQ26 DQ2 FBB_D26 <48> <48> FBB_EDC5 EDC1 EDC2 DQ26 DQ2 FBB_D34 <48>
R13 B2 R13 B2
<48> FBB_EDC1 EDC2 EDC1 DQ27 DQ3 FBB_D27 <48> <48> FBB_EDC6 EDC2 EDC1 DQ27 DQ3 FBB_D35 <48>
R2 E4 R2 E4
<48> FBB_EDC0 EDC3 EDC0 DQ28 DQ4 FBB_D28 <48> <48> FBB_EDC7 EDC3 EDC0 DQ28 DQ4 FBB_D36 <48>
E2 E2
DQ29 DQ5 FBB_D29 <48> DQ29 DQ5 FBB_D37 <48>
F4 F4
DQ30 DQ6 FBB_D30 <48> DQ30 DQ6 FBB_D38 <48>
D
D2 F2 D2 F2 D
<48> FBB_DBI3 DBI0# DBI3# DQ31 DQ7 FBB_D31 <48> <48> FBB_DBI4 DBI0# DBI3# DQ31 DQ7 FBB_D39 <48>
D13 A11 D13 A11
<48> FBB_DBI2 DBI1# DBI2# DQ16 DQ8 FBB_D16 <48> <48> FBB_DBI5 DBI1# DBI2# DQ16 DQ8 FBB_D40 <48>
P13 A13 P13 A13
<48> FBB_DBI1 DBI2# DBI1# DQ17 DQ9 FBB_D17 <48> <48> FBB_DBI6 DBI2# DBI1# DQ17 DQ9 FBB_D41 <48>
P2 B11 P2 B11
<48> FBB_DBI0 DBI3# DBI0# DQ18 DQ10 FBB_D18 <48> <48> FBB_DBI7 DBI3# DBI0# DQ18 DQ10 FBB_D42 <48>
B13 B13
DQ19 DQ11 FBB_D19 <48> DQ19 DQ11 FBB_D43 <48>
J12 E11 J12 E11
<48> FBB_CLK0 CK DQ20 DQ12 FBB_D20 <48> <48> FBB_CLK1 CK DQ20 DQ12 FBB_D44 <48>
J11 E13 J11 E13
<48> FBB_CLK0# CK# DQ21 DQ13 FBB_D21 <48> <48> FBB_CLK1# CK# DQ21 DQ13 FBB_D45 <48>
J3 F11 J3 F11
<48> FBB_CMD1 CKE# DQ22 DQ14 FBB_D22 <48> <48> FBB_CMD17 CKE# DQ22 DQ14 FBB_D46 <48>
F13 F13
DQ23 DQ15 FBB_D23 <48> DQ23 DQ15 FBB_D47 <48>
U11 U11
DQ8 DQ16 FBB_D8 <48> DQ8 DQ16 FBB_D48 <48>

1
40.2_0402_1%

40.2_0402_1%

40.2_0402_1%

40.2_0402_1%
H11 U13 H11 U13
<48> FBB_CMD12 BA0/A2 BA2/A4 DQ9 DQ17 FBB_D9 <48> <48> FBB_CMD29 BA0/A2 BA2/A4 DQ9 DQ17 FBB_D49 <48>

RG525

RG113

RG526

RG114
K10 T11 K10 T11
<48> FBB_CMD14 BA1/A5 BA3/A3 DQ10 DQ18 FBB_D10 <48> <48> FBB_CMD27 BA1/A5 BA3/A3 DQ10 DQ18 FBB_D50 <48>
K11 T13 K11 T13
<48> FBB_CMD13 BA2/A4 BA0/A2 DQ11 DQ19 FBB_D11 <48> <48> FBB_CMD28 BA2/A4 BA0/A2 DQ11 DQ19 FBB_D51 <48>
H10 N11 H10 N11
<48> FBB_CMD11 BA3/A3 BA1/A5 DQ12 DQ20 FBB_D12 <48> <48> FBB_CMD30 BA3/A3 BA1/A5 DQ12 DQ20 FBB_D52 <48>
N13 N13
FBB_D13 <48> FBB_D53 <48>

2
DQ13 DQ21 M11 DQ13 DQ21 M11
DQ14 DQ22 FBB_D14 <48> DQ14 DQ22 FBB_D54 <48>
K4 M13 K4 M13
<48> FBB_CMD5 A8/A7 A10/A0 DQ15 DQ23 FBB_D15 <48> <48> FBB_CMD25 A8/A7 A10/A0 DQ15 DQ23 FBB_D55 <48>
H5 U4 H5 U4
<48> FBB_CMD8 A9/A1 A11/A6 DQ0 DQ24 FBB_D0 <48> <48> FBB_CMD20 A9/A1 A11/A6 DQ0 DQ24 FBB_D56 <48>

0.01U_0402_16V7K

0.01U_0402_16V7K
1 H4 U2 1 H4 U2
<48> FBB_CMD9 A10/A0 A8/A7 DQ1 DQ25 FBB_D1 <48> <48> FBB_CMD21 A10/A0 A8/A7 DQ1 DQ25 FBB_D57 <48>

CG315

CG316
K5 T4 K5 T4
<48> FBB_CMD4 A11/A6 A9/A1 DQ2 DQ26 FBB_D2 <48> <48> FBB_CMD24 A11/A6 A9/A1 DQ2 DQ26 FBB_D58 <48>
J5 T2 J5 T2
<48> FBB_CMD6 A12/RFU/NC DQ3 DQ27 FBB_D3 <48> <48> FBB_CMD22 A12/RFU/NC DQ3 DQ27 FBB_D59 <48>
N4 N4
2 DQ4 DQ28 FBB_D4 <48> 2 DQ4 DQ28 FBB_D60 <48>
A5 N2 A5 N2
+1.35VS_VGA VPP/NC DQ5 DQ29 FBB_D5 <48> VPP/NC DQ5 DQ29 FBB_D61 <48>
U5 M4 U5 M4
VPP/NC DQ6 DQ30 FBB_D6 <48> VPP/NC DQ6 DQ30 FBB_D62 <48>
M2 M2
DQ7 DQ31 FBB_D7 <48> DQ7 DQ31 FBB_D63 <48>
RG115 2 1 1K_0402_1% J1 +1.35VS_VGA RG116 2 1 1K_0402_1% J1 +1.35VS_VGA
RG117 2 1 1K_0402_1% J10 MF RG118 2 1 1K_0402_1% J10 MF
RG119 2 1 121_0402_1% J13 SEN B1 RG120 2 1 121_0402_1% J13 SEN B1
ZQ VDDQ D1 ZQ VDDQ D1
VDDQ F1 VDDQ F1
J4 VDDQ M1 J4 VDDQ M1
<48> FBB_CMD7 ABI# VDDQ <48> FBB_CMD23 ABI# VDDQ
G3 P1 G3 P1
<48> FBB_CMD0 RAS# CAS# VDDQ <48> FBB_CMD19 RAS# CAS# VDDQ
G12 T1 G12 T1
+1.35VS_VGA
GDDR5_B <48>
<48>
<48>
FBB_CMD10
FBB_CMD3
FBB_CMD15
L3
L12
CS#
CAS#
WE#
WE#
RAS#
CS#
VDDQ
VDDQ
VDDQ
G2
L2
B3
<48>
<48>
<48>
FBB_CMD31
FBB_CMD16
FBB_CMD26
L3
L12
CS#
CAS#
WE#
WE#
RAS#
CS#
VDDQ
VDDQ
VDDQ
G2
L2
B3
VDDQ D3 VDDQ D3
C VDDQ VDDQ C
F3 F3
D5 VDDQ H3 D5 VDDQ H3
CG404

CG405

CG406

CG407

CG408

CG409

CG410

CG411

CG412

CG413

CG414

CG415

CG416

CG417

CG418

CG419

<48> FBB_WCK23# WCK01# WCK23# VDDQ <48> FBB_WCK45# WCK01# WCK23# VDDQ
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 K3 D4 K3
<48> FBB_WCK23 WCK01 WCK23 VDDQ <48> FBB_WCK45 WCK01 WCK23 VDDQ
M3 M3
P5 VDDQ P3 P5 VDDQ P3
<48> FBB_WCK01# WCK23# WCK01# VDDQ <48> FBB_WCK67# WCK23# WCK01# VDDQ
P4 T3 P4 T3
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 <48> FBB_WCK01 WCK23 WCK01 VDDQ <48> FBB_WCK67 WCK23 WCK01 VDDQ
E5 E5
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

VDDQ N5 VDDQ N5
A10 VDDQ E10 A10 VDDQ E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FBB_VREFC J14 VREFD VDDQ B12 +FBB_VREFC J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
VDDQ H12 VDDQ H12
J2 VDDQ K12 J2 VDDQ K12
<48> FBB_CMD2 RESET# VDDQ <48> FBB_CMD18 RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
K1 VSS VDDQ B14 K1 VSS VDDQ B14
B5 VSS VDDQ D14 B5 VSS VDDQ D14
G5 VSS VDDQ F14 +1.35VS_VGA G5 VSS VDDQ F14
L5 VSS VDDQ M14 L5 VSS VDDQ M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
B10 VSS VDDQ T14 B10 VSS VDDQ T14
+1.35VS_VGA D10 VSS VDDQ D10 VSS VDDQ

CG344

CG345

CG346

CG347

CG348

CG349

CG350

CG351

CG352

CG353
G10 VSS G10 VSS
VSS 1 1 1 1 1 1 1 1 1 1 VSS
L10 A1 L10 A1
VSS VSSQ VSS VSSQ
1

P10 C1 P10 C1
RG121 T10 VSS VSSQ E1 T10 VSS VSSQ E1
549_0402_1% H14 VSS VSSQ N1 2 2 2 2 2 2 2 2 2 2 H14 VSS VSSQ N1

22U_0603_6.3V6M

10U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
+1.35VS_VGA K14 VSS VSSQ R1 K14 VSS VSSQ R1
VSS VSSQ U1 +1.35VS_VGA VSS VSSQ U1
2

VSSQ H2 VSSQ H2
1 2 +FBB_VREFC W=16mils G1
VDD
VSSQ
VSSQ
K2 G1
VDD
VSSQ
VSSQ
K2
B
L1 A3 L1 A3 B
VDD VSSQ VDD VSSQ
1

RG122 G4 C3 G4 C3
RG123

CG113

CG114
820P_0402_25V7

820P_0402_25V7
1.33K_0402_1%

1 1 VDD VSSQ VDD VSSQ


931_0402_1% L4 E3 L4 E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
2 2 C10 VDD VSSQ U3 C10 VDD VSSQ U3
2

VDD VSSQ VDD VSSQ


1

D R10 C4 R10 C4
2 QG3 D11 VDD VSSQ R4 D11 VDD VSSQ R4
<46,52,54> MEM_VREF VDD VSSQ VDD VSSQ
G MESS138W-G_SOT323-3 G11 F5 G11 F5
L11 VDD VSSQ M5 L11 VDD VSSQ M5
S
3

P11 VDD VSSQ F10 P11 VDD VSSQ F10


G14 VDD VSSQ M10 +1.35VS_VGA G14 VDD VSSQ M10
L14 VDD VSSQ C11 L14 VDD VSSQ C11
VDD VSSQ R11 VDD VSSQ R11
VSSQ A12 VSSQ A12
VSSQ C12 VSSQ C12

CG354

CG355

CG356

CG357

CG358

CG359

CG360

CG361

CG362

CG363
VSSQ E12 VSSQ E12
VSSQ 1 1 1 1 1 1 1 1 1 1 VSSQ
N12 N12
VSSQ R12 VSSQ R12
170-BALL VSSQ U12 170-BALL VSSQ U12
VSSQ H13 2 2 2 2 2 2 2 2 2 2 VSSQ H13

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
X76@ X76@

+1.35VS_VGA
Under VRAM +1.35VS_VGA
CG115

CG116

CG117

CG118

CG119

CG120

CG121

CG122

CG123

CG124

CG125

CG126

CG132

CG133

CG134

CG135

CG136

CG137

CG138

CG139

CG140

CG141

A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A

22uF 10uF 1uF


2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
10U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

VDD/VDDQ 10 12 36

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GDDR5_B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 53 of 80
5 4 3 2 1
5 4 3 2 1

UG5 MF=1 UG6 MF=0


MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 A4
DQ24 DQ0 FBC_D24 <48> DQ24 DQ0 FBC_D32 <48>
C2 A2 C2 A2
<48> FBC_EDC3 EDC0 EDC3 DQ25 DQ1 FBC_D25 <48> <48> FBC_EDC4 EDC0 EDC3 DQ25 DQ1 FBC_D33 <48>
C13 B4 C13 B4
<48> FBC_EDC2 EDC1 EDC2 DQ26 DQ2 FBC_D26 <48> <48> FBC_EDC5 EDC1 EDC2 DQ26 DQ2 FBC_D34 <48>
R13 B2 R13 B2
<48> FBC_EDC1 EDC2 EDC1 DQ27 DQ3 FBC_D27 <48> <48> FBC_EDC6 EDC2 EDC1 DQ27 DQ3 FBC_D35 <48>
R2 E4 R2 E4
<48> FBC_EDC0 EDC3 EDC0 DQ28 DQ4 FBC_D28 <48> <48> FBC_EDC7 EDC3 EDC0 DQ28 DQ4 FBC_D36 <48>
E2 E2
DQ29 DQ5 FBC_D29 <48> DQ29 DQ5 FBC_D37 <48>
F4 F4
DQ30 DQ6 FBC_D30 <48> DQ30 DQ6 FBC_D38 <48>
D
D2 F2 D2 F2 D
<48> FBC_DBI3 DBI0# DBI3# DQ31 DQ7 FBC_D31 <48> <48> FBC_DBI4 DBI0# DBI3# DQ31 DQ7 FBC_D39 <48>
D13 A11 D13 A11
<48> FBC_DBI2 DBI1# DBI2# DQ16 DQ8 FBC_D16 <48> <48> FBC_DBI5 DBI1# DBI2# DQ16 DQ8 FBC_D40 <48>
P13 A13 P13 A13
<48> FBC_DBI1 DBI2# DBI1# DQ17 DQ9 FBC_D17 <48> <48> FBC_DBI6 DBI2# DBI1# DQ17 DQ9 FBC_D41 <48>
P2 B11 P2 B11
<48> FBC_DBI0 DBI3# DBI0# DQ18 DQ10 FBC_D18 <48> <48> FBC_DBI7 DBI3# DBI0# DQ18 DQ10 FBC_D42 <48>
B13 B13
DQ19 DQ11 FBC_D19 <48> DQ19 DQ11 FBC_D43 <48>
J12 E11 J12 E11
<48> FBC_CLK0 CK DQ20 DQ12 FBC_D20 <48> <48> FBC_CLK1 CK DQ20 DQ12 FBC_D44 <48>
J11 E13 J11 E13
<48> FBC_CLK0# CK# DQ21 DQ13 FBC_D21 <48> <48> FBC_CLK1# CK# DQ21 DQ13 FBC_D45 <48>
J3 F11 J3 F11
<48> FBC_CMD1 CKE# DQ22 DQ14 FBC_D22 <48> <48> FBC_CMD17 CKE# DQ22 DQ14 FBC_D46 <48>
F13 F13
DQ23 DQ15 FBC_D23 <48> DQ23 DQ15 FBC_D47 <48>
U11 U11
DQ8 DQ16 FBC_D8 <48> DQ8 DQ16 FBC_D48 <48>

1
40.2_0402_1%

40.2_0402_1%

40.2_0402_1%

40.2_0402_1%
H11 U13 H11 U13
<48> FBC_CMD12 BA0/A2 BA2/A4 DQ9 DQ17 FBC_D9 <48> <48> FBC_CMD29 BA0/A2 BA2/A4 DQ9 DQ17 FBC_D49 <48>

RG527

RG124

RG528

RG125
K10 T11 K10 T11
<48> FBC_CMD14 BA1/A5 BA3/A3 DQ10 DQ18 FBC_D10 <48> <48> FBC_CMD27 BA1/A5 BA3/A3 DQ10 DQ18 FBC_D50 <48>
K11 T13 K11 T13
<48> FBC_CMD13 BA2/A4 BA0/A2 DQ11 DQ19 FBC_D11 <48> <48> FBC_CMD28 BA2/A4 BA0/A2 DQ11 DQ19 FBC_D51 <48>
H10 N11 H10 N11
<48> FBC_CMD11 BA3/A3 BA1/A5 DQ12 DQ20 FBC_D12 <48> <48> FBC_CMD30 BA3/A3 BA1/A5 DQ12 DQ20 FBC_D52 <48>
N13 N13
FBC_D13 <48> FBC_D53 <48>

2
DQ13 DQ21 M11 DQ13 DQ21 M11
DQ14 DQ22 FBC_D14 <48> DQ14 DQ22 FBC_D54 <48>
K4 M13 K4 M13
<48> FBC_CMD5 A8/A7 A10/A0 DQ15 DQ23 FBC_D15 <48> <48> FBC_CMD25 A8/A7 A10/A0 DQ15 DQ23 FBC_D55 <48>
H5 U4 H5 U4
<48> FBC_CMD8 A9/A1 A11/A6 DQ0 DQ24 FBC_D0 <48> <48> FBC_CMD20 A9/A1 A11/A6 DQ0 DQ24 FBC_D56 <48>

0.01U_0402_16V7K

0.01U_0402_16V7K
1 H4 U2 1 H4 U2
<48> FBC_CMD9 A10/A0 A8/A7 DQ1 DQ25 FBC_D1 <48> <48> FBC_CMD21 A10/A0 A8/A7 DQ1 DQ25 FBC_D57 <48>

CG317

CG318
K5 T4 K5 T4
<48> FBC_CMD4 A11/A6 A9/A1 DQ2 DQ26 FBC_D2 <48> <48> FBC_CMD24 A11/A6 A9/A1 DQ2 DQ26 FBC_D58 <48>
J5 T2 J5 T2
<48> FBC_CMD6 A12/RFU/NC DQ3 DQ27 FBC_D3 <48> <48> FBC_CMD22 A12/RFU/NC DQ3 DQ27 FBC_D59 <48>
N4 N4
2 DQ4 DQ28 FBC_D4 <48> 2 DQ4 DQ28 FBC_D60 <48>
A5 N2 A5 N2
+1.35VS_VGA VPP/NC DQ5 DQ29 FBC_D5 <48> VPP/NC DQ5 DQ29 FBC_D61 <48>
U5 M4 U5 M4
VPP/NC DQ6 DQ30 FBC_D6 <48> VPP/NC DQ6 DQ30 FBC_D62 <48>
M2 M2
DQ7 DQ31 FBC_D7 <48> DQ7 DQ31 FBC_D63 <48>
RG126 2 1 1K_0402_1% J1 +1.35VS_VGA RG127 2 1 1K_0402_1% J1 +1.35VS_VGA
RG128 2 1 1K_0402_1% J10 MF RG129 2 1 1K_0402_1% J10 MF
RG130 2 1 121_0402_1% J13 SEN B1 RG131 2 1 121_0402_1% J13 SEN B1
ZQ VDDQ D1 ZQ VDDQ D1
VDDQ F1 VDDQ F1
J4 VDDQ M1 J4 VDDQ M1
<48> FBC_CMD7 ABI# VDDQ <48> FBC_CMD23 ABI# VDDQ
G3 P1 G3 P1
<48> FBC_CMD0 RAS# CAS# VDDQ <48> FBC_CMD19 RAS# CAS# VDDQ
G12 T1 G12 T1
+1.35VS_VGA
GDDR5_C <48>
<48>
<48>
FBC_CMD10
FBC_CMD3
FBC_CMD15
L3
L12
CS#
CAS#
WE#
WE#
RAS#
CS#
VDDQ
VDDQ
VDDQ
G2
L2
B3
<48>
<48>
<48>
FBC_CMD31
FBC_CMD16
FBC_CMD26
L3
L12
CS#
CAS#
WE#
WE#
RAS#
CS#
VDDQ
VDDQ
VDDQ
G2
L2
B3
VDDQ D3 VDDQ D3
C VDDQ VDDQ C
F3 F3
D5 VDDQ H3 D5 VDDQ H3
CG420

CG421

CG422

CG423

CG424

CG425

CG426

CG427

CG428

CG429

CG430

CG431

CG432

CG433

CG434

CG435

<48> FBC_WCK23# WCK01# WCK23# VDDQ <48> FBC_WCK45# WCK01# WCK23# VDDQ
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 K3 D4 K3
<48> FBC_WCK23 WCK01 WCK23 VDDQ <48> FBC_WCK45 WCK01 WCK23 VDDQ
M3 M3
P5 VDDQ P3 P5 VDDQ P3
<48> FBC_WCK01# WCK23# WCK01# VDDQ <48> FBC_WCK67# WCK23# WCK01# VDDQ
P4 T3 P4 T3
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 <48> FBC_WCK01 WCK23 WCK01 VDDQ <48> FBC_WCK67 WCK23 WCK01 VDDQ
E5 E5
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

VDDQ N5 VDDQ N5
A10 VDDQ E10 A10 VDDQ E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FBC_VREFC J14 VREFD VDDQ B12 +FBC_VREFC J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
VDDQ H12 VDDQ H12
J2 VDDQ K12 J2 VDDQ K12
<48> FBC_CMD2 RESET# VDDQ <48> FBC_CMD18 RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
K1 VSS VDDQ B14 K1 VSS VDDQ B14
B5 VSS VDDQ D14 B5 VSS VDDQ D14
G5 VSS VDDQ F14 +1.35VS_VGA G5 VSS VDDQ F14
L5 VSS VDDQ M14 L5 VSS VDDQ M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
B10 VSS VDDQ T14 B10 VSS VDDQ T14
+1.35VS_VGA D10 VSS VDDQ D10 VSS VDDQ

CG364

CG365

CG366

CG367

CG368

CG369

CG370

CG371

CG372

CG373
G10 VSS G10 VSS
VSS 1 1 1 1 1 1 1 1 1 1 VSS
L10 A1 L10 A1
VSS VSSQ VSS VSSQ
1

P10 C1 P10 C1
RG132 T10 VSS VSSQ E1 T10 VSS VSSQ E1
549_0402_1% H14 VSS VSSQ N1 2 2 2 2 2 2 2 2 2 2 H14 VSS VSSQ N1

22U_0603_6.3V6M

10U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
+1.35VS_VGA K14 VSS VSSQ R1 K14 VSS VSSQ R1
VSS VSSQ U1 +1.35VS_VGA VSS VSSQ U1
2

VSSQ H2 VSSQ H2
1 2 +FBC_VREFC W=16mils G1
VDD
VSSQ
VSSQ
K2 G1
VDD
VSSQ
VSSQ
K2
B
L1 A3 L1 A3 B
VDD VSSQ VDD VSSQ
1

RG133 G4 C3 G4 C3
RG134

CG148

CG149
820P_0402_25V7

820P_0402_25V7
1.33K_0402_1%

1 1 VDD VSSQ VDD VSSQ


931_0402_1% L4 E3 L4 E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
2 2 C10 VDD VSSQ U3 C10 VDD VSSQ U3
2

VDD VSSQ VDD VSSQ


1

D R10 C4 R10 C4
2 QG4 D11 VDD VSSQ R4 D11 VDD VSSQ R4
<46,52,53> MEM_VREF VDD VSSQ VDD VSSQ
G MESS138W-G_SOT323-3 G11 F5 G11 F5
L11 VDD VSSQ M5 L11 VDD VSSQ M5
S
3

P11 VDD VSSQ F10 P11 VDD VSSQ F10


G14 VDD VSSQ M10 +1.35VS_VGA G14 VDD VSSQ M10
L14 VDD VSSQ C11 L14 VDD VSSQ C11
VDD VSSQ R11 VDD VSSQ R11
VSSQ A12 VSSQ A12
VSSQ C12 VSSQ C12

CG374

CG375

CG376

CG377

CG378

CG379

CG380

CG381

CG382

CG383
VSSQ E12 VSSQ E12
VSSQ 1 1 1 1 1 1 1 1 1 1 VSSQ
N12 N12
VSSQ R12 VSSQ R12
170-BALL VSSQ U12 170-BALL VSSQ U12
VSSQ H13 2 2 2 2 2 2 2 2 2 2 VSSQ H13

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
X76@ X76@

+1.35VS_VGA
Under VRAM +1.35VS_VGA
CG150

CG151

CG152

CG153

CG154

CG155

CG156

CG157

CG158

CG159

CG160

CG161

CG167

CG168

CG169

CG170

CG171

CG172

CG173

CG174

CG175

CG176

A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A

22uF 10uF 1uF


2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
10U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

10U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

VDD/VDDQ 10 12 36

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GDDR5_C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 54 of 80
5 4 3 2 1
A B C D E F G H

+3VS +1.8VS +1V8_AON

+1V8_AON / +1V8_MAIN

1
1
CG438 @
0.1U_0201_6.3V6K RG70 RG71 +1.8VS
10K_0402_5% 4.7K_0402_5% +1V8_AON
2 UG12

2
1 14
VIN1 VOUT1

5
2 13
RG551 1 VCC VIN1 VOUT1
<46,71> +1.35VS_VGA_PGOOD B 1V8_AON_ON 1
0_0201_5% Y
4 3 12 1 2
1 2 GPU_PWR_EN 2 ON1 CT1
A CG64 CG320
<20,43> DGPU_PWR_EN G +5VS 4 11 220P_0402_50V8J 10U_0603_6.3V6M
VBIAS GND 2

3
1 1V8_MAIN_EN 5 10 1 2 +1V8_MAIN 1
UG25
1 @ 2 74LVC1G32GW_TSSOP5 ON2 CT2 CG65
<43> EC_1V8_AON_EN +1V8_AON 6 9 220P_0402_50V8J
RG552 7 VIN2 VOUT2 8
0_0201_5% VIN2 VOUT2
1

0.1U_0402_10V7K

22U_0603_6.3V6M

0.1U_0402_10V7K

10U_0603_6.3V6M
15
GPAD CG290
1 1 1

1
CG487

CG288

CG386

CG289
@ AOZ1331_SON14_2X3 10U_0603_6.3V6M
2

2
2 2 2
<46> 1V8_MAIN_EN

+3VS
<43> GPU_OVERT# 1 2
@
<43> EC_3V3_SYS_EN
RG567
0_0201_5%

1
RG505
10K_0201_5%
+1V8_AON
+1V8_MAIN +3VS
+3V3_SYS +3V3_SYS
+1V8_MAIN RB751S40T1G_SOD523-2

2
DG7
1 UG14
1 2 1V8_MAIN_EN 2 1 NVVDD1_EN 1
CG439
NVVDD1_EN <69> VIN1
1

1
0.1U_0201_6.3V6K 1 2
RG546 @ CG322 VIN2
100K_0201_5% DG3 2 RG515 1U_0402_6.3V6K 7 6

5
RB751S40T1G_SOD523-2 10K_0402_5% VIN thermal VOUT
1 @ 2 RG545 2 3

GND VCC
+5VALW
2

2
EC_NVVDD1_EN <43> VBIAS

6
D

1U_0402_6.3V6K~D

10U_0402_6.3V6M
RG549 1 68K_0402_1%
2 IN B 4 1 2 3V3_SYS_EN 4 5
UG23A 15K_0402_5% RG568 1 1
1V8_MAIN_EN OUT Y ON GND

CG323

CG385
G BSS138DW_SC88-6 1 2 0_0201_5% 2
IN A
1
3

1
D
S UG26 TPS22961DNYR_WSON8

1
OVERT# 5 UG23B NL17SZ08DFT2G_SC70-5 CG240 CG384 2 2

3
<46> OVERT# G BSS138DW_SC88-6 CG442 0.01U_0402_16V 0.1U_0402_10V7K

2
0.01U_0402_16V 2

2
S
4

+1V8_AON

2 2

1
CG444
0.1U_0201_6.3V6K

5
2
RB751S40T1G_SOD523-2

GND VCC
DG6 1
IN B 4
1 2 2 OUT Y NVVDD2_EN <68,70>
IN A
<26,27,46> DGPU_PEX_RST#
UG28
NL17SZ08DFT2G_SC70-5

3
1 @ 2
EC_NVVDD2_EN <43>
RG550 RG569
+1V8_AON 100K_0402_5% 0_0201_5%
1 2
+1V8_AON

1
1 CG443
CG246 0.01U_0402_16V

2
1

0.1U_0201_6.3V6K

RG516 2
DMN53D0LDW-7 2N SOT363-6

10K_0201_5% +3VS
5

3
2

RG554
QG502B
GND VCC

DGPU_PEX_RST#
1

1 0_0201_5%
IN B 4 1 2 5
2 OUT Y RG506
IN A 10K_0201_5%
4

UG22
DMN53D0LDW-7 2N SOT363-6

NL17SZ08DFT2G_SC70-5 DG4
3
6

RB751S40T1G_SOD523-2
RG553
QG502A

0_0201_5% 2 1
GPU_GC6_FB_EN 1 2 2 NVVDD1_PGOOD <46,69,70>
<46> GPU_GC6_FB_EN +NVVDD1 +NVVDD2 +1V8_AON +1V8_MAIN +3V3_SYS
1

100_0402_1%

100_0402_1%

51_0402_5%

51_0402_5%

51_0402_5%
NVVDD2_PGOOD <68,70>

1
+5VALW +5VALW +5VALW +5VALW +5VALW

RG544

RG542

RG510

RG512

RG514
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2

2
1

1
RG543

RG541

RG509

RG511

RG513
DMN53D0LDW-7_SOT363-6

DMN53D0LDW-7_SOT363-6

DMN53D0LDW-7_SOT363-6
3 3

DMN53D0LDW-7 2N SOT363-6

DMN53D0LDW-7 2N SOT363-6
3

3
2

2
QG509B

QG507B

QG503B

QG504B

QG505B
5 5 5 5 5

DMN53D0LDW-7_SOT363-6

DMN53D0LDW-7_SOT363-6

DMN53D0LDW-7_SOT363-6
DMN53D0LDW-7 2N SOT363-6

DMN53D0LDW-7 2N SOT363-6
4

4
6

6
QG509A

QG507A

QG503A

QG504A

QG505A
NVVDD1_EN 2 NVVDD2_EN 2 1V8_AON_ON 2 1V8_MAIN_EN 2 3V3_SYS_EN 2

+1V8_AON

1
1
CG440
0.1U_0201_6.3V6K
2
5

1 VCC
B 4
Y FBVDD/Q_EN <71>
2 A
<68> +1.0VS_VGA_PGOOD G
1
3

UG27 @
74LVC1G32GW_TSSOP5 RG557 1 @ 2
EC_FBVDD/Q_EN <43>
10K_0402_5%
RG570
2

0_0201_5%

4 4

Security Classification
2015/09/18
Compal Secret Data
2016/09/18 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GPU power control
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 55 of 80
A B C D E F G H
5 4 3 2 1

UT1

S IC DSL6340 SLKYB B0 FC-CSP I/O CONTROL


SA000090N0L UT1A
ARES2R1@ TBT@ CT3 1 2 0.22U_0201_6.3V PEG_CTX_TRX_P12_C Y23 V23 PEG_CRX_TTX_P12_C 0.22U_0201_6.3V 2 1 CT14 TBT@
<7> PEG_CTX_TRX_P12 PEG_CTX_TRX_N12_C Y22 PCIE_RX0_P PCIE_TX0_P V22 PEG_CRX_TTX_N12_C 0.22U_0201_6.3V PEG_CRX_TTX_P12 <7>
TBT@ CT15 1 2 0.22U_0201_6.3V 2 1 CT16 TBT@
<7> PEG_CTX_TRX_N12 PCIE_RX0_N PCIE_TX0_N PEG_CRX_TTX_N12 <7>
UT1
TBT@ CT1 1 2 0.22U_0201_6.3V PEG_CTX_TRX_P13_C T23 P23 PEG_CRX_TTX_P13_C 0.22U_0201_6.3V 2 1 CT12 TBT@

PCIe GEN3
<7> PEG_CTX_TRX_P13 PEG_CTX_TRX_N13_C PCIE_RX1_P PCIE_TX1_P P22 PEG_CRX_TTX_N13_C 0.22U_0201_6.3V PEG_CRX_TTX_P13 <7>
TBT@ CT13 1 2 0.22U_0201_6.3V T22 2 1 CT2 TBT@
<7> PEG_CTX_TRX_N13 PCIE_RX1_N PCIE_TX1_N PEG_CRX_TTX_N13 <7>
PEG X4 Bus PEG_CTX_TRX_P14_C M23
TBT@ CT4 1 2 0.22U_0201_6.3V K23 PEG_CRX_TTX_P14_C 0.22U_0201_6.3V 2 1 CT109 TBT@
<7> PEG_CTX_TRX_P14 PEG_CTX_TRX_N14_C M22 PCIE_RX2_P PCIE_TX2_P K22 PEG_CRX_TTX_N14_C 0.22U_0201_6.3V PEG_CRX_TTX_P14 <7>
TBT@ CT18 1 2 0.22U_0201_6.3V 2 1 CT108 TBT@
<7> PEG_CTX_TRX_N14 PCIE_RX2_N PCIE_TX2_N PEG_CRX_TTX_N14 <7>
D S IC A31 DSL6340 QSCX B0 THUNDERBOLT PEG_CTX_TRX_P15_C H23 PEG_CRX_TTX_P15_C 0.22U_0201_6.3V D
SA000090N2L TBT@ CT5 1 2 0.22U_0201_6.3V F23 2 1 CT111 TBT@
<7> PEG_CTX_TRX_P15 PEG_CTX_TRX_N15_C H22 PCIE_RX3_P PCIE_TX3_P PEG_CRX_TTX_N15_C 0.22U_0201_6.3V PEG_CRX_TTX_P15 <7>
ARQSR1@ TBT@ CT21 1 2 0.22U_0201_6.3V F22 2 1 CT110 TBT@
<7> PEG_CTX_TRX_N15 PCIE_RX3_N PCIE_TX3_N PEG_CRX_TTX_N15 <7>
UT1 V19 L4 TBT_RST#_R RT1 2 @ 1 0_0201_5%
PEG CLK <17> CLK_PCIE_P3 PCIE_REFCLK_100_IN_P PERST_N PCIRST# <6,17,28,29,30,43>
(From PCH CLKOUT3) T19
<17> CLK_PCIE_N3 2 1 CLKREQ_PCIE#3_R AC5 PCIE_REFCLK_100_IN_N N16 PCIE_RBIAS 1 TBT@ 2 3.01K_0201_1%
@ RT3
<17> CLKREQ_PCIE#3 PCIE_CLKREQ_N PCIE_RBIAS
RT2 0_0201_5%
TBT@ CT6 1 2 0.1U_0201_6.3V6K CPU_DP1_P0_C AB7 R2
<7> CPU_DP1_P0 CPU_DP1_N0_C DPSNK0_ML0_P DPSRC_ML0_P
TBT@ CT7 1 2 0.1U_0201_6.3V6K AC7 R1
S IC DSL6340 SLL42 B1 FCCSP 337P THUNDERBOLT A31 !
<7> CPU_DP1_N0 DPSNK0_ML0_N DPSRC_ML0_N Closed to UT1 +3.3V_TBT_SX
TBT@ CT8 1 2 0.1U_0201_6.3V6K CPU_DP1_P1_C AB9 N2
SA000090N5L <7> CPU_DP1_P1 CPU_DP1_N1_C DPSNK0_ML1_P DPSRC_ML1_P TBT_I2C_SDA
ARQSR3@ TBT@ CT9 1 2 0.1U_0201_6.3V6K AC9 N1 RT26 2 TBT@ 1 3.3K_0201_5%

SOURCE PORT 0
<7> CPU_DP1_N1 DPSNK0_ML1_N DPSRC_ML1_N TBT_I2C_SCL RT27 2 TBT@ 1 3.3K_0201_5%

SINK PORT 0
TBT@ CT10 1 2 0.1U_0201_6.3V6K CPU_DP1_P2_C AB11 L2 TBT_PCIE_WAKE_N RT28 2 TBT@ 1 10K_0201_5%
<7> CPU_DP1_P2 CPU_DP1_N2_C DPSNK0_ML2_P DPSRC_ML2_P TBT_CIO_PLUG_EVENT#
<7> CPU_DP1_N2 TBT@ CT23 1 2 0.1U_0201_6.3V6K AC11 L1 RT29 2 TBT@ 1 10K_0201_5%
DPSNK0_ML2_N DPSRC_ML2_N SUSP#_R RT30 2 @ 1 10K_0201_5%
TBT@ CT11 1 2 0.1U_0201_6.3V6K CPU_DP1_P3_C AB13 J2 BATLOW# RT31 2 TBT@ 1 10K_0201_5%
CPU DDI1 <7> CPU_DP1_P3 CPU_DP1_N3_C DPSNK0_ML3_P DPSRC_ML3_P TBTA_I2C_INT
<7> CPU_DP1_N3 TBT@ CT24 1 2 0.1U_0201_6.3V6K AC13 J1 RT32 2 TBT@ 1 10K_0201_5%
+3VS_TBT DPSNK0_ML3_N DPSRC_ML3_N TBTB_I2C_INT RT33 2 TBT@ 1 10K_0201_5%
Reserve for common DP design CPU_DP1_AUXP_C TBT_RESET_N
TBT@ CT25 1 2 0.1U_0201_6.3V6K Y11 W19 RT80 2 @ 1 10K_0201_5%
<7> CPU_DP1_AUXP CPU_DP1_AUXN_C DPSNK0_AUX_P DPSRC_AUX_P NC_B4
TBT@ CT26 1 2 0.1U_0201_6.3V6K W11 Y19 RT86 2 @ 1 10K_0201_5%
CPU_DP1_AUXN_C 1 2 <7> CPU_DP1_AUXN DPSNK0_AUX_N DPSRC_AUX_N TBT_FORCE_PWR_R 2 1
RT76 @ 100K_0201_5% RT94 @ 10K_0201_5%
CPU_DP2_AUXN_C RT77 1 @ 2 100K_0201_5% CPU_DDI1HPD AA2 G1 TBT_SRC_HPD RT4 1 TBT@ 2 1M_0201_1%
CPU_DP1_AUXP_C <16> CPU_DDI1HPD DPSNK0_HPD DPSRC_HPD
RT78 1 @ 2 100K_0201_5%
CPU_DP2_AUXP_C RT79 1 @ 2 100K_0201_5% CPU_DDC1CLK Y5 N6 DPSRC_RBIAS RT5 1 TBT@ 2 14K_0402_1%
CLKREQ_PCIE#3 <16> CPU_DDC1CLK CPU_DDC1DATA DPSNK0_DDC_CLK DPSRC_RBIAS
RT24 1 TBT@ 2 10K_0201_5% R4
<16> CPU_DDC1DATA DPSNK0_DDC_DATA U1
CPU_DP2_P0_C GPIO_0 TBT_I2C_SDA <58>
<7> CPU_DP2_P0 TBT@ CT27 1 2 0.1U_0201_6.3V6K AB15 U2
TBT_I2C_SCL <58>
TBT@ CT28 1 2 0.1U_0201_6.3V6K CPU_DP2_N0_C AC15 DPSNK1_ML0_P GPIO_1 V1 TBT_EE_WP_N

LC GPIO
<7> CPU_DP2_N0 DPSNK1_ML0_N GPIO_2 TBT_TMU_CLK_OUT
V2 @ T2
TBT@ CT29 1 2 0.1U_0201_6.3V6K CPU_DP2_P1_C AB17 GPIO_3 W1 TBT_PCIE_WAKE_N RT10 1 @ 2 0_0201_5% To KB9022
+3.3V_LC +3.3V_LC <7> CPU_DP2_P1 CPU_DP2_N1_C DPSNK1_ML1_P GPIO_4 TBT_CIO_PLUG_EVENT# TBT_PCIE_WAKE# <43>
<7> CPU_DP2_N1 TBT@ CT30 1 2 0.1U_0201_6.3V6K AC17 W2 TBT_CIO_PLUG_EVENT# <20>
To CPU pin AN43
DPSNK1_ML1_N GPIO_5 Y1 TBT_HDMI_DDC_DATA
CPU_DP2_P2_C GPIO_6 TBT_HDMI_DDC_CLK @ T7
TBT@ CT31 1 2 0.1U_0201_6.3V6K AB19 Y2

SINK PORT 1
<7> CPU_DP2_P2 CPU_DP2_N2_C DPSNK1_ML2_P GPIO_7 TBT_SRC_CFG1 @ T9
<7> CPU_DP2_N2 TBT@ CT32 1 2 0.1U_0201_6.3V6K AC19 AA1 RT11 1 TBT@ 2 1M_0201_1%
C DPSNK1_ML2_N GPIO_8 J4 TBTA_I2C_INT C
CPU DDI2 CPU_DP2_P3_C POC_GPIO_0 TBTB_I2C_INT TBTA_I2C_INT <58>
TBT@ CT33 1 2 0.1U_0201_6.3V6K AB21 E2

POC GPIO
<7> CPU_DP2_P3 DPSNK1_ML3_P POC_GPIO_1
1

CPU_DP2_N3_C RTD3_USB_PWR_EN_R
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

RT6 RT7 RT8 RT9 <7> CPU_DP2_N3 TBT@ CT34 1 2 0.1U_0201_6.3V6K AC21 D4 RT12 1 @ 2 0_0201_5% RTD3_USB_PWR_EN <20>
From CPU pin AR41
DPSNK1_ML3_N POC_GPIO_2 H4 TBT_FORCE_PWR_R RT13 1 @ 2 0_0201_5% From CPU pin P43
CPU_DP2_AUXP_C POC_GPIO_3 TBT_FORCE_PWR <17>
TBT@ TBT@ TBT@ TBT@ TBT@ CT35 1 2 0.1U_0201_6.3V6K Y12 F2 BATLOW# RT14 1 @ 2 0_0201_5% PCH_BATLOW# <18>
From CPU pin BD13
<7> CPU_DP2_AUXP CPU_DP2_AUXN_C DPSNK1_AUX_P POC_GPIO_4 SUSP#_R
TBT@ CT36 1 2 0.1U_0201_6.3V6K W12 D2 RT15 1 @ 2 0_0201_5% SUSP# <29,43,45,64,67,76>
From EC pin 116
<7> CPU_DP2_AUXN DPSNK1_AUX_N POC_GPIO_5 F1 RTD3_CIO_PWR_EN_R 1 @ 2 From CPU pin AR44
JTAG RT16 0_0201_5% RTD3_CIO_PWR_EN <20>
2

1 CPU_DDI2HPD Y6 POC_GPIO_6
TBT_TDI 1 <16> CPU_DDI2HPD DPSNK1_HPD TBT_TEST_EN
2 E1 RT17 1 TBT@ 2 100_0201_5%
TBT_TMS 3 2 CPU_DDC2CLK Y8 TEST_EN

Misc
TBT_TCK 3 <16> CPU_DDC2CLK CPU_DDC2DATA DPSNK1_DDC_CLK
4 N4 AB5 TBT_TEST_PWG RT18 1 TBT@ 2 100_0201_5%
TBT_TDO 5 4 <16> CPU_DDC2DATA DPSNK1_DDC_DATA TEST_PWR_GOOD YT1
6 5 2 TBT@ 1 DPSNK_RBIAS Y18 F4 TBT_RESET_N 25MHZ 20PF +-10PPM 7M25000153
6 DPSNK_RBIAS RESET_N TBT_RESET_N <58>
RT19 14K_0402_1% RT23 1 @ 2 0_0201_5%
TBT_RESET_N_EC <43>
7 TBT_TDI Y4 D22 TBT_XTAL_25_IN 1 3
8 GND TBT_TMS V4 TDI XTAL_25_IN D23 TBT_XTAL_25_OUT 1 3
GND TBT_TCK TMS XTAL_25_OUT 1 GND GND 1
T4 CT37 CT38
TBT_TDO W4 TCK AB3 TBT_EE_DI 27P_0402_50V8J
ACES_50228-0067N-001
TDO MISC EE_DI TBT_EE_DO
27P_0402_50V8J
2
TBT@
4
CONN@ AC4 TBT@ TBT@
2 TBT@ 1 TBT_RBIAS H6 EE_DO AC3 TBT_EE_CS_N 2 2
RT25 4.75K_0402_0.5% TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_EE_CLK
+3VS_TBT RSENSE EE_CLK
A15 B7
<58> USB3_A_TRX_DTX_P1 PA_RX1_P PB_RX1_P
B15 A7
TBTA_LSTX <58> USB3_A_TRX_DTX_N1 PA_RX1_N PB_RX1_N
RT21 2 @ 1 10K_0201_5%
CLKREQ_PCIE#3_R RT20 2 TBT@ 1 10K_0201_5% TBT@ CT39 1 2 0.22U_0201_6.3V USB3_A_TTX_DRX_P1 A17 A9 TBT_TMU_CLK_OUT RT34 1 TBT@ 2 100K_0201_5%
<58> USB3_A_TTX_C_DRX_P1 USB3_A_TTX_DRX_N1 PA_TX1_P PB_TX1_P TBT_FORCE_PWR_R
<58> USB3_A_TTX_C_DRX_N1 TBT@ CT40 1 2 0.22U_0201_6.3V B17 B9 RT35 1 TBT@ 2 100K_0201_5%
RPT1 +3VS PA_TX1_N PB_TX1_N RTD3_CIO_PWR_EN_R RT36 1 TBT@ 2 100K_0201_5%
CPU_DDC2CLK 1 8 TBT@ CT41 1 2 0.22U_0201_6.3V USB3_A_TTX_DRX_P0 A19 A11 RTD3_USB_PWR_EN_R RT37 1 TBT@ 2 100K_0201_5%
CPU_DDC2DATA <58> USB3_A_TTX_C_DRX_P0 USB3_A_TTX_DRX_N0 PA_TX0_P PB_TX0_P
2 7 <58> USB3_A_TTX_C_DRX_N0 TBT@ CT42 1 2 0.22U_0201_6.3V B19 B11
CPU_DDC1CLK 3 6 PA_TX0_N PB_TX0_N NC_B4 RT45 1 TBT@ 2 100K_0201_5%

TBT PORTS
CPU_DDC1DATA 4 5 B21 A13 NC_B5 RT46 1 TBT@ 2 100K_0201_5%
<58> USB3_A_TRX_DTX_P0 PA_RX0_P PB_RX0_P NC_G2
A21 B13 RT47 1 TBT@ 2 100K_0201_5%

Port A

PORT B
<58> USB3_A_TRX_DTX_N0 PA_RX0_N PB_RX0_N
TBT@ 2.2K_0804_8P4R_5%
TBT@ CT43 1 2 0.1U_0201_6.3V6K TBT_A_AUX_P Y15 Y16
<58> TBT_A_AUX_P_C TBT_A_AUX_N PA_DPSRC_AUX_P PB_DPSRC_AUX_P
B
<58> TBT_A_AUX_N_C TBT@ CT44 1 2 0.1U_0201_6.3V6K W15 W16 B
CPU_DDI1HPD 1 2 PA_DPSRC_AUX_N PB_DPSRC_AUX_N
CPU_DDI2HPD
RT38 TBT@ 100K_0201_5%
TBT_A_USB20_P
Close to UT2
RT39 1 TBT@ 2 100K_0201_5% E20 E19
TBTA_LSTX <58> TBT_A_USB20_P TBT_A_USB20_N PA_USB2_D_P PB_USB2_D_P TBT_EE_DI
RT40 1 TBT@ 2 1M_0201_1% D20 D19 RT98 1 @ 2 0_0201_5%
TBTA_HPD <58> TBT_A_USB20_N PA_USB2_D_N PB_USB2_D_N TBT_EE_DO PD_EE_DI <58>
RT41 1 TBT@ 2 100K_0201_5% RT99 1 @ 2 0_0201_5% PD_EE_DO <58>
TBTA_LSRX RT42 1 TBT@ 2 1M_0201_1% TBTA_LSTX A5 B4 NC_B4 TBT_EE_CS_N RT100 1 @ 2 0_0201_5%
<58> TBTA_LSTX TBTA_LSRX PA_LS_G1 PB_LS_G1 NC_B5 TBT_EE_CLK PD_EE_CS_N <58>

POC
POC
<58> TBTA_LSRX
A4 B5 RT101 1 @ 2 0_0201_5% PD_EE_CLK <58>
TBTA_HPD M4 PA_LS_G2 PB_LS_G2 G2 NC_G2
<58> TBTA_HPD PA_LS_G3 PB_LS_G3
2 TBT@ 1 PA_USB2_RBIAS H19 F19 PB_USB2_RBIAS 1 TBT@ 2
RT43 499_0201_1% PA_USB2_RBIAS PB_USB2_RBIAS RT44 499_0201_1%
AC23 D6
AB23 THERMDA MONDC_SVR
THERMDA A23
V18 ATEST_P B23
PCIE_ATEST ATEST_N
AC1 DEBUG E18
TEST_EDM USB2_ATEST
L15 W13
N15 FUSE_VQPS_64 MONDC_DPSNK_0
FUSE_VQPS_128 W18
C23 MONDC_DPSNK_1
C22 MONDC_CIO_0 AB2
MONDC_CIO_1 MONDC_DPSRC
@ ALPINE-RIDGE_BGA337
+3.3V_FLASH

1
CT45
0.1U_0201_6.3V6K
TBT@
2
UT2
RT50 1 TBT@ 2 3.3K_0402_5% TBT_EE_CS_N 1 8
RT49 2 TBT@ 1 3.3K_0402_5% TBT_EE_DO 2 CS# VCC 7 TBT_HOLD_N 3.3K_0402_5% 2 TBT@ 1 RT51
A A
RT48 1 TBT@ 2 3.3K_0402_5% TBT_EE_WP_N 3 DO(IO1) HOLD#(IO3) 6 TBT_EE_CLK
4 WP#(IO2) CLK 5 TBT_EE_DI
GND DI(IO0)
W25Q80DVSSIG_SO8
SA00003EW10
TBT@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2016/01/06 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Thunderbolt (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 56 of 80
5 4 3 2 1
5 4 3 2 1

+3VALW +3.3V_TBT_SX +3VALW +3VS_TBT +3.3V_LC +3.3V_TBT_SX +3VS_TBT

1 @ 2 1 @ 2

0.1U_0201_6.3V6K

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
RT97 RT95 1 1 1 1 1 1 1 1
0_0402_5% 0_0805_5% CT46 CT47 CT48 CT49 CT50 CT51 CT52 CT53

D
TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ D
2 2 2 2 2 2 2 2

R13
+0.9V_DP

R6

H9
F8
UT1B
L8 A2

VCC3P3_SX

VCC3P3A
VCC3P3_LC

VCC3P3_S0
VCC0P9_DP VCC3P3_SVR

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
L11 A3
L12 VCC0P9_DP VCC3P3_SVR B3
1 1 1 1 1 1 1 VCC0P9_DP VCC3P3_SVR
CT54 CT57 CT58 CT59 CT60 CT61 CT62 M8
T11 VCC0P9_DP
TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ T12 VCC0P9_DP L9 +0.9V_SVR
2 2 2 2 2 2 2 VCC0P9_DP VCC0P9_SVR

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
L6 M9
M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12
VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA 1 1 1 1 1 1 1
V11 E13 CT63 CT64 CT65 CT66 CT67 CT68 CT69
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
+0.9V_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12 TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
VCC0P9_PCIE VCC0P9_SVR_ANA

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
M15 J9
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
1 1 1 1 VCC0P9_PCIE
CT55 CT70 CT71 CT72 L19 LT1 TBT@
N19 VCC0P9_ANA_PCIE_1 C1 TBT_SVR_IND 1 2
VCC0P9_ANA_PCIE_1 SVR_IND

47U_0603_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
TBT@ TBT@ TBT@ TBT@ L18 C2 0.6UH_MND-04ABIR60M-XGL_20%
2 2 2 2 M18 VCC0P9_ANA_PCIE_2 SVR_IND D1
VCC0P9_ANA_PCIE_2 SVR_IND 1 1 1
+0.9V_USB N18 CT73 CT74 CT75

VCC
VCC0P9_ANA_PCIE_2
R15 A1 TBT@ TBT@ TBT@
1U_0201_6.3V6M VCC0P9_USB SVR_VSS 2 2 2

1U_0201_6.3V6M
R16 B1
+0.9V_CIO VCC0P9_USB SVR_VSS B2
1 1 SVR_VSS
CT77 CT56 R8
R9 VCC0P9_CIO
TBT@ TBT@ R11 VCC0P9_CIO
2 2 VCC0P9_CIO +0.9V_LVR_OUT

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
R12 F18
VCC0P9_CIO VCC0P9_LVR

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 H18
CT78 CT79 CT80 +3.3V_ANA_PCIE L16 VCC0P9_LVR J11
+3.3V_ANA_USB2 VCC3P3_ANA_PCIE VCC0P9_LVR 1 1 1 1
J16 H11 CT81 CT82 CT83 CT84
C
TBT@ TBT@ TBT@ VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE C
2 2 2

1U_0201_6.3V6M

1U_0201_6.3V6M
A6 V5 TBT@ TBT@ TBT@ TBT@
A8 VSS_ANA VSS_ANA V6 2 2 2 2
1 1 VSS_ANA VSS_ANA
CT85 CT86 A10 V8
A12 VSS_ANA VSS_ANA V9
TBT@ TBT@ A14 VSS_ANA VSS_ANA V15
2 2 A16 VSS_ANA VSS_ANA V16
A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
B6 VSS_ANA VSS_ANA W8
B8 VSS_ANA VSS_ANA W9
B10 VSS_ANA VSS_ANA W20
B12 VSS_ANA VSS_ANA W22
B14 VSS_ANA VSS_ANA W23
B16 VSS_ANA VSS_ANA Y9
B18 VSS_ANA VSS_ANA Y13
B20 VSS_ANA VSS_ANA Y20
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
D11 VSS_ANA VSS_ANA AB8
D12 VSS_ANA VSS_ANA AB10
D13 VSS_ANA VSS_ANA AB12
D15 VSS_ANA VSS_ANA AB14
D16 VSS_ANA VSS_ANA AB16

GND
D18 VSS_ANA VSS_ANA AB18
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
E15 VSS_ANA VSS_ANA AC8
E16 VSS_ANA VSS_ANA AC10
E22 VSS_ANA VSS_ANA AC12
E23 VSS_ANA VSS_ANA AC14
F9 VSS_ANA VSS_ANA AC16
B F16 VSS_ANA VSS_ANA AC18 B
F20 VSS_ANA VSS_ANA AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
H12 VSS_ANA VSS E6
H13 VSS_ANA VSS F5
H15 VSS_ANA VSS F6
H16 VSS_ANA VSS H5
H20 VSS_ANA VSS H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
J19 VSS_ANA VSS J13
J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

N20 VSS_ANA VSS T18


N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
@ ALPINE-RIDGE_BGA337
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2016/01/06 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Thunderbolt (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 57 of 80
5 4 3 2 1
5 4 3 2 1

USB3_A_TTX_C_DRX_P0 DT2 1 2
ESD@
ESD8011MUT5G X3DFN2 ESD
USB3_A_TTX_C_DRX_N0 DT3 1 2
ESD@
ESD8011MUT5G X3DFN2 ESD
+3VALW +3VALW_PD
USB3_A_TRX_DTX_P0 DT4 1 2
ESD@
1 @ 2 ESD8011MUT5G X3DFN2 ESD

RT53 USB3_A_TRX_DTX_N0 DT5 1 2


D 1 D
0_0402_5% CT88 ESD@
0.1U_0402_10V6K +5VALW +TBTA_VBUS ESD8011MUT5G X3DFN2 ESD
PD@
2 USB3_A_TTX_C_DRX_P1 DT6 1 2
60mil 3A 60mil 3A Change DT1 and add DT15 follow E-team's design for DELL dat.04/07
ESD@
ESD8011MUT5G X3DFN2 ESD

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 1 1 1 USB3_A_TTX_C_DRX_N1
CT90 CT91 CT92 CT93 DT7 1 2

3
CT106 ESD@
1U_0603_25V6K DT1 DT15 ESD8011MUT5G X3DFN2 ESD
2 2 2 2 SDM10U45-7_SOD523-2~D AZ4024-02S_SOT23-3~D

2
ESD@ ESD@ USB3_A_TRX_DTX_P1 DT8 1 2
ESD@

2
ESD8011MUT5G X3DFN2 ESD

1
TBTA_LDO_BMC
+1.8VD_TBTA_LDO USB3_A_TRX_DTX_N1 DT9 1 2
+1.8VA_TBTA_LDO Close to UT4
ESD@
1 1 ESD8011MUT5G X3DFN2 ESD

1
CT98 CT99 CT100 TBTA_CC1 DT111 2

2
2.2U_0603_16V6K 4.7U_0603_10V6K 4.7U_0603_10V6K ESD@

2
PD@ 2 2 RT22 ESD8011MUT5G X3DFN2 ESD
PD@ +3VALW_PD PD@ +3.3V_FLASH
0_0201_5%
@ TBTA_CC2 DT121 2
ESD@

1
1 ESD8011MUT5G X3DFN2 ESD

+3VS CT101 TBTA_SBU1 DT131 2


1U_0402_6.3V6K 0.6A ESD@
Follow TD team 2 ESD8011MUT5G X3DFN2 ESD
Master0:0 ohm PD@

H10

C11
D11
A11
B11

B10

A10
H1

B1

K1

A2

E1

A6
A7
A8
B7

B9

A9
Slave1:93.1K ohm UT4 TBTA_SBU2 DT141 2
1

RT83 1 2 0_0201_5% F1 ESD@

VDDIO

LDO_1V8D

LDO_BMC

SENSEN
VIN_3V3

PP_5V0
PP_5V0
PP_5V0
PP_5V0

HV_GATE1

HV_GATE2
LDO_1V8A

PP_CABLE

PP_HV
PP_HV
PP_HV
PP_HV

SENSEP
RT107 RT57 RT58 I2C_ADDR ESD8011MUT5G X3DFN2 ESD
10K_0201_5% 10K_0201_5% 10K_0201_5% D1 +3.3V_TBT_SX_R +3.3V_TBT_SX
<56> TBT_I2C_SDA I2C_SDA1
@ @ <56> TBT_I2C_SCL D2
C1 I2C_SCL1
<56> TBTA_I2C_INT
2

PD_IRQ# I2C_IRQ1_N 1 @ 2
RT61 0_0201_5%
RT59 1 @ 2 0_0201_5% TBTA_I2C_SDA1_R A5
<18,41,42,43,46> EC_SMB_DA2 TBTA_I2C_SCL1_R I2C_SDA2 +3.3V_FLASH
<18,41,42,43,46> EC_SMB_CK2 RT60 1 @ 2 0_0201_5% B5 H11
PD_IRQ# B6 I2C_SCL2 VBUS J10
<43> PD_IRQ# I2C_IRQ2_N VBUS J11
B2 VBUS K11
T64 TP@ GPIO0 VBUS
C T65 TP@ C2 1 1 C
TI's Request D10 GPIO1 CT102 CT103
T114 TP@ GPIO2
T120 TP@ G11 1U_0201_6.3V6M 10U_0402_6.3V6M
C10 GPIO3 PD@ PD@
<56> TBTA_HPD GPIO4 2 2
T121 TP@ E10 H2
G10 GPIO5 VOUT_3V3
T122 TP@ GPIO6
TI's Request
T70 TP@ D7
H6 GPIO7 MCM1012B900F06BP_4P
T71 TP@ GPIO8 Delete RT96 for layout @12/31 TBT_A_USB20_PT
G1 4 3 TBT_A_USB20_L_PT
PD_EE_CLK A3 LDO_3V3
<56> PD_EE_CLK PD_EE_DI SPI_CLK
<56> PD_EE_DI B4
PD_EE_DO A4 SPI_MOSI TBT_A_USB20_NT 1 2 TBT_A_USB20_L_NT
<56> PD_EE_DO PD_EE_CS_N SPI_MISO TBT_A_USB20_PT
<56> PD_EE_CS_N B3 K6
SPI_SS_N C_USB_TP L6 TBT_A_USB20_NT LT2 EMI@
TBT_A_USB20_P L5 C_USB_TN
<56> TBT_A_USB20_P TBT_A_USB20_N USB_RP_P
<56> TBT_A_USB20_N K5
USB_RP_N MCM1012B900F06BP_4P
RT62 2 PD@ 1100K_0201_5% PD_UART E2 K7 TBT_A_USB20_PB TBT_A_USB20_NB 4 3 TBT_A_USB20_L_NB
F2 UART_TX C_USB_BP L7 TBT_A_USB20_NB
UART_RX C_USB_BN
F4 TBT_A_USB20_PB 1 2 TBT_A_USB20_L_PB
T62 TP@ SWD_DATA
TI's Request
T63 TP@ G4
SWD_CLK L9 TBTA_CC1 CT112 1 2 220P_0201_25V7K LT3 EMI@
C_CC1 L10 TBTA_CC2 CT113 1 2 220P_0201_25V7K +3.3V_FLASH
C_CC2 TI's Requirement
RT63 2 PD@ 1 100K_0201_5% TBTA_MRESET E11
MRESET
RPD_G1

1
K9 RT64 1 PD@ 2 10K_0201_5% DT10
TBTA_LSTX L4 RPD_G1 K10 RPD_G2 RT65 1 PD@ 2 10K_0201_5% RT66 RT67 TBT_A_USB20_L_PT 1 9 TBT_A_USB20_L_PT
<56> TBTA_LSTX TBTA_LSRX TBT_LSTX/R2P RPD_G2
<56> TBTA_LSRX K4 TI's Requirement 10K_0201_5% 10K_0201_5%
TBT_LSRX/P2R PD@ PD@ TBT_A_USB20_L_NT 2 8 TBT_A_USB20_L_NT

2
+3.3V_TBT_SX RT68 2 PD@ 1 100K_0201_5% TBTA_DIG_AUD_P L3 E4 DEBUG_CTL1 TBT_A_USB20_L_NB 4 7 TBT_A_USB20_L_NB
RT69 2 PD@ 1 100K_0201_5% TBTA_DIG_AUD_N K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 DEBUG_CTL2
DIG_AUD_N/DEBUG4 DEBUG_CTL2 TBT_A_USB20_L_PB 5 6 TBT_A_USB20_L_PB
1

RT70 RT71 2 PD@ 1 100K_0201_5% TBTA_DEBUG1 L2


100K_0201_5% RT72 2 PD@ 1 100K_0201_5% TBTA_DEBUG2 K2 DEBUG1
DEBUG2 3
K8 TBTA_SBU1
2

TBT_A_AUX_P_C J1 C_SBU1 Differential Signal ESD@ TVWDF1004AD0_DFN9


<56> TBT_A_AUX_P_C TBT_A_AUX_N_C AUX_P TBTA_SBU2
<56> TBT_A_AUX_N_C J2 L8
AUX_N C_SBU2
1

RT73 +3.3V_FLASH 1 @ 2 BUSPOWER# F10


100K_0201_5% 0_0201_5% BUSPOWER_N F11 RESET_N 1 @ 2 TBT_RESET_N
B RESET_N TBT_RESET_N <56> B
RT74 RT102 0_0201_5%
TBTA_ROSC G2
2

R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1

RT75 PD@ TPS65982_BGA96


A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11

15K_0402_1%
PD@ +TBTA_VBUS +TBTA_VBUS
2

1
CT104 JUSBC1
0.22U_0402_10V4Z A1 B12
2 GND GND
PD@
<56> USB3_A_TTX_C_DRX_P0 A2 B11 USB3_A_TRX_DTX_P0 <56>
A3 SSTXP1 SSRXP1 B10
<56> USB3_A_TTX_C_DRX_N0 SSTXN1 SSRXN1 USB3_A_TRX_DTX_N0 <56>

<43> PD_RESET 1 2 TBT@ CT94 1 2 0.47U_0402_25V6K A4 B9 TBT@ CT96 1 2 0.47U_0402_25V6K


VBUS VBUS
RT109 TBTA_CC1 A5 B8 TBTA_SBU2
0_0201_5% CC1 RFU2
1

TBT_A_USB20_L_PT A6 B7 TBT_A_USB20_L_NB
@ TBT_A_USB20_L_NT A7 DP1 DN2 B6 TBT_A_USB20_L_PB
RT108 DN1 DP2

Bottom
0_0201_5% TBTA_SBU1 A8 B5 TBTA_CC2
RFU1 CC2

TOP
2

TBT@ CT95 1 2 0.47U_0402_25V6K A9 B4 TBT@ CT97 1 2 0.47U_0402_25V6K


VBUS VBUS

<56> USB3_A_TRX_DTX_N1 A10 B3 USB3_A_TTX_C_DRX_N1 <56>


A11 SSRXN2 SSTXN2 B2
<56> USB3_A_TRX_DTX_P1 SSRXP2 SSTXP2 USB3_A_TTX_C_DRX_P1 <56>
A12 B1
GND GND

1 4
GND GND 6
2 GND 3
5 GND GND
GND
CONN@ JAE_DX07S024JJ2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2016/01/06 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PD+USB3.1 type C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 58 of 80
5 4 3 2 1
A B C D

ACES_51202-00901-001 EMI@ PL1


SMB3025500YA_2P
VIN
11 1 2 +3VALW
11 10 ADPIN EMI@ PL3
10 9 SMB3025500YA_2P
9 8 1 2
8 7

1000P_0402_50V7K

1000P_0402_50V7K
7 6

2.2K_0402_5%
100P_0402_50V8J

100P_0402_50V8J
6

1
5
5

2
EMI@ PC1

EMI@ PC2

EMI@ PC3

EMI@ PC4
4
4 3

2
3

PR3
2
2 1 PR4
1 33_0402_5%

1
1 3 PSID-3 1 2 PS_ID <43>

S
1 PJPDC1 1
@ PQ7
FDV301N_G 1N SOT23-3

G
2
100K_0402_1%
2
EMI@ PL2
PR8

PR6
BLM15HG601SN1D_2P
PSID 2 1 PSID-2 2 1
+5VALW

Adapter 240W Adapter connector:

1
10K_0402_1%

1
C
240W/19.5V=12.3A 1. X PSID-1 2 PQ2
2. P S ID B

15K_0402_1%
S TR METR3904W -G NPN SOT323-3

2
3 . GN D E PR2

3
PR9
4 . GN D @ 1K_0402_1%

1
BATT+ 5 . GN D PD1 @ JRTC1 PD5
6 . A DP IN SM24_SOT23 1 2 1 JRTC1 2

1
1 2 1
BATT++ 7 . A DP IN 2 +RTC_CELL
BATT+

EMI@ PL4 3 3
SMB3025500YA_2P 8 . A DP IN G1 4 +3VLP
1 2 9. X G2 BAS40CW _SOT323-3
10.X
EMI@ PL5 ACES_50271-00201-001
SMB3025500YA_2P 11.X
1 2 BATT++
RTC
100P_0402_50V8J
1

1
1000P_0402_50V7K
0.022U_0402_25V7K

0.01UF_0402_25V7K
1

PC7

EMI@ PC8

EMI@ PC9
EMI@ PC6

2
2

1
PQ3 6
EMI@

2
PD2 PD3 SI3457CDV-T1-GE3_TSOP6 5 2

TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3 2
EMI@ EMI@ 4 1
B+_BIAS

D
B+

100K_0402_1%

0.1U_0402_25V6
0.22U_0603_25V7K
2

G
1

1
PR12

PC10

PC11
3
2

2
2
VCIN_ BATT_TEMP
@ PBATT1
1 VCIN_ BATT_TEMP <43,62>
+5VALW PR13
1 2 100K_0402_1%
2 3 1 2 VSB_N_001
3 4

2
CLK_SMB 1

1VSB_N_003
2 PR16
4 5 DAT_SMB 1 PR19 2 100_0402_1% 10K_0402_1% PR14
5 6 BATT_PRS 1 PR21 2 100_0402_1% 1 2 100K_0402_1%
6 7 SYS_PRES PR22 100_0402_1% +3VALW
7 8

1
8 9 @ PR17 D
9 10 2 1 VSB_N_002 2 PQ4
10 11 <43,63> POK G L2N7002W T1G 1N SC-70-3
11 0_0402_5%

.1U_0402_16V7K
S
EC_SMB_CK1 <43,62>

3
1

PC12
ACES_50493-0110N-001 Battery 92W
92W/12V=7.7A @

2
Battery connector: EC_SMB_DA1 <43,62>
1.BATT++
2.BATT++
3.BATT++
3
4.BATT++ Adapter protection For PROCHOT VIN CPU thermal protection 3

<43,62> ADP_I
5.CLK_SMB VCIN0_PH
6.DAT_S MB Erp lot 6 circuit
7.BATT_PRS <9,43,62> H_PROCHOT#
Trig = 1V
PR732
8.SYS_P R ES 93 +/- 3 degree C

1
3.3K_0402_1%
9.BAT_ALERT 240W Recover = 2.28V +3VALW +3VLP

2
10. GN D 50 +/- 3 degree C
VCIN1_PH= 1.26V PR729

14.7K_0402_1%

12.1K_0402_1%
11. GN D

2
PC14 1M_0402_1%
12. GN D reset = 1.17V

3 2

PR24

PR25
1U_0603_25V6K
1

D
13. GN D 180W

1
VCIN_ BATT_TEMP 1 2 2

PQ710B
PQ8 PR23
VCIN1_PH=0.97V <18,37,43,62> VCIN1_AC_IN

S TR 2N7002KDW 2N SOT-363-6
G L2N7002W T1G 1N SC-70-3 110K_0402_1% @

1
1
5
reset = 0.88V
100K_0402_1%

S
3
2

PR731
<43> VCIN0_PH1
1

2
PR28

200K_0402_1%

4
PQ710A

1
1M_0402_1%

S TR 2N7002KDW 2N SOT-363-6
2 PR730 PH1
1

100K_0402_1%_B25/50 4250K

1
1
<43> VCIN1_ADP_PROCHOT

1
0.1U_0402_25V6

2
PC724 2
2

PR26 PC13 @
<43> ECAGND
100K_0402_1% .1U_0402_16V7K
1
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-DCIN / BATT CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: W ednesday, September 07, 2016 Sheet 61 of 80
A B C D
A B C D

PQ700
CC = 4.1A

1
D L2N7002WT1G 1N SC-70-3
2
VIN PQ707 P1 S
G
PR701 PR700 CV = 17.7V

3
MDU1512RH_POWERDFN56-8-5 3M_0402_5% 1M_0402_1%
1
2
2 1 2 1
P2
5 3
Iada=0~9.23A(180W)
1000P_0402_50V7K
1
PC722

4
PR726
2

1 2 ADP_I = 40*Iadapter*Rsense
4.7_0402_5%
1
PQ702 1

PQ701 MDU1512RH_POWERDFN56-8-5 PR702


B+ PQ703 AON7506_DFN33-8-5

MDU1512RH_POWERDFN56-8-5 1 0.005_1206_1% 1
1 2 2
2 3 5 1 4 5 3 PQ703_S
5 3

0.1U_0402_25V6
2 3

1
1000P_0402_50V7K

PC701

4
4
1
PC723

2
PR725 CHG_B+

CSSP_1
1 2 PD700
PJP700 @

1CSSN_1
2

4.7_0402_5% 2 1 2 PC725
BATT++ 1 2 1 2
1 JUMP_43X39

1U_0402_25V6K

1000P_0402_50V7K
10U_0805_25V6K~D

10U_0805_25V6K~D
1

2200P_0402_50V7K
PR703 @
PC702 0.022U_0603_25V7K

0_0402_5%
0_0402_5%

0.1U_0402_25V6
1

1
3 0.047U_0402_25V7K

@ PR704

EMI@ PC703

PC705

PC706

EMI@ PC727

EMI@ PC726
VIN

EMI@ PC704
1 2 PR733 PR734
10K_0402_1% 10_0402_1%

2
4.12K_0603_1%

4.12K_0603_1% BAT54CW-7-F SOT-323


1

PC707 PC708
PC709

2
0.1U_0603_25V7K 0.1U_0402_25V6

10_1206_1%
PR706
PR705

BATDRV_CHG 2

2
1

1
1 2 1 2 1 2

2.2_0603_5%
PR707

PR708

2
0.01UF_0402_25V7K +3VALW
2

BATSRC_CHG
PC710
2.2U_0603_16V6K

REGN_CHG 1
PQ704

5
1 2

BTST_CHG

20K_0402_1%

1
DH_CHG

DL_CHG
LX_CHG

AON6414AL_DFN8-5
2
PC711 PR710

PR709
1U_0603_25V6K 6.49K_0402_1%
DH_CHG 4

1 2
PU700 PQ705

28

27

26

25

24

23

22

1
D
L2N7002WT1G 1N SC-70-3
2TB_STAT#_CHG

VCC

REGN

GND
BTST
PHASE

HIDRV

LODRV
G PR712

3
2
1
29 S PL700 0.01_1206_1%
CSSP_2

CSSN_2
2 2

3
PWPD 2.2UH_PCMB104T-2R2MS_12A_20%
PR711 LX_CHG 1 2 1 4 BATT+
1 21 1 2
ACN ILIM 2 3

1
1.62K_0402_1%

5
2 20 PR713

CSON_1
CSOP_1
ACP SRP 4.7_1206_5%

AON7518_DFN8-5
EMI@

22U_0805_25V6M

22U_0805_25V6M

22U_0805_25V6M
CMSRC_CHG 3 19

2
CMSRC SRN

1
SNUB_CHG

PQ706

PC712

PC713

PC714
DL_CHG 4

1
ACDRV_CHG 4 18 BATDRV_CHG PC715

2
ACDRV BQ24780SRUYR_QFN28_4X4 BATDRV 680P_0402_50V7K
EMI@

2
5 17 BATSRC_CHG
<18,37,43,61> VCIN1_AC_IN

3
2
1
ACOK BATSRC
PR714
REGN_CHG 1 ACDET_CHG TB_STAT#_CHG
2
VIN 6 16
120K_0402_5%

100K_0402_1% ACDET TB_STAT#


324K_0402_1%
1

@ PR717 PC716 PC717 PC721


1

2 1 7 15 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6


PR715

IADP BATPRES#

1
<43,61> ADP_I 1 2 1 2 1 2
PR716

PROCHOT#
0_0402_5% PR718

CMPOUT
10K_0402_1%

CMPIN
100P_0402_50V8J

IDCHG
2

PMON

1
SDA
2

SCL
2

@ PR727 PR722
PC718

AC Det

2
10_0402_1%
Max:18.16V 0_0402_5% 1 2
1

10

11

12

13

14
Typ :17.98V

2
Min :17.8V +3VALW PR723
1

10_0402_1%
1

1 2 1 2
PR719
49.9K_0402_1%

PC719
0.01UF_0402_25V7K PC720
2

1
PR720 @
100P_0402_50V8J @ PR721

0_0402_5%
2

0_0402_5% PR724

0_0402_5%
<43,61> VCIN_ BATT_TEMP
3
ADPI = 0.005*40*IADP = 0.2 * IADP 3
2

0_0402_5%

2
PR728

Adapter = 240W
CP = 240W/19.5V*0.9 = 11.07A @
1

@
ADPI = 2.21V
Hybrid trigger = CP*107% = 11.85A
ADPI = 2.37V
<43,61>

<43,61>
EC_SMB_DA1

EC_SMB_CK1

IPCC= 240W/19.5V*0.95 = 11.69A


ADPI = 2.32V
<9,43,61>
H_PROCHOT#
<73>
I_SYS

IPCC(hybrid mode)= 240W/19.5V = 12.3A


ADPI = 2.46V
PROCHOT = 240W/19.5V+1 = 13.3A
ADPI = 2.66V

Adapter = 180W
CP = 180W/19.5V*0.9 = 8.30A
APDI = 1.66V
Hybrid trigger = CP*107% = 8.88A
ADPI = 1.77V
IPCC = 180W/19.5V*(1*0.95) = 8.77A
ADPI = 1.75V
IPCC(hybrid mode)= 180W/19.5V = 9.23A
ADPI = 1.85V
PROCHOT = 180W/19.5V+1 = 10.23A
4
ADPI = 2.04V 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 62 of 80
A B C D
A B C D E

Input Current: 7.5A


3.3V*10A/0.85/12V=2.23
5V*10A/0.85/12V=5.27
+3VLP
PC101
4.7U_0603_6.3V6K
1 2

1 1
Output capacitor ESR need follow
below equation to make sure feed back
loop stability
ESR=20mV*L*fsw/2V
PR101 PR102
6.49K_0402_1% 15.8K_0402_1%
1 2 1 2
VFB=2V VFB=2V

PR103 PR104
10K_0402_1% 10K_0402_1%
1 2 1 2

1
3/5V_B+
PR105 PR106
69.8K_0402_1% 68.1K_0402_1%
POK need pull high, it
PJP103@
B+ will pull high on VS

2
3/5V_B+

10U_0805_25V6K~D

10U_0805_25V6K~D
1 2
1 2 transfer circuit

1
1000P_0402_50V7K
1U_0402_25V6K

FB_3V

FB_5V

PC114

PC102
JUMP_43X39
2200P_0402_50V7K

CS2

CS1
10U_0805_25V6K~D

10U_0805_25V6K~D
0.1U_0402_25V6

1
EMI@ PC107

EMI@ PC115

2
1

5
EMI@ PC100

EMI@ PC103

PC104

PC113

PQ100
AON7518_DFN8-5
2

5
<43,61> POK
2

AON7518_DFN8-5
PU100
2 2

CS2

VFB2

VREG3

VFB1

CS1
4 21
3V_EN PAD

PQ102
6
EN2 20 5V_EN 4
EN1 @ PR107
7 200_0402_1%
DCR = 14/15mohm
1
2
3

PGOOD 19 1 2
VCLK
DCR = 14/15mohm

3
2
1
PL101 LX_3V 8 TPS51225CRUKR_QFN20_3X3
S COIL 1.5UH +-20% 9A 7X7X3 PC105 PR108 SW2 18 LX_5V PL102
1 2 LX_3V 0.1U_0402_25V6 0_0603_5% SW1 PR109 PC106 S COIL 1.5UH +-20% 9A 7X7X3
+3VALWP 1 2 1 2 BST_3V 9 0_0603_5% LX_5V 1 2
VBST2 BST_5V +5VALWP
17 1 2 1 2
VBST1
1

UG_3V
4.7_1206_5%

680P_0603_50V8J 4.7_1206_5%
10

220U_D2_6.3VY_R15M
DRVH2 1

1
UG_5V
EMI@ PR110

EMI@ PR111
16
220U_D2_6.3VY_R15M

VREG5
1

DRVL2

DRVL1
DRVH1 +

PC108
0.1U_0402_25V6

VO1
5

5
VIN
+
PC118

AON7534_DFN3X3-8-5

AON7534_DFN3X3-8-5
2

2
PQ101

11

12

13

14

15

2
2

PQ103
680P_0603_50V8J

4 LG_3V LG_5V 4
1

1
EMI@ PC109

EMI@ PC110
+5VALWP
2

2
3/5V_B+
1
2
3

3
2
1
3.3VALWP VL
TDC=9A

1
Peak Current 12.9A PC111
3
OCP current 15.48A 4.7U_0603_6.3V6K
3

2
FSW=355kHz OVP=Vout*(112.5%~117.5%)
TYP MAX 5VALWP
H/S Rds(on) : 11.2mohm 14mohm OCP=Vtrip/Rdson+Iripple/2 TDC=9.4A
L/S Rds(on) : 6.7mohm 8.5mohm Vtrip=Ics(min)*Rcs/8+1mV Peak Current 13.46A (11.66 + 1.8)
Vcs=Ics*vcs should be in the range of 0.2~2V OCP current 16.2A
EN FSW=300kHz
Rising=1.6~0.3V Vout=VFB*(1+Rtop/Rbot) TYP MAX
VFB=2V H/S Rds(on) : 11.2mohm 14mohm
@ PR100 0_0402_5%
3V_EN 1 2 L/S Rds(on) : 6.7mohm 8.5mohm

@ PR112 0_0402_5%
5V_EN 1 2 PJP100 PJP102
+5VALWP 1 2 +5VALW +3VALWP 1 2 +3VALW
1 2 1 2
PD100 PR113 JUMP_43X118 @ JUMP_43X118 @
2 2.2K_0402_5% PJP101 PJP104
<43> EC_ON 1 1 2 1 2 1 2
3 1 2 1 2
<35> USBCHG_DET_D JUMP_43X118 @ JUMP_43X118 @
BAS40CW_SOT323-3

@ PR114 0_0402_5%
1 2
4 <43> VCOUT0_MAIN_PWR_ON# 4
@ PD101 @ PR115
LL4148_LL34-2 1M_0402_1%
2 1 1 2
VIN
200K_0402_1%

4.7U_0603_6.3V6K
1
PR116

PC112

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title
2

PWR-3.3VALWP/5VALWP
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 63 of 80
A B C D E
5 4 3 2 1

Input Current: 1A
1.2V*8.88A/0.85/12V=1

D D

Pin19 need pull separate from +1.2VP.


If you have +1.2V and +0.6V sequence question, 0.6VSP
you can change from +1.2VP to +1.2VS. TDC 1.05A
PJP203@
B+ 1 2 1.2V_B+ PR200 Peak Current 1.5A
1 2 2.2_0603_5%

2200P_0402_50V7K
0.1U_0402_25V6
JUMP_43X39 BST_1.2V 1 2 BOOT_1.2V

1U_0402_25V6K

1000P_0402_50V7K
10U_0805_25V6K~D

10U_0805_25V6K~D
+1.2VP
1

1
EMI@ PC200

EMI@ PC201

PC202

PC203

EMI@ PC208

EMI@ PC216
+0.6VSP
2

2
DH_1.2V

2
SW _1.2V

10U_0805_6.3V6K

10U_0805_6.3V6K
1
PQ200

1
PC204

PC205

PC206
5
AON7408L_DFN8-5
0.1U_0603_25V7K

16

17

18

19

20
2
C PU201 C

2
VLDOIN
PHASE

UGATE

BOOT

VTT
21
PAD
4 DL_1.2V 15 1
LGATE VTTGND

14 2
PL201 PR201 PGND VTTSNS

1
2
3
1UH_11A_20%_7X7X3_M 20.5K_0402_1%
1 2 1 2 CS_1.2V 13 3
+1.2VP PC207 CS RT8207PGQW _W QFN20_3X3 GND
1

1U_0603_10V6K

5
1 2 12 4 VTTREF_1.2V
220U_D2 SX_2VY_R9M

220U_D2 SX_2VY_R9M

@EMI@ PR202 PQ201 PR203 VDDP VTTREF


1 1
4.7_1206_5% AON7506_DFN33-8-5 5.1_0603_5%
+ + 1 2 VDD_1.2V 11 5
PC209

PC215

+5VALW +1.2VP
1 2

VDD VDDQ

1
PGOOD
4 PC210

2.2_0603_5%

TON
1

2
2 2 0.033U_0402_16V7K
1.2VP @EMI@ PC211

FB
S5

S3

2
680P_0402_50V7K PC212

PR204
TDC=7.66A
2

1U_0603_10V6K

10

6
Ipeak=10.94A
1
2
3

OCP=13.12A PR213??60K

1
Switching Frequency: 285kHz

EN_0.6VSP
PR205

EN_1.2V
12K_0402_1%
+1.2VP

TON_1.2V
1 2
1 2
B +3VALW B
OVP: 110%~120% PR206

1
@ PR210 100K_0402_1% 887K_0402_1%

20K_0402_1%
VFB=0.75V, Vout=1.2V

1
1.2V_B+ 1 2

PR207

60.4K_0402_1%
TYP MAX PR213
H/S Rds(on) : 23.2mohm 27.8mohm 60.4K_0402_1%

PR215
L/S Rds(on) : 13mohm 15.8mohm @ PR208

2
S TR 2N7002KDW 2N SOT-363-6
2 1
<43,45> SYSON

2
@

6
0_0402_5%

1
@ PJP201 @ PC213

PQ202A
Mode Level +0.6VSP VTTREF_1.2V 1K_0402_1%
1 2 0.1U_0402_10V7K
S5 L off off 1 2 2 2 1 XMP1 <20>

2
S3 L off on JUMP_43X118

1
S0 H on on @ PJP200

0.1U_0402_25V6
PR212

1
1 2 @ PR209

PC217
+1.2VP 1 2 +1.2V_DDR
0_0402_5%
Note: S3 - sleep ; S5 - power off

2
S TR 2N7002KDW 2N SOT-363-6
JUMP_43X118 1 2
<29,43,45,56,67,76> SUSP#

3
PJP202@ @ PR211

PQ202B
1 2 2 1
+0.6VSP 1 2 +0.6VS <9> SM_PG_CTRL
JUMP_43X39 0_0402_5% 5 2 1 XMP2 <20>

1
PR214

0.1U_0402_10V7K

1
1K_0402_1%

4
PC214

PC218
0.1U_0402_25V6
@

2
@ @
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.2VP/0.6VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: W ednesday, September 07, 2016 Sheet 64 of 80
5 4 3 2 1
A B C D

1 1

+3VALW
@ PR1301
2 1 +2.5VSP_ON
<18,43,45> PM_SLP_S4#

1
0.1U_0402_16V7K
1
0_0402_5% @ PR1300

1M_0402_1%
2 2

1
PR1302

PC1301
100K_0402_1%

Input 0.7A

2
2 @

9
PU1300
@ PJP1301 1 8

GND
2 PGOOD GND 7
+5VALW 1 2 +2.5VSP_VIN 3 EN ADJ 6
1 2 4 VIN VOUT 5 +2.5V_MEMP
VDD NC

1
JUMP_43X79
1

1
RT9059GSP_SO8
22U_0603_6.3V6M

22U_0603_6.3V6M

1
PC1306

PC1300
PR1304

22P_0603_50V8

1
PC1305

22U_0603_6.3V6M

22U_0603_6.3V6M
21.5K_0402_1%
2

PC1303

PC1304
2
2

2
1
PR1305
10K_0402_1%
Rdown
1
1U_0603_6.3V6M

2
PC1307

@ PJP1300

3 1 2 3

+2.5V_MEMP 1 2 +2.5V_MEM
JUMP_43X79

+2.5V_MEM
TDC 0.63A
Peak Current 0.9A
OCP Current 3.5A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+2.5V_MEM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: W ednesday, September 07, 2016 Sheet 65 of 80
A B C D
5 4 3 2 1

PJP301@
+1VALW P_B+ 1 2
1 2 B+
JUMP_43X39

1U_0402_25V6K
2200P_0402_50V7K

1000P_0402_50V7K
0.1U_0402_25V6

10U_0805_25V6K~D

10U_0805_25V6K~D
1

1
EMI@ PC301

EMI@ PC302

PC303

PC304

EMI@ PC310

EMI@ PC311
+3VALW

2
@
Input Current: 0.9A

5
1V*9.41A/0.85/12V=0.9

AON7408L_DFN8-5
PR301
D 100K_0402_1% D

PQ300
<43> +1VALW P_PGOOD
4

2
PR302 PC305
PU300 2.2_0603_5% 0.1U_0603_25V7K
PR303 1 10 BST_+1VALW P 1 2 1 2

3
2
1
200K_0402_1% PGOOD VBST
@ PR300 1 2 TRIP_+1VALW P 2 9 UG_+1VALW P PL300
0_0402_5% TRIP DRVH 1UH_11A_20%_7X7X3_M
1 2 EN_+1VALW P 3 8 SW _+1VALW P 1 2
<43,45> PCH_PW R_EN
FB_+1VALW P 4
EN SW
+1VALWP
7
VFB V5IN
+5VALW

1
0.1U_0402_16V7K
RF_+1VALW P 5 6 LG_+1VALW P

AON7506_DFN33-8-5

220U_D2 SX_2VY_R9M

220U_D2 SX_2VY_R9M
TST DRVL

1
PR305 @EMI@

@ PC300
1 1

1
11 4.7_1206_5%
TP +1VALW

1
+ +

PQ301

PC307

PC306
2

2
PR306 TPS51212DSCR_SON10_3X3 PC308
1U_0603_6.3V6M
4 TDC 9.41A
470K_0402_1%
Peak Current 13.45A

1
PC309 @EMI@ 2 2

2
680P_0402_50V7K OCP current 16.14A
FSW=290kHz

3
2
1

2
Switching Frequency: 290kHz
C PR307 C
4.42K_0402_1%
OVP: 120%-130%
1 2 VFB=0.7V
TYP MAX
H/S Rds(on) : 27mohm 34mohm
1

L/S Rds(on) : 13mohm 15.8mohm


PR308
10K_0402_1%
2

@ PJP300
+1VALWP 1 2 +1VALW
1 2
JUMP_43X118

@ PJP302
1 2
1 2
JUMP_43X118

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: W ednesday, September 07, 2016 Sheet 66 of 80
5 4 3 2 1
5 4 3 2 1

D D

+1.8VSP
TDC 2.26A
Peak Current 3A
OCP current 4A
FSW=1MHz
TYP MAX
Choke DCR 0.045mohm , 0.059mohm
C C

Input 0.4A
PU802
PJP802@ 11
+5VALW 1 2 10 TP 1
1 2 PVIN NC PL801
10U_0603_6.3V6M

JUMP_43X39 9 2 LX_+1.8VGS 1 2
PVIN LX
+1.8VSP
2
PC810

8 3
1U_0603_6.3V6M

SVIN LX 1UH_1239AS-H-1R0M-P2_3A_20%

1
1

7 4 @EMI@ PR809
PC814

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
NC PGOOD

1
4.7_0603_5%

PC812

PC813

PC815
6 5
1

FB EN

2
2
SNB_+1.8VGS
PR820
Rup RT8061AZQW _W DFN10_3X3

1
10K_0402_5%
PR810 @EMI@ PC806
2 1 FB_+1.8VGS 680P_0402_50V7K
+1.8VSP

2
22.1K_0402_1%
1

1 2 +3VS
10.7K_0402_1%

Rdown

PC816
PR811

22P_0603_50V8
Vout=0.6V* (1+Rup/Rdown)
2

B B

PJP803 @
<29,43,45,56,64,76> SUSP#
@ PR807 +1.8VSP 1 2 +1.8VS
2 1 1V8_ENP 1 2

0_0402_5% JUMP_43X79
0.1U_0402_16V7K
1

PC811
1

PR808
1M_0402_1%
2

@
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.8VSP/+1.8VGSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: W ednesday, September 07, 2016 Sheet 67 of 80
5 4 3 2 1
5 4 3 2 1

D
+3V3_SYS D

2
PR821
+1.0VS_VGAP
Input 0.7A 10K_0402_5%
TDC 3A
Peak Current 3A

1
+1.0VS_VGA_PGOOD <55>

B+ 1
PJ800 @
2 2
PU800
9 PR806 PC808
OCP current 6A
1 2 IN PG 0_0603_5% 0.1U_0603_25V7K FSW=1MHz

10U_0805_25V6K~D
JUMP_43X39 3 1 1 2 1 2
IN BS PL800

2
PC800
2 1 4 6 LX_1.0VS_VGAP 1 2
<55,70> NVVDD2_EN
@ IN LX
+1.0VS_VGAP

330P_0402_50V7K
1

1
PR8217 5 19 PR804
IN LX 1UH_PCMB042T-1R0MS_4.5A_20%

1
0_0402_5% 21.5K_0402_1%

PC809
<43> EC_PEX_VDD_EN
7 20
Rup

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
GND LX

1
2 1

PC804

PC805

PC818

PC819
2
@ 8 14 FB_1.0VS_VGAP

2
PR823 GND FB

2
0_0402_5% 18 17
GND VCC

1
2 1 PEX_VDD_ENP 11 10 @EMI@ PR803

2.2U_0402_16V6K
<55,70> NVVDD2_PGOOD EN NC 4.7_0603_5%

1
PR801 13 12

PC803
0.01U_0402_16V7K

ILMT NC
1

30K_0402_1%
PC801

2
1

1
C PR802 15 16 SNB_1.0VS_VGAP C

31.6K_0402_1%

Rdown
2
1M_0402_1% BYP NC

PR805
1
21
2

PAD @EMI@ PC802


2

SY8286RAC_QFN20_3X3 680P_0402_50V7K

2
+3VALW
2

PR812 @
0_0402_5%
Vout=0.6V* (1+Rup/Rdown)
1

PJP801 @
2

+1.0VS_VGAP 1 2 +PEX_VDD
@ PR813 1 2
0_0402_5% +3VALW JUMP_43X79
1

1
1U_0603_6.3V6M

PC817
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.0VS_VGA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: W ednesday, September 07, 2016 Sheet 68 of 80
5 4 3 2 1
GPU_B+ NVVDD_B+

B+ PR6100 PR6101

1 4 1 4

2 3 2 3

0.005_2512_1% 0.005_2512_1% 1 1 1

33U_D2_25VM_R40M

33U_D2_25VM_R40M

33U_D2_25VM_R40M

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
2

2
+ + +

PC6122

PC6123

PC6124

PC6130

PC6131

PC6132
1

1
2 2 2
+5VS

4.7U_0603_6.3V
1
PC6100
<49> CSSP_B+ <49> CSSN_B+<49> CSSP_NVVDD <49> CSSN_NVVDD

2
NVVDD_LG1 NVVDD_LG2

1U_0402_25V6K

0.1U_0402_25V6
1000P_0402_50V7K

2200P_0402_50V7K

10U_0805_25V6K~D

10U_0805_25V6K~D
NVVDD_HG1

EMI@ PC6101

EMI@ PC6102

EMI@ PC6103

EMI@ PC6104
1

1
NVVDD_SW1 NVVDD_SW2

PC6105

PC6106
EN can't float PC6108

1
PC6107 0.22U_0603_25V7K NVVDD_SW1

2
1

2
0.22U_0603_25V7K PQ6100 PQ6101

AON6992_DFN5X6D-8-7
G1

D1

G1

D1
2

AON6992_DFN5X6D-8-7
+3V3_SYS +NVVDD1

2
1 2 1 2 +3VS
PU6100 7 7

20

19

18

17

16
D2/S1 D2/S1

2
PR6103 PR6102 NCP81278MNTXG_QFN20_3X3
30K_0402_5% 1M_0402_1% PR6104 PR6105

PH1

LG1

LG2

PH2
PVCC

G2

G2
2.2_0603_1% 2.2_0603_1%

S2

S2

S2

S2

S2

S2
PR6107
NVVDD_BST1 1 15 NVVDD_BST2
10K_0402_5%

3
BST1 BST2 PL6100
NVVDD_HG1 2 14 NVVDD_HG2 0.22UH_MMD-10DZIR22M-R1L__50A_20%

1
HG1 HG2 1 4
NVVDD1_EN 3 13 NVVDD1_PGOOD <46,55,70>
<55> NVVDD1_EN EN PGOOD NVVDD_LG1 2 3

2200P_0603_50V7K
4 12 NVVDD_COMP 2 1 PR6129
PSI COMP/OPT 1

470U_D2_2VM_R4.5M~D
@ PR6110 0_0402_5% 1 2 NVVDD_B+

82.5K_0402_1%
2

2
1 2 5 11 PR6109 +

PC6125

PC6129
<46> NVVDD_VID VID FB 75K_0402_1%

VIDBUF

FBRTN
2.2_0805_1%

REFIN

VREF

PR6112
GND

1
2

FS

2
@ PR6132 5.1K_0402_1%

2 1
1 2 PC6109
+1.8VS

21

10
PC6110 10P_0402_25V8J

1
@ PR6108

1U_0402_25V6K

0.1U_0402_25V6
1000P_0402_50V7K

2200P_0402_50V7K

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
1 2 NVVDD1_PSI 330P_0402_50V8J NVVDD_HG2

EMI@ PC6111

EMI@ PC6112

EMI@ PC6113

EMI@ PC6114
<46> NVVDD_PSI

2
PC6115

PC6133

PC6116

PC6134

PC6135
0_0402_5%

2
NVVDD_VIDBUF

1
1

2
1 2 PR6113 PQ6103 PQ6102
49.9_0402_1%

G1

D1

G1

D1
1

2
@ PR6133 0_0402_5% +NVVDD1

AON6992_DFN5X6D-8-7
PR6117

2 1

AON6992_DFN5X6D-8-7
PR6115 NVVDD_SW2 7 7
71.5K_0402_1% D2/S1 D2/S1
10K_0402_5%
R1 R4
1

PC6117
6.19K_0402_1%

1
PC6119
R3
PR6119

PR6120

G2

G2
47P_0402_50V8J

S2

S2

S2

S2

S2

S2
16.5K_0402_1%

1
1

NVVDD_VREF 2 1
4700P_0402_50V7K
PC6118
4.32K_0402_1%

3
1000P_0402_25V PL6101
PR6118
2

0.22UH_MMD-10DZIR22M-R1L__50A_20%
PC6120 1 4
2

2200P_0603_50V7K
PR6130
1

0.01U_0402_16V @ PR6122 @ PR6123 NVVDD_LG2 2 3


0_0402_5% 1 2
R5 0_0402_5%
2

2
PC6126
1

1
PR6125 2.2_0805_1%
309_0402_1%

1
PR6126 100_0402_5%
1

2 1
+NVVDD1
R2
2 1 NVVDD_VCC_SENSE <49>
+NVVDD1
C PR6127 Avoid high dV/dt TDC 62A
1500P_0402_50V7K

20.5K_0402_1% NVVDD_VSS_SENSE <49>


Peak Current 164A
1

PC6121

PR6128
2
100_0402_5%
1
OCP=179A
TYP MAX
2

@
H/S Rds(on):6.7mohm ,8.5mohm
L/S Rds(on):2mohm ,2.5mohm
Place close to GPU

N17E_G1 VDD VDDS


TDC 62 21
Peak 164 50

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+NVVDD1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 69 of 80
1 2 3 4 5

GPU_B+
NVVDDS_B+
PR6200

1 4

2 3

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
2

2
PC6219

PC6220

PC6221
0.005_2512_1% 1

33U_D2_25VM_R40M
1

1
+

PC6217
A 2 A
+5VS
<49> CSSP_NVVDDS <49> CSSN_NVVDDS

4.7U_0603_6.3V
1
PC6200

1U_0402_25V6K

0.1U_0402_25V6
1000P_0402_50V7K

2200P_0402_50V7K

10U_0805_25V6K~D

10U_0805_25V6K~D
2
NVVDDS_HG1

EMI@ PC6201

EMI@ PC6202

EMI@ PC6203

EMI@ PC6204
1

1
PC6205

PC6206
2

2
1

2
NVVDDS_LG1 PQ6200 PQ6201

AON6992_DFN5X6D-8-7
G1

D1

G1

D1
NVVDDS_SW1 +NVVDD2

AON6992_DFN5X6D-8-7
PC6207 NVVDDS_SW1 7 7
EN can't float D2/S1 D2/S1

1
0.22U_0603_25V7K
<46,55,69> NVVDD1_PGOOD

G2

G2
S2

S2

S2

S2

S2

S2
2
1 2 1 2 +3V3_SYS
PU6200

20

19

18

17

16

3
2
PR6201 PR6202 NCP81278MNTXG_QFN20_3X3 PL6200
30K_0402_5% 1M_0402_1% PR6203 0.22UH_MMD-10DZIR22M-R1L__50A_20%

PH1

LG1

LG2

PH2
PVCC

2
2.2_0603_1% @ 1 4
PR6205
NVVDDS_BST1
1 15 NVVDDS_LG1 2 3
10K_0402_5%

2200P_0603_50V7K
PR6226

1
BST1 BST2
NVVDDS_HG1 2 14 1 2

1
HG1 HG2

2
PC6218
NVVDD2_EN 3 13 NVVDD2_PGOOD <55,68>
<55,68> NVVDD2_EN EN PGOOD 2.2_0805_1%

1
NVVDD2_PSI 4 12 NVVDDS_COMP 2 1
PR6229 @ PR6208 PSI COMP/OPT

82.5K_0402_1%
2
@ 0_0402_5% 1 2 5 11 PR6207
<46> NVVDDS_VID VID FB
1 2 @ 51.1K_0402_1%

VIDBUF

FBRTN
+1.8VS

REFIN

VREF
0_0402_5%

PR6210
GND

FS

2
Avoid high dV/dt +NVVDD2

2 1
1 2 PC6209
<46> NVVDDS_PSI
21

10
B PC6210 10P_0402_25V8J TDC 21A B

1
PR6228
5.1K_0402_1% 330P_0402_50V8J Peak Current 50A

1
OCP=89A
1

TYP MAX

2
PR6230 NVVDDS_VIDBUF
5.1K_0402_1% PR6211 H/S Rds(on):6.7mohm ,8.5mohm
49.9_0402_1%
1 L/S Rds(on):2mohm ,2.5mohm

2
2

PR6213

2 1
240K_0402_1% PR6214
10K_0402_5%
R1 R4
1

PC6211
6.19K_0402_1%

1
PC6213
R3
PR6216

PR6217

47P_0402_50V8J
16.5K_0402_1%

1
1

NVVDDS_VREF 2 1
4700P_0402_50V7K
PC6212
4.32K_0402_1%

1000P_0402_25V
PR6215
2

PC6214
2

2
1

0.01U_0402_16V @ PR6219 @ PR6220


0_0402_5%
R5 0_0402_5%
2

PR6222
309_0402_1%
PR6223 100_0402_5%
1

2 1 +NVVDD2
R2
2 1 NVVDDS_VCC_SENSE <49>
1500P_0402_50V7K

PR6224
C 20.5K_0402_1% Avoid high dV/dt NVVDDS_VSS_SENSE <49>
1
PC6215

PR6225 100_0402_5%
2 1
2

C C

Place close to GPU

D D

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+NVVDD2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 70 of 80
1 2 3 4 5
5 4 3 2 1

PJP8200@
+1.35VS_B+ 1 2
+5VALW 1 2 GPU_B+
JUMP_43X39

1U_0402_25V6K

1000P_0402_50V7K
10U_0805_25V6K~D

10U_0805_25V6K~D

1
EMI@PC8202

EMI@PC8220

EMI@PC8221
2200P_0402_50V7K

0.1U_0402_25V6
2

1
EMI@PC8201

PC8203

PC8204
PR8200

2
AON6992 2N DFN5X6D
2.2_0603_5%

2
1
RT8812_PVCC

PQ8200
D D
PC8200

1
PC8205 2.2U_0603_16V6K

D1

G1
2 1PWR_VGA_CORE_TON_1 PL8200

18
PU8200 1UH_11A_20%_7X7X3_M
0.1U_0402_25V6 7 1 2
+1.35VS_VGAP

PVCC
PR8201 PR8202 D2/S1

1
2.2_0402_1% 383K_0402_1%
2 1 2 1 PWR_VGA_CORE_TON 9 2 PWR_VGA_CORE_UGATE1

G2
S2

S2

S2
+1.35VS_B+ TON UGATE1 PC8206 PR8203@EMI@

220U_D2 SX_2VY_R9M

220U_D2 SX_2VY_R9M
PR8204 PR8205 2.2_0603_1% 0.22U_0603_25V7K 4.7_1206_5% 1 1

6
2 1 13 1 PWR_VGA_CORE_BOOT12 1PWR_VGA_CORE_BOOT1_1 2 1
+1V8_AON

1 2
PGOOD BOOT1 + +

PC8207

PC8208
100K_0402_1% PC8209@EMI@
<46,55> +1.35VS_VGA_PGOOD FBVDD/Q_ENP 3 20 PWR_VGA_CORE_PHASE1 680P_0402_50V7K
+1.35VS_VGAP
EN PHASE1 2 2 Vout = 1.55V

2
@ PR8219
+3VS
1 2 4 19 PWR_VGA_CORE_LGATE1 TDC 16.9A

1
PSI LGATE1
0_0402_5% PR8220 @ PC8211 2
PR8206
1
Peak Current 24.2A
<55> FBVDD/Q_EN
@ PR8216 10K_0402_5% 8.25K_0402_1%
OCP=36.3A

2
1 2 0.1U_0402_25V6 FSW=400kHz

10U_0805_25V6K~D

10U_0805_25V6K~D
5 14 PWR_VGA_CORE_UGATE2

1
VID UGATE2 TYP MAX

AON6992 2N DFN5X6D
0_0402_5% PC8212

PC8213

PC8214
PR8207 2.2_0603_1% 0.22U_0603_25V7K
8 15 PWR_VGA_CORE_BOOT22 1PWR_VGA_CORE_BOOT2_1 2 1 H/S Rds(on):6.7mohm ,8.5mohm

2
VREF BOOT2
L/S Rds(on):1.8mohm ,2.3mohm
1

7 16 PWR_VGA_CORE_PHASE2
REFIN PHASE2

PQ8201
PR8208
10K_0402_1%

1
6 17 PWR_VGA_CORE_LGATE2
REFADJ LGATE2 PR8209

D1

G1
2

100_0402_5% PL8201
PWR_VGA_CORE_SS 11 12 1 2 1UH_11A_20%_7X7X3_M PJP8201
SS VSNS
2200P_0402_50V7K

7 1 2 +1.35VS_VGAP 1 2 +1.35VS_VGA
D2/S1 1 2
0.1U_0402_25V6

0.1U_0402_25V6

1
21 10 JUMP_43X118 @
GND RGND PJP8202

G2
S2

S2

S2
1

1
PR8210@EMI@ 1 2
PC8215

PC8218
PC8216

1 2
1

C @ 4.7_1206_5% C
34.8K_0402_1%

6
PR8215 PC8217 RT8812AGQW-GP JUMP_43X118 @
PR8211
2

1 2
47P_0402_50V8J
52.3K_0402_1% OPS
2

PC8219@EMI@
@ 680P_0402_50V7K
2

2
<49> FB_VDDQ_SENSE
3

DMN53D0LDW-7 2N SOT363-6
PQ8202B

PR8221
1 2 5
+3VALW
10K_0402_5%
4
DMN53D0LDW-7 2N SOT363-6
6

PQ8202A

@ PR8214
1 2 2
1

0_0402_5%
PC8222
0.1U_0402_25V6

MEM_VDD_CTL <46>
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.55V_VGAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D581P
Date: Wednesday, September 07, 2016 Sheet 71 of 80
5 4 3 2 1
D

0.3
Rev

80
X 7

of
Compal Electronics, Inc.

72
1uF_0402 X 16
22uF_0603_X5R

Sheet
LA-D581P
VGA DECOUPLING
470uF X 3
1

1
+NVVDDS

W ednesday, September 07, 2016


Document Number

Date:
Title

Size

PC6321 PC6343
PC6415
1U_0402_6.3V6K 1U_0402_6.3V6K
470U_D2_2VM_R4.5M~D
1 2 1 2
+
1

PC6320 PC6342
PC6363
1U_0402_6.3V6K 1U_0402_6.3V6K
470U_D2_2VM_R4.5M~D
1 2 1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

PC6319 PC6341
1U_0402_6.3V6K 1U_0402_6.3V6K PC6378
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
22U_0805_10V6M
2016/09/18

1 2 1 2
PC6318 PC6340 1 2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

2
1U_0402_6.3V6K 1U_0402_6.3V6K PC6362
22U_0805_10V6M
1 2 1 2
PC6317 PC6339 1 2
1U_0402_6.3V6K 1U_0402_6.3V6K PC6377
22U_0805_10V6M
1 2 1 2
PC6316 PC6338 1 2
1U_0402_6.3V6K 1U_0402_6.3V6K PC6376

Deciphered Date
22U_0805_10V6M

Compal Secret Data


1 2 1 2
PC6315 PC6337 1 2
1U_0402_6.3V6K 1U_0402_6.3V6K PC6361
22U_0805_10V6M
1 2 1 2
PC6314 PC6336 1 2
1U_0402_6.3V6K 1U_0402_6.3V6K PC6375
22U_0805_10V6M
1 2 1 2
1 2
PC6374
+NVVDD2

22U_0805_10V6M
1 2

2015/09/18
4.7uF_0603 X 9
47uF_0805 X 2
22uF_0603 X 4
10uF_0603X 23

1uF_0402 X 49
470uF X 4
3

3
+NVVDD

Security Classification
Issued Date
PC6391
470U_D2_2VM_R4.5M~D
PC6313 PC6335 PC6357
+
1

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K


1 2 1 2 1 2
PC6390
PC6312 PC6334 PC6356 PC6360
470U_D2_2VM_R4.5M~D
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 47U_0805_6.3V6M
+
1

1 2 1 2 1 2 1 2
PC6311 PC6333 PC6355 PC6373 PC6403
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 47U_0805_6.3V6M 10U_0603_6.3V6M
PC6389
1 2 1 2 1 2 1 2 470U_D2_2VM_R4.5M~D 1 2
PC6310 PC6332 PC6354 PC6372 PC6402 PC6414
+
1

2
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0805_6.3VAM 10U_0603_6.3V6M 10U_0603_6.3V6M
1

1 2 1 2 1 2 PC6388 1 2 1 2
470U_D2_2VM_R4.5M~D
PC6309 PC6331 PC6353 PC6371 PC6401 PC6413
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0805_6.3VAM + 10U_0603_6.3V6M 10U_0603_6.3V6M
1

2
1

1 2 1 2 1 2 1 2 1 2
4

4
PC6308 PC6330 PC6352 PC6370 PC6387 PC6400 PC6412
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0805_6.3VAM 4.7U_0603_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
1

2
1 2 1 2 1 2 1 2 1 2 1 2
PC6307 PC6329 PC6351 PC6359 PC6386 PC6399 PC6411
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0805_6.3VAM 4.7U_0603_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
1

2
1 2 1 2 1 2 1 2 1 2 1 2
PC6306 PC6328 PC6350 PC6369 PC6385 PC6398 PC6410
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC6305 PC6327 PC6349 PC6368 PC6384 PC6397 PC6409
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC6304 PC6326 PC6348 PC6367 PC6383 PC6396 PC6408
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC6303 PC6325 PC6347 PC6366 PC6382 PC6395 PC6407
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC6302 PC6324 PC6346 PC6358 PC6381 PC6394 PC6406
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC6301 PC6323 PC6345 PC6365 PC6380 PC6393 PC6405
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
5

5
PC6300 PC6322 PC6344 PC6364 PC6379 PC6392 PC6404
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
+NVVDD1

A
5 4 3 2 1

<43> VR_HOT#

47P_0402_50V8J~D
1

PC501
+5VS

2
+VCCST CPU_B+

1
0_0402_5%

0_0402_5%
1_0402_5%
0.1U_0402_25V6
1

PC502

@ PR504

PR505

@ PR506
D D

45.3_0402_1%

75_0402_1%

100_0402_1%
PC503

PR503
PR501

PR502

2
@ 1U_0402_16V6K

2
2 1 1 2 1 2
<9> VR_SVID_CLK

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