Professional Documents
Culture Documents
4740 Lecture19 Dynamic Latches and Flipflops
4740 Lecture19 Dynamic Latches and Flipflops
ECE4740:
Digital VLSI Design
Lecture 19: Dynamic latches/flip-flops
690
Recap
691
1
6/8/2018
D Q D Q D Q D Q
!CLK
input sampled
D (transparent mode)
CLK
CLK
in D Q out !CLK
clk CLK
feedback (hold mode)
693
2
6/8/2018
T2 I5 T4 I6 Q
I2 I3
QM
T1 I4 T3
D I1
0
CLK
1
T2 I5 T4 I6 Q
I2 I3
QM
T1 I4 T3
D I1
1
CLK
0
3
6/8/2018
clock clock
In data must
be stable
tpd,ff time
CLK CLK
!CLK !CLK
697
4
6/8/2018
P2 P4
!CLK CLK
B P4
P2
on
!CLK CLK
699
5
6/8/2018
CLK
tnon_overlap
CLK1
CLK2
700
701
6
6/8/2018
master transparent
slave hold
CLK
master hold
!CLK
slave transparent
703
7
6/8/2018
704
D T1 I1 T2 I2 Q
C1 !CLK C2
CLK
8
6/8/2018
CLK1 CLK2
D T1 I1 T2 I2 Q
C1 !CLK2 C2
!CLK1
requires
master transparent routing of 4
slave hold clock signals
CLK1
tnon_overlap
CLK2
master hold
slave transparent
706
Issue 2: robustness
• Dynamic flip-flops suffer from
– Coupling between signal nets and internal
storage nodes (can destroy FF state)
– Leakage currents cause state to leak with time
• Solution: pseudostatic FF add weak
feedback inverter
to each latch
!CLK CLK
D Q
CLK !CLK
707
9
6/8/2018
708
M2 M6
master transparent
slave hold
CLK
10
6/8/2018
M1 M5
CLK CLK
!CLK !CLK
710
M1 M5
CLK CLK
!CLK !CLK
11
6/8/2018
1.5
Q(0.1)
1 clk(0.1)
For a
0.5 CLK(3) 3 ns clock
0 (race condition
exists)
-0.5
0 2 4 6 8
Time (nsec)
712
Image adapted from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
713
12
6/8/2018
REG
a
REG
CLK log Out
REG
b CLK
CLK
• Critical path:
Tmin=tpd,ff+tpd,add+tpd,abs+tpd,log+tsu,ff
714
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
+
REG
REG
REG
CLK
715
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
13
6/8/2018
Pipelining
a1+b1
a REG
REG
REG
REG
CLK log Out
REG
716
Pipelining (cont’d)
REG
a |a1+b1|
+
REG
REG
REG
717
14
6/8/2018
Pipelining (cont’d)
a REG
log|a1+b1|
REG
REG
REG
CLK log Out
REG
718
+
REG
REG
REG
CLK
15
6/8/2018
REG
REG
REG
CLK log Out
REG
CLK
+
REG
REG
REG
CLK
16
6/8/2018
A B A B
P1 P2 P2 P1
722
17
6/8/2018
B D
DQ + DQ
CLK CLK
*
C tsu,ff=0.5ns
DQ
tpd,mult=7ns
CLK
• Tmin=tpd,ff+tpd,mult+tpd,add+tsu,ff=10ns
• fmax=100MHz
725
18
6/8/2018
B D
DQ + DQ
CLK CLK
*
C tsu,ff=0.5ns
DQ
tpd,mult=7ns
CLK
• Tmin,pipe=tpd,ff+tpd,mult+tsu,ff=8ns
• fmax=125MHz
726
19