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VLSI DESIGN LAB: ECL-307

ROLL NO:
2 0 2 0 B E C E 0 2 0

NAME:
T A N V E E R

DATE OF PERFORMING EXPERIMENT:

1 6 0 9 2 0 2 2

DATE OF REPORT SUBMISSION:

1 4 1 0 2 0 2 2

EXPERIMENT NO.01

OBJECT: To plot the device characteristic of NMOS Transistor.

➢ Id Vs Vgs ( for different Vds)

➢ Id Vs Vds (for different Vgs)

Tools/simulator used: LT Spice Simulator

Circuit diagram:
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i) Id Vs Vgs ( for different Vds )

Schematic/Netlist

Waveforms/Tables:

ii) Id Vs Vds ( for different Vgs )

Schematic/Netlist
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Waveform:

➢ RESULT: As Vgs increases for the NMOS transistor, the threshold voltage is reached where
drain current elevates. Once Vgs reaches 0.7V, the current increases rapidly.