400 V to 12 V Step-down DC-DC Power Converter

Based on the Differential Concept

Neilor Colombo Dal Pont Jessika Melo Andrade Matheus Schramm Dall’Asta
Dept. of Electrical and Electronic Dept. of Electrical and Electronic Dept. of Electrical and Electronic
Engineering Engineering Engineering
Federal University of Santa Catarina Federal University of Santa Catarina Federal University of Santa Catarina
Florianopolis, Brazil Florianopolis, Brasil Florianopolis, Brazil
neilorcdp@gmail.com jessikameloandrade@gmail.com dallastamatheus@gmail.com

Telles Brunelli Lazzarin Brad Lehman

Dept. of Electrical and Electronic Dept. of Electrical and Computer
Engineering Engineering
Federal University of Santa Catarina Northeastern University
Florianopolis, Brazil Boston, USA
telles@inep.ufsc.br lehman@ece.neu.edu

Abstract—A new approach for step-down dc-dc power con-
verter design is proposed in this paper, which is based on
the differential connection of two conventional topologies. The
converters provide two output voltages, and, then, the difference
between them is the output voltage applied to the load. This
strategy allows that each converter to work in an adequate
operation point regarding gain and duty cycle because a high
step-down gain is provided by the difference of voltages between
converters. The method can be applied in all converters, using
either equal or different topologies. In this paper, an analysis
for a differential converter is presented, and corroborated by
simulation and experimental results, using a designed prototype
of 400 V to 12 V and 100 W rated power.
Index Terms—Step-down, high gain, differential concept.
II. PROPOSED CONCEPT
Usually, step-down dc-dc converters are made employing
one circuit between the input source and the load (as depicted
in Fig. 1(a)), which can use transformer [1], commutation cells
[2], [3], [5], [6], [8] or connection of converters to provide
high gains [9], [10]. In this solution, the power converter has
to provide all of the desired gain between vo and vi , which is
the biggest challenge when a high-gain step-down converter is
required. On the other hand, the new concept proposed herein
uses two converters between the input source and the load.
The converters 1 and 2 supply vo1 and vo2 voltages, as seen
in Fig. 1(b).

I. I NTRODUCTION
vo=vo1-vo2
+
Step-Down +
+ -
In the last years, extensive efforts have been devoted to vi dc-dc vo vi
+ Conv. +
vo1 vo2+ Conv.
- - 1 - - 2
increase the gain of step-up and step-down dc-dc converters. converter -

Isolated converters use a transformer turns ratio value to

provide gain. However, the transformer is a bulky component (a) (b)

and when a high gain is required, the intrinsic parameters

Fig. 1. (a) Conventional step-down dc-dc converters; (b) Differential connec-
become significant, which may counterbalance its benefit [1]. tion concept.
Recently, topologies based on switched-inductor (SL) [2]–[4],
switched-capacitor (SC) [2], [4], [5], coupled inductor [2], The load is connected between both voltages (in a differen-
[6], [7], impedance source circuit [2], [8], series and parallel tial connection) and the load output voltage vo is the difference
connections [9], ladder [2], [5] and stacked connection [10] between the vo1 and vo2 . The output voltage of converter 1 is
have been proposed to obtain high voltage gain. However, all defined by vo1 = vi G1 and the output voltage of converter 2
of them use a higher number of components, which can reduce by vo2 = vi G2 . Thus the output voltage is given by (1) and
the efficiency or increase complexity. the total static gain (G12 ) is obtained by (2).
This paper proposes a new concept to generate high gain
step-down dc-dc power converters: it uses a differential con- vo = vo1 − vo2 = vi (G1 − G2 ) (1)
nection of two conventional converters, and then the voltage
difference between both is the output voltage. Main details vo
about the proposal will be presented herein. = G1 − G2 = G12 (2)
vi

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 S1a Conv. 1 Conv. 2 S2a Conv. 1 Conv. 2
Buck Buck L1 S L2
io Boost Boost
S2a
+ + 1a vo
vi vi + -
- S1b + L1 + vo - L2 + S2b -
+ + + +
v1 C1 vo1 vo2 C2 v2 S1b S2b
- -
C1 vo1
-
vo2
-
C2
- -

D1 D2 D1 D2
PWM1 PWM2 PWM1 PWM2
(a) (b)

Conv. 1 Conv. 2 Conv. 1 Conv. 2

L2
S1b Buck-Boost Buck-Boost S S1a Buck Boost
S2a
+ S1a vo S2a 2b
+ vo
+ - + -
vi vi
- - - - L1 + +
L1 C1 vo1
+
vo2
+ C2 L2 S1b C1 vo1 vo2 C2 S2b
- -

D1 D2 D1 D2
PWM1 PWM2 PWM1 PWM2
(c) (d)

Fig. 2. Proposed step-down dc-dc topology based on differential connection: (a) based on two buck converters; (b) based on two boost converters; (c) based
on two buck-boost converters and; (d) based on one buck and one boost converter.

Using this concept, the converters 1 or 2 do not have The Figs. 2 and 3 illustrate how the differential voltage v12 is
to provide all of the desired gain because the total gain is generated and how vo is controlled by ΔT .
obtained by difference between both converters, as described
by (2). This strategy allows each converter to work with S1a
adequate values of duty cycle. T1
S2a t
T2
III. CONCEIVED TOPOLOGY BASED ON
v1 v t
PROPOSED CONCEPT i

The proposed concept is employed to design a step-down v2 vi t

topology based on two conventional-bidirectional buck con-
verters, as showed in Fig. 2(a). However, the principle can t
v12,vo vi v12
be applied in all converters, using either equal or different vo
topologies. For instance, other conventional topologies could
be used as seen in Figs. 2(b), (c) and (d), because the concept ΔT ΔT t
2 2
can be generalized and any kind of topology can be applied.
Ts
Based on (1), the output voltage vo from converter of Fig.
2(a) is defined in (3) in relation to the duty cycles D1 and D2 . Fig. 3. Main waveforms of the proposed converter.
Both duty cycles are given by (4) regarding the conduction
time of each Buck converter (T1 and T2 ). The difference
between both conduction times (ΔT ), written in (5), defines vo = vi (D1 − D2 ) (3)
the differential duty cycle (ddif ), which describes the real
static gain of the topology, as shown in (6). Thus, a small ddif T1 T2
supplies a high conversion rate, regardless of each converter D1 = D2 = (4)
Ts Ts
working with high value of duty cycle (for examples D = 0.5
or D = 0.8). As a result of this strategy, the average value of ΔT = T1 − T2 (5)
output voltage on the load is given by (7) in relation to the
duty cycle ddif . This value can be controlled by difference
T1 − T2 ΔT
between D1 and D2 . ddif = = = D1 − D2 (6)
The main waveforms of proposed structure are depicted in Ts Ts
Fig. 3, where the gate driver signals and the v1 , v2 , v12 and ΔT vi
vo voltages are shown. In Fig. 2(a) these voltages are defined. vo Ts = = ddif vi (7)
Ts

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 On considering that D1 = Dsp + ddif /2 and D2 = Dsp −
ddif /2, the duty cycles D1 , D2 , Dsp and ddif are shown in D1,D2
1.0
Fig. 4 (a). The duty cycle Dsp means the set point where D1
the converters will operate around. A small variation on this
Dsp
operation point will be defined by ddif . If Dsp is set on 0.8 D2
and ddif = 0, the D1 and D2 are 0.8 and thus the output
voltage vo will be 0 V. When D1 and D2 are changed (one
Min_Gain
increases and another decreases), the difference between both 0.0
defines the output voltage vo . The figure illustrates a minimum 0
ddif_min 1 d
dif
value of ddif , which means a minimum gain (Min gain) due to
(a)
technological restrictions as either PWM resolution or turn-on Gain
and turn-off switch limit times.
It should be noticed that small values of ddif can provide 1.0

a gigantic gain G12 (an ultra-high step-down gain), and

nevertheless both converters operate next to duty cycle Dsp .
0.1
This value can be set in 0.5 or on another value that provide
more advantages, as 0.2, 0.6, 0.8, etc. The differential gain Min_Gain
versus duty cycles are depicted in Fig. 4(b), that consider 0.0
0.0 0.1 1 d
Dsp = 0.5. ddif_min dif

Similar analysis could may be applied to other converters, as 0.50 0.55 1 D1

shown in Fig. 2(b) and Fig. 2(c). The output voltage provided 0.50 0 D2
0.45
by two boost differential converter (Fig.2(b)) is given by (8), (b)
and by two buck-boost differential converter (Fig.2(c)) is given
by (9). Fig. 4. (a) Duty cycles of the proposed topology; (b) Static gain of the
proposed topology versus duty cycle.
(1 − D2 ) − (1 − D1 )
vo = vi (8)
(1 − D1 )(1 − D2 )
depends on the duty cycle, reaching its peak value for D =
D2 (1 − D1 ) − D1 (1 − D2 ) 0.5.
vo = vi (9)
(1 − D1 )(1 − D2 )
Vi D(1 − D)
Io,crit = (13)
IV. D ESIGN 2Lfs
This sections focuses on the design considerations for the The minimum capacitance of each buck converter can be
differential connections of buck converters, as shown in Fig. calculated based on the output voltage maximum ripple value
2(a). The project is made by each buck converter individually. specified for each buck converter, given by (14), where ΔVCbk
However, the current through the converter components is is defined in (15). Regarding the capacitance values, they
the differential output current (Io ). The inductance values are become smaller as the duty cycles approaches to 0.5.
computed based on the maximal current ripple allowed (ΔIL ),
|1 − 2D|
using (10), where D is the duty cycle related to the converter Cbk,min = (14)
and ΔIL is the normalized value of current ripple in relation 32fs2 LΔVCbk
to the output current, as defined in (11). ΔVCbk
ΔVCbk = (15)
Vi2 D(1 − D)ΔD Vobk
L= (10) The equations for the current stresses in the devices are
ΔIL Po fs
described in Table I.
ΔIL
ΔIL = (11) V. SIMULATION RESULTS
Io
The proposed concept has been verified in a 400 V to 12 V
It is important to note that, if the topology is implemented
converter, based on differential connection of two Buck con-
employing diodes in S1b and S2a , the converters may operate
verters (Fig. 2(a)). The specification is: 100 W at rated power,
in discontinuous conduction mode. To guarantee the continu-
0.03 of gain (1/33.33), 50 kHz switching frequency, Dsp equal
ous conduction mode, the current ripple must satisfy (12).
0.7 and 2% of peak to peak output ripple voltage. The current
through the inductors are showed in Fig. 5(a). Their ripple is
ΔIL ≤ 2Io (12)
roughly 4.1 A, which corresponds approximately to 50% of the
Thus, the minimum average output current value that allow output current value at rated power. The output voltage supply
the operation in CCM is given by (13). The equation shows for each converter is seen in Fig. 5(b). They are working with
that the boundary current between DCM and CCM modes D1 = 0.715 and D2 = 0.685, which provides vo1 = 286 V and

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 TABLE I iL1(A) iL2(A)
C URRENT STRESSES 11
10
 2 √
ΔIL
IS1a,rms Io2 + 12
D1 9

 2 √
8
ΔIL
IS2b,rms Io2 + 12
1 − D2 7
6
IS1b,avg Io (1 − D1 ) 0.00994 0.00997 0.01
Time (s)
(a)
IS2a,avg Io D2
vo1(V) vo2(V)
 2
290
ΔIL
IL,rms Io2 + 12 285

Vi D(1−D)
ΔiL Lfs 280

ΔIL 275
ΔIS,max Io + 2
270
ΔIL 0.00994 0.00997 0.01
ΔIS,min Io − 2 Time (s)
(b)
v1(V)
400
200
vo2 = 274 V, respectively. The voltages v1 and v2 from each 0
v2(V)
buck converter before LC filter plus the differential voltage 400
v12 are depicted in Fig. 5(c). The output differential voltage 200
0
is 12 V, as shown in Fig 5(d). This value means a ddif = 0.03 v12(V)
and a gain of 1/33.33. 400
200
0
VI. EXPERIMENTAL RESULTS 0.00994 0.00997 0.01
Time (s)
(c)
To validate the theoretical analysis, a prototype was built
vo(V)
with the following specifications: Vi = 400 V, Vo = 12 V, Po 12.5
= 100 W, fs = 50 kHz. The duty cycle is specified close to 0.7
and the differential duty cycle ddif at 0.03, in order to obtain
12 V in the differential output. Therefore, the duty cycle of 12
the first buck converter is defined by Dbk1 = 0.7 + 0.03/2
and the duty cycle of the second buck converter by Dbk1 =
0.7 − 0.03/2. Thus, the output voltage of buck 1 is Vbk2 = 286 11.5
0.00994 0.00997 0.01
V and buck 2 is Vbk2 = 274 V. The configuration used in the Time (s)
tests is shown in Fig. 6. The prototype photography is shown (d)

in Fig. 7.
The experimental results of the input voltage, the buck
converters voltages and the differential output voltage on the
load at rated power are shown in Fig. 8. The obtained results,
with 403.6V in the input, was 290.5 V in the first buck
converter, 276 V in the second buck converter, and 12.12 V
in the differential output. The proposed converter was tested
in open loop, which caused a small difference between the
experimental and theoretical values.
The experimental results of buck inductor currents and the
differential output current at rated power are shown. As it is
expected in Fig. 9, they have almost the same average value,
around 8.6 A.
To expand the converter applications, the same prototype
was tested from a Vi = 400 V to Vo = 3.3 V, considering
Po = 12 W. The obtained results are depicted in Fig. 10, in
which a good performance and an easy method to provide
a direct conversion from 400 V to 3.3 V can be seen.
Fig. 5. Simulation results: (a) Current through the inductors; (b) Output
voltages on each converter; (c) Voltages before the LC filter; (d) Differential
output voltage.
These experimental results demonstrated the high step down
capability of the proposed connection.
The efficiency curves for different values of duty cycle are
shown in Fig. 11. Using D = 0.7, the peak efficiency was
71.5%, being 67% at rated power (100 W). However, for
D = 0.1 and D = 0.9, a peak efficiency of 75.5% was
observed, showing that an optimum value of duty cycle can
be obtained to maximize it. The losses distribution among the
devices was estimated for D = 0.7 at rated power (100 W)
and are depicted in Fig 6. Most of the losses are related to the
inductors, because of their high averaged and ripple currents,
and the MOSFETS, due their high switching current-voltage
values.

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 This first prototype was built for demonstration purposes
and to verify the principle of operation. The authors expected Vi
to improve the prototype efficiency in the future as follows: (i)
reduce the ripple current in the inductors (it was used 50% of Vbk1 Vbk2
output current), which will reduce the inductors core losses;
(ii) Integrate both LC filters in one. This can make smaller
the inductor core losses and inductor conduction losses as
well; (iii) Exchange the silicon MOSFETs by gallium nitride
switches (eGaN FET), which will reduce significantly the Vo
conduction and switching losses.
c1,c2,c3
Co=560nF c4
S 1a IXKH70N60C5 S 2a
+ L1=400μH Ro=1.44Ω L2=400μH
vi
-
+
+ vo -
+
S 1b C1=20μF v bk1 v bk2 C2=20μF S 2b
- - Fig. 8. Input voltage (Vi ), individual buck voltages (Vbk1 ,Vbk2 ) and differ-
ential output voltage (Vo ) for a 12 V and 100 W output. Scales:Vi ,Vbk1 ,Vbk2
= 50 V; Vo 5 = V.
Dbk1 Dbk2
PWM 1 PWM 2

Fig. 6. Converter structure used in the tests. iLbk1

c2
iLbk2

c3
Io

c4

Fig. 9. Individual buck inductor currents (iLbk1 ,iLbk2 ) and differential output
current (Io ) for a 12 V and 100 W output. Scales:iLbk1 ,iLbk1 = 5 A; Io =
4 A.

Vi
Fig. 7. Prototype photography.
Vbk1 Vbk2
VII. COMPARISON BETWEEN THE PROPOSED
CONVERTER AND OTHER SOLUTIONS
A comparison between the proposed solution, the conven-
tional buck converter and other step down converters is pre-
sented in Table II. It is considered the number of components
Vo
and the provided gain in function of the duty cycle. In all cases, c1,c2,c3
the maximum voltage stresses over the switches are limited by c4
the input voltage.
A common approach to obtain non isolated high step down
conversion is based on a conventional buck converter with
a gain cell. In [4], two solutions to increase the step down Fig. 10. Input voltage (Vi ), individual buck voltages (Vbk1 ,Vbk2 ) and differ-
ential output voltage (Vo ) for a 3.3 V and 12 W output. Scales:Vi ,Vbk1 ,Vbk2
gain for low values of duty cycle are presented. The first = 50 V; Vo = 2 V.
uses a passive SC cell and the second employs a passive SL

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 TABLE II
C OMPARISON B ETWEEN S TEP -D OWN T OPOLOGIES
74
Efficiency [%]

72 Topology L C S D vSmax G
70 Conventional Buck 1 1 1 1 vi D
Proposed 2 2 4 0 vi D1 − D2
68 D
[4] SC 2 3 1 4 vi 2−D
66 D = 0.1 D = 0.9 D
D = 0.3 D = 0.7 [4] SL 3 1 1 2 vi 2−D
64 D = 0.5 [11] 2 2 2 2 vi D2
D
[7] 1∗ 2 2 1 vi N +1
30 40 50 60 70 80 90 ∗ Coupled inductor.
Power [W]

Fig. 11. Experimental efficiency curves for different values of D.

Inductor Diode
Core 23%
18%
MOSFET
Inductor Conduction
Conduction 8%
21%
MOSFET
Switching
30%
Fig. 12. Theoretical division of losses at rated power and D = 0.7.
cell. Those solutions are simple, however, the obtained gain
is poor, and the efficiency is decreased due to the addition of
components.
Other solutions use modified versions of the buck converter
in order to provide more gain, as approached in [11]. This
solution provides a higher step down gain than [4] due to the
quadratic characteristics. In comparison with the proposed so-
lution, it presents the same number of components. However,
the differential converter can provide higher gain and presents
linear characteristics of the output voltage as a function of D
(in the buck-buck case), which makes it easier to be controlled.
Furthermore, coupled inductor can be used to increase the
step down conversion. In [7], a coupled inductor step down
converter is presented, obtaining soft switching to increase the
efficiency and reduce the stress on the semi-conductors. The
step down gain is increased to the factor (N +1), depending on
the turn ratio of the coupled inductor, which has a maximum
limit value.
The proposed solution herein can provide larger step down
gain than all the converters in Table II due to the differential
gain. However, each buck converter has a current equal to the
differential output current, which is usually high. In addition,
the output voltage of each converter is usually higher than the
differential voltage. Consequently, each converter processes
more power than the differential output power, which means
a high reactive power in each converter that reduces its
efficiency.
VIII. CONCLUSION AND FUTURE WORKS
A new approach for step-down dc-dc converter is proposed
in this paper. The concept is based on a differential connection
of two conventional converters, which together can provide a
high step-down gain. The concept was verified in two Buck
converters that supplied either 12 V and 3.3 V from 400 V.
Both Buck converters were set with duty cycle close to 0.7
and, thus, the difference between both duty cycles defines
the high step-down gain. This study was corroborated in
two Buck topologies, however the concept can be applied in
other structures. The proposed converter configuration presents
advantages, such as a simple analysis, simple control and
high step-down gain. As for drawbacks, the efficiency may
be low for high power applications. Nevertheless, other values
of duty cycle, new components or other topologies could be
set looking for better efficiency or another optimization.
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