Department of Computer Science & Engineering

Exam: III B.Tech. (CSE)

Monsoon Semester, 2022-23
Subject: Computer Organization
Full Marks: 50 Time: 2 hours

Sl. Section-A ( 30 Marks; Attempt All Questions) Marks

No.

1. a. Assume a PN flip-flop in which state of flip flop changes as per following. Clear
to 0, Set to 1, No change and Complement when inputs P and N are 00, 01, 10, and
11, respectively. What is the characteristics equation of PN flip flop? Register A
holds the binary information 11011001. Determine the B operand and the logic
micro operation to be performed between A and B to change the value in A to
(i) 01101101
(ii)11111101
Truth Table : [1 Marks ]

Q(t) P N Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
From above truth table :

Q(t+1) = Q(t)’.P’.N + Q(t)’.P.N + Q(t).P.N’ + Q(t).P’N

= Q(t)’. N (P+P’) + P’.N (Q(t)’ + Q(t)) + Q(t).P.N’ [1 Marks ]

= Q’.N +P’.N + P.N’.Q [1 Marks ]

(i) B = 10110100 , Logic Operation : XOR [ 0.5x2 =1 Marks]

(ii) B= 00100100 OR 11111101, Logic Operation : OR [0.5x2=1 Marks]
b. Redefine the carry propagate and carry generate function as follows:
Pi = Ai + Bi
Gi = Ai . Bi
Show that the output carry and output sum of full adder becomes:
Ci+1 = (Ci’.Gi’ + Pi’)’ = Gi + Pi.Ci
[ After Applying DeMorgan’s and Involution theorem to simplify]
= (Ci + Ai. Bi ) . ( Ai + Bi) [1 Marks]
= Ci.Ai + Ci. Bi + Ai.Bi [1 Marks ]
= Gi + Ci (Ai + Bi) [1 Marks]
i.e. Gi + Pi.Ci
Si = (Pi.Gi’) ⊕ Ci
After Substitution
= ( (Ai + Bi). (Ai.Bi)’ ⊕ Ci [1 Marks ]

After applying DeMorgan’s Theorem

= ( (Ai + Bi) .( Ai’ + Bi’) ⊕ Ci [1 Marks ]

= Ai ⊕ Bi⊕ Ci
)
i) 2. a. A 36-bit floating point binary number has 9 bits including sign for the exponent.
The coefficient/mantissa is assumed to be a normalized fraction. The numbers in
mantissa and exponent are in sign and magnitude form. What are the largest and
smallest positive quantities that can be accommodated, excluding zero? Show the
necessary steps to compute the same.

Exponent : 9 bits in Sign and Magnitude

Mantissa : 27 bits in Sign and Magnitude

Exponent Smallest value : 1 11111111 ( -255) [1 Marks]

Mantissa Smallest Value : All Zero’s [ 0.1 or 2-1 is implied ]

Hence smallest value = m x be = 2-1 x 2-255

= 2-256 1 Marks

Exponent Largest value : 0 11111111 ( +255) [1 Marks]

Mantissa Largest value : All 1’s [ 0.1 is implied ]

i.e. 2-1 + 2-2 + 2-3 +……………………………+ 2-27

= 2-1 (1-(2-1)27) /1-2-1

= (1 – 2 -27) [1 Marks]

Hence Largest value = (1-2-27) x 2255 1 Marks]

b. Add the 8-bit 2’s complement numbers 0110 1111 + 0110 1010.
State the result of the addition (as a binary value), as well as whether overflow
occurred
(i)If the number were treated as signed,
(ii)If the numbers were treated as unsigned.
Show your work to justify the answer.
01101111 + 01101010 = 11011001 [1 Marks ]

C8 = 1
C9 =0 [ 1 Marks ]

( i.e. sign of result is different from sign of inputs or carries are different)

Hence over flow occurs in case of signed number [ 1 Marks ]

C9= 0 i.e. number representable in 8 bits hence overflow does not occurs [ 1 Marks]

Overflow does not occurs in case of unsigned numbers. [1 Marks ]

3. a. Find the combination logic delays for each output or each circuit given the
following parameters. There is no setup or hold time from the inputs or outputs.
● XOR gate delay: 80 ps
● AND gate delay: 60 ps
● OR gate delay: 40 ps

Out_1 Delay = 80 ps + 80 ps= 160 [1 Marks ]

Out_2 Delay = 80 ps + 60 ps + 40 ps + 80 ps =260 ps [2 Marks ]

Out_3_Delay = 80 ps + 60 ps + 40 ps + 60 ps + 40 ps = 280 ps [2 Marks ]

b. How many CSA levels are needed to reduce 32 summands to 2? Draw the pattern
diagram for the same to justify your answer.

Eight CSA levels are needed to reduce 32 summands to 2 [1 Marks]

[4 Marks]
 Section-B ( 20 Marks : Attempt Any Two)

4. a. A computer uses a memory unit with 512K words of 32 bits each. A binary
instruction code is stored in one word of memory. The instruction has four parts: an
indirect bit, an operation code, a register code part to specify one of 64 registers and
an address part.
(i) How many bits are there in the operation code, the register code part and address
part? Draw the instruction word format and indicate the number of bits in each part.

Total WORD size= 32 Bits

Address size= 512K= 219 (i.e. 19 bits) [1 Marks]

Register Part = 64 Registers ( i.e. 6 bits)
Indirect bit = 1 bit
Operation code = 32 – ( 19+6+1) = 6 bits

Indirect :1 Bit Operation code: 6 Bits Register code: 6 Bits Address :19

[1 Marks]
(ii)How many bits are there in the data and address inputs of the memory?
Data =32 bits
Address = 19 bits [1 Marks]

b. Perform nonrestoring binary division between given integers as per following

details.
Initialization : Dividend =11 , Divisor =3
Register A = 00000 [1 Marks]
Divisor (M) : 00011
-M = 11101 ( 2’s Complement negative number representation)

[1.5x4=6 Marks]
5. a. Consider the following signed integer numbers.
Multiplicand : 0101 1010 1110 1110
Multiplier: 0111 0111 1011 1000
(i) The numbers are multiplied using the Booth’s algorithm. How many additions
and subtractions are required for the multiplication of the above two numbers? Show
the necessary steps to justify your answer.

Booth Recoding of Multiplier : +1 0 0 -1 +1 0 0 0 -1 +1 0 0 -1 0 0 0 [ 2Marks]

Hence 3 numbers of addition and 3 numbers of subtractions are required

[ 1 Marks]
Note: 0.5 Marks are awarded if total 6 Number of Addition/Subtraction mentioned.

(ii)Perform the fast multiplication between abovementioned numbers using bit pair
recoding method.

Bit pair recoding of multiplier : +2 - 1 +2 0 -1 0 -2 0 [ 1 Marks]

Proper noting of Summands [ 1x 5=5 Marks]

Addition of summands : [1 Marks ]

6. a. Write the sequence of control steps required for single bus structure to add the
contents of the memory location whose address is at memory location SUM to
register R2. Assume that each instruction consists of two words. The first word
specifies the operation and addressing mode and second word contains the number
SUM.

(a) 1: PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin 3
2: Zout, PCin, WMFC
3: MDRout, IRin

[Instruction Fetch: 2 Marks]

4: PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin

5: Zout, PCin
6. MDRout , MARin, Read, WMFC
 7: MDRout, MARin, Read

[Operand1 Fetch : 3 Marks]

8: R2out, Yin, WMFC [ Operand 2 Transfer: 1 Marks]
9: MDRout, Add, Zin
10: Zout, R2in, End
[Perform addition and store result : 1 Marks]

b. Registers R1 and R2 of a computer contain the decimal values 1200 and 4600.
What is the effective address of the memory operand in each of the following
instructions?
Move 20(R1),R5
Add -(R2),R5
Subtract (R2)+,R5

Effective address of the memory operand. [1x 3=3 Marks]

1. 1220
2. 4599
3. 4600 [