Lec3 Library Preparation For RH Analysis 0

Library Preparation for
RedHawk™ Analysis
VERSION: V2.1-AL-RH101-10MAY2010
Agenda
 Library Preparation Overview
 Physical Modeling
 Electrical Modeling
 Memory Modeling
- AVM & SIM2IPROF
6/23/2010, 2 ©2010 Apache Design Solutions

LIBRARY PREPARATION OVERVIEW

Library Overview
Physical Models: Electrical Models:

Physical Electrical
• LEF Model Model • .lib
• Macro GDS • Switching current profiles
• Memory GDS • ESR
• DEF/LEF/pratio RedHawk • Leakage current
Static & Dynamic
Analysis

LIBRARY CREATION
PHYSICAL MODELING

Physical Model Creation
 RedHawk is primarily a LEF/DEF cell-based flow
 Can take in GDS data as input
 Translates to DEF format using Apache utilities

(gds2def)
 GDS to DEF translations done for:

- RDL layers
- I/O cells
- memory blocks
- Custom macros and hard IPs

Physical Modelling: RedHawk Approaches
Model Features
LEF shapes for Power grid
‘Black’ Box Current/decap at pins
Suitable for early stage analysis
Full GDSII power grid
‘Gray’ Box Current/decap at pins
Suitable for early or signoff analysis
Full GDSII power grid

Spatially accurate distribution of current/decap
‘White’ Box
Temporally precise memory activity
Sign-off level accuracy

Memory Modelling for SoCs
Modelling Issues:
 Where should current sinks/

decaps be inserted?
Array
 How to characterize dynamic Array
current drawn at each sink?
 How to capture the temporal and

spatial behaviour of memory
switching activity?

Controlled Power Grid Extraction Current source / decap insertion
No met1/2 inside array region but Instances (decaps and current sources)
present elsewhere inserted in the memory block

Metal2 Metal1
Consider Metal1 and above everywhere

Consider Metal2 and above in memory array regions => metal1 has straps over array

gds2def Input/Output
GDSII Config file Layer map SPICE Netlist
gds2def
LEF
DEF
.pratio
RedHawk
Usage: gds2def [-m] <gds2def_configuration_file>

gds2def Methods
 gds2def <configuration file>

Use for:
 RDL layers
 I/O cells
 gds2def –m <configuration file>

Use for:
 memory blocks
 Custom macros and hard IPs

gds2def –m
Input and Output Data
 Input data
 Configuration file
 GDS file (individual or combined)
 LEF file
 Layer mapping file
 Spice Netlist (optional)
 Output data [create in a central area for all groups to use]

 <block_name>_adsgds.def
 <block_name>_adsgds.lef
 <block_name>_adsgds.pratio

gds2def -m
Configuration File
TOP_CELL top_cell With SPICE
GDS_MAP_FILE <layermap>
SPICE_NETLIST
LEF_FILE <lef> SPICE_XY_SCALE
If specified, creates a LEF file along with NMOS_MODEL_NAME
DEF PMOS_MODEL_NAME
MEMORY_CELL
VDD_NETS { WORD_LINE_DIMENSION
VDD
}
GND_NETS {
VSS
} No SPICE
MEMORY_BIT_CELL MEMORY_CORE_REGIONS

gds2def -m
Configuration File (Cont’d)
 Using SPICE netlist with XY locations
SPICE_NETLST cell.spice
This netlist should have XY locations, an example netlist is shown below:
.SUBCKT test 1 2 3 4 5 6 11
** N=14 EP=7 IP=53 FDC=8
M0 3 14 2 3 nlv L=1.3e-07 W=1e-06 $X=790 $Y=5490
M1 12 4 3 3 nlv L=1.3e-07 W=1e-06 $X=1360 $Y=5490
M2 13 5 12 3 nlv L=1.3e-07 W=1e-06 $X=1930 $Y=5490
M3 14 6 13 3 nlv L=1.3e-07 W=1e-06 $X=2500 $Y=5490
M4 1 14 2 11 plv L=1.3e-07 W=1e-06 $X=790 $Y=1590
M5 14 4 1 11 plv L=1.3e-07 W=1e-06 $X=1360 $Y=1590
M6 1 5 14 11 plv L=1.3e-07 W=1e-06 $X=1930 $Y=1590
M7 14 6 1 11 plv L=1.3e-07 W=1e-06 $X=2500 $Y=1590
.ENDS
SPICE_XY_SCALE 1
If the X and Y co-ordinates in the SPICE netlist are in microns, set this to 1000.
The units in Hercules netlists are typically specified in microns. The units in Calibre
netlists is in microns*1000, so SPICE_XY_SCALE is set to default value of 1.

gds2def -m
Configuration File (Cont’d)
 Using SPICE netlist with XY locations (cont.)
NMOS_MODEL_NAME {
NM
}
PMOS_MODEL_NAME {
PM
}
These keywords are used to specify the NMOS and PMOS transistor models in
SPICE netlist.
MEMORY_CELL bit_cell/auto_detect
The name of the memory bit cell name in SPICE netlist
WORD_LINE_DIMENSION 128
The width of the word line in the memory.

Creating GDSII Layer Map File
Syntax
<Layer_name> <Layer_type> <Layer_number> <Text_layer_number>
If no text layer number is available, it can be replaced by “-”. An example layer

map file is shown below. Please refer to manual for more details.
Example
#Layer_name Layer_type Layer_number Text_layer_number
CO contact 30:0 -
METAL1 m 1:5;10:0 11:1;13
VIA1 v 2:12 4
METAL2 m 13:0;15:50 -
VIA2 v 3:12;3:43 -
In the above specification,

• Layer_type can be 'm' for metal, 'v' for via
• Layer_number and Text_layer_number can be specified for several layer-datatype pairs and for several
layer numbers separated by ';' (semi-colon).
• Layer and datatype are separated by ':' (colon).
• Text_layer_number can be ignored by inserting a dash '-'.

gds2def
Input and Output Data
 Input data
 Configuration file
 GDS file (individual or combined)
 LEF file
 Layer mapping file
 Output data [create in a central area for all groups to use]
 <block_name>.def
 <block_name>_adsgds.lef

gds2def
Configuration File
Extract for one cell Extract for many cells
TOP_CELL top_cell TOP_CELL {

<cell 1>
GDS_MAP_FILE <layermap> <cell 2>
..
LEF_FILE <lef> }
If specified, creates a LEF file along with
DEF GDS_MAP_FILE <layermap>
VDD_NETS { LEF_FILE <lef>

VDD If specified, creates a LEF file along with
} DEF
GND_NETS {
VSS VDD_NETS {
} VDD
}
GND_NETS {
VSS
}

LIBRARY CREATION
ELECTRICAL MODELING

Apache Power Library
 Provides switching current, leakage current,

intrinsic decap and leakage information
 For power gated designs provides switch apl.conf
model and PWL capacitance data .lib files
APL
 w/o APL, .LIB is used to approximate I(t)
SPICE model
 Inputs for APL Characterization
SPICE netlist
 Device model (Hspice format)
 Spice Netlist (Hspice format) Design data
cell.spcurrent
 .lib information
cell.cdev
 Design data (optional)

APL-DI Flow Overview
.LIB
Input Output
Slew Load Vectors
Netlist*
APL Models*
*Hspice compatible
Cell current
Cell Decap

APL-DD Flow Overview
SPEF
.LIB LEF/DEF
STA
RedHawk
Input Output
Slew Load Vectors
Netlist*
APL Models*
Cell current *Hspice compatible

Cell Decap

Dynamic Analysis with APL
Sum of Instance Current (Design-dependent)

Sum of Instance Current (Design-indepdent)
Total Supply Current (Design-dependent)

Total Supply Current (Design-independent)

APL BASICS AND STD CELL
CHARACTERIZATION

Dynamic Voltage Drop Modeling
On-chip power/ground network
i(t)
Vdd Pad
L R Cdev
is(t)
Rload
V(t)
Cpg
Cload
- Cload
Vss Pad
Switching instance Non-switching instance

Output: 1->1
 On-chip power/ground network  R,L,C mesh

 Switching instances  PWL current sources
 Non-switching instances  equivalent decaps

Dynamic Voltage Drop Modeling (Cont’d)
 PWL current for each instance (APL Current)
 Equivalent decaps (APL Cap)
 Vdynamic waveform is computed at every node by transient simulation
V(t)
Vdd Pad
i(t) ESR
Cpg
Cdev Cload
Vss Pad
Non-switching instance
Switching instance Output: 1->1

APL (Apache Power Library)
 APL captures following for all the cells in the library

- Switching Current
- Intrinsic Capacitance
- Effective Series Resistance (ESR)
- Leakage Power
- Timing
- Switch Models – Voltage varying RC of Power switch
- Piecewise Intrinsic Capacitance and ESR – Voltage varying Capacitance

and ESR
(Useful during ramp-up analysis)

APL (Cont’d)
 Advantages of APL
- Adaptively changes the current drawn based on cell’s voltage during the
simulation
- Voltage drop at different parts of chip can vary significantly from ideal
during operation
- If current profiles are constructed based on ideal VDD and/or GND
> Over-estimate of current profiles so pessimistic drop
> Inaccurate modeling of switching current [cells consume same current
irrespective of drop, placement, package, etc]
> Like doing timing analysis assuming ideal slew at every cell pin – and
not consider degraded slew in the paths

LIB vs APL
.Lib: Triangular energy waveforms
D
Q
APL model for a cell
D CK
Q • Cell level abstraction with transistor
CK
level characterization
Current
• For standard cells, memories and
macros
APL: Multi-dimensional current profiles Contains:

Switching current
Current versus loads Current versus VDD
450 400
Leakage ~ f(state, temperature)
400
350
350
300
Intrinsic capacitance
300
250 Effective series resistance
Current
250
Current
200
150
200
150
Cell delays and slews
100 100
…
50 50
0 0
0 50 100 150 200 250 300 0 50 100 150 200 250 300
Time Time

APL Data Requirements
400
350
Characterization Spice Device
Netlist Lib / Lef
conditions Models
300
250
Current
Uses Nspice to capture

200 APL Voltage, load, slew and
State dependency
150
100
Leakage Decoupling Current Pwcap
Delay
50 Current Cap & ESR Waveforms
0
0 50 100ESR 150 200 250 300
Decap Time

APL I(t) Characterization
Vdd
I(t)
R
rslew fslew C1 C2
• Capture the I(t) for varying slews, cload and different voltages

APL Cdev Characterization
Vdd Vdd
ESR
I-leak
Cdev
Vss Vss

APL Design Independent
 Characterizes all cells found in .lib

 Range of slews/loads are derived from .lib lookup tables
- Slews normalized from .lib threshold to full swing
- Default: Average of 70 combinations of slew and load and 4 voltages
 Required inputs:
- Synopsys .lib
- Spice sub-circuits
- Device models
- Configuration file
- LEF/custom lib files for multi-rail cell (P/G pin)
- PG-ARC custom lib for Cdev characterization on mvdd/mvss cells

Basic APLDI Configuration File
APL_RUN_MODE DI
WORKING_DIR .
VDD_PIN_NAME VDD
GND_PIN_NAME VSS Subckt P/G pin names to probe
APL_RESULT_DIRECTORY my_result
DESIGN_CORNER {
TT {
PROCESS TT
TEMP 25 Operating conditions – forms signature
VDD 1.6 of generated APL file
}
}
LIB_FILES {
lib_dir
Synopsys .lib
stdcell_tt_1.6v.lib
}
SPICE_NETLIST foundry.cir
#SPICE_NETLIST_DIRECTORY netlist_dir
Spice sub-circuits
# Option 1
INC spice1.models
Device models
# Option 2 – multiple .LIB
DEVICE_MODEL_LIBRARY cl013lv.l TT

APL Command File Checklist
 VDD value consistent with GSR and .LIB?

 Temperature consistent with .LIB, tech file?
 Slew Thresholds correct?
 Name of Power/Ground nodes in Spice netlist may not be
same as design
 Sizes in Spice netlist in um?
 Best to use extracted Spice netlist with RC parasitics
 PROCESS keyword defined correctly

APL Voltages
 APL configuration file keyword ‘APL_VOLTAGES’ specifies

voltage values as a fraction of LIB nominal voltage, which
are used for creating the current profiles. Voltage fractions
should be specified in ascending or descending order.
Eg. Nominal Voltage of 1.5V

‘APL_VOLTAGES 6 0.7 0.8 0.9 1.0 1.1 1.2’
Will create current profiles for:
1.05V, 1.2V, 1.35V, 1.5V, 1.65V, 1.8V
 Default: APL_VOLTAGES 4 0.75 0.9 1.0 1.15

APLDI command line mode
apldi <config_file>
Options
-l <file> - characterize only listed cells
-c - decap characterization
-p <file> - intentional decap cells
-j 1|2 - parallel execution
-o - output current or decap file
-s 1|2 - 1: generate apache.apdi, 2: skip sample generation
-w - Piecewise cap characterization for Low Power
– Intentional decap cells must be explicitly listed because they are not
found in .lib
– To characterize standard cell, custom cell, and IO cell in one apl run,
define the cell type in the list file, e.g.,
Cell_a S - std cell
Cell_b C - custom cell
Cell_d I - io cell

Parallel execution
 Setup LSF or Sungrid environment

source /<lsf_setup_path>/cshrc.lsf
source /<lsf_setup_path>/settings.csh
 Login to one of machines in LSF/Sungrid cluster
 In APL config file specify

GRID_TYPE LSF
BATCH_QUEUING_COMMAND bsub
 Monitor execution with

aplstat <config_file>

Running APL over LSF/SunGrid
 APL config file options:
LSF_JOB_COUNT 40
BATCH_QUEUING_OPTIONS [-q <queue_name>] [-R <resource_name>] [-m
<machine_name>] [-o /dev/null ]
BATCH_QUEUING_COMMAND bsub (default) | qsub
LSF_SUBMIT_MODE 1 (default, bsub) |2 (LSF API)
GRID_TYPE LSF (default) | SUN_GRID
 Batch-mode command:
apldi –s 2 -j 2 apl.conf # for current characterization
apldi –s 2 –j 2 –c apl.conf # for cap/ESR/leakage characterization

Finding APL Results
 Summary log file

apldi.current.<time>.log
apldi.cap.<time>.log
 Current profiles of all characterized cells in one file. Default -
corner<name>.current
 For each cell
- In APLDI_<date>/corner1/CURRENT/
<cell>.current.<time>.log
cell.spiprof - current profile
- In APLDI_<date>/corner1/CAP/
<cell>.cap.<time>.log
cell.cdev - device capacitance

APL Log File
 Log messages
– Summary report apldi.{current,cap,pwlcap}.<date>.log
Nominal VDD used: 1.8

Temperature used: 25
Netlist used: ../../spice/scc8q3rgenb.sp
Voltage range: 2.07 1.8 1.62 1.35
# |------- slews --------|
stat #smpl #smpl_done c_min c_max rs_min rs_max fs_min fs_max vec cell_name
pass 70 70 1.00 278.80 0.012 2.500 0.012 2.500 LIB bufx1
…
– Detailed log files – all warning/error messages for each cell are
logged to:
<APL_RESULT_DIRECTORY>/<corner>/CURRENT/<cell
name>.{current,cap}.log

APLDI Characterization Modes
 APL sample mode controls number of samples.
APL_SAMPLE_MODE [ FAST_CHECK | DEFAULT ]
 FAST_CHECK : 1 Voltage ; 1 load-slew sample

 DEFAULT : 4 Voltage ; Adaptive load-slew samples
(avg 70)
 Automatic slew normalization

All slews in RedHawk/APL normalized to 0-100% threshold
based on .lib thresholds

Recommended procedure for characterization
of new library
Step 1 - Run fast check mode

 Add to config file:
APL_SAMPLE_MODE FAST_CHECK
One sample per cell – no need for LSF
 Run both apldi <config_file> and
apldi –c <config_file>
 Check that most cells pass in apldi.current.<time>.log and
apldi.cap.<time>.log
Sample range:
stat #smpl #smpl_done c_min c_max rsw_min rsw_max fsw_min fsw_max vec cell_name
pass 1 1 1.000 1.000 0.012 0.012 0.012 0.012 LIB bufX1
pass 1 1 1.000 1.000 0.012 0.012 0.012 0.012 LIB andX1
…

Recommended procedure (Cont’d)
Step 2 - Verify that LSF works

 apldi –j 2 <config_file>
 Use aplstat <config_file> to monitor, check aplstat.log for failure
reason
#### 2 Cells Succeeded ####
bufX1 pass
andX1 pass
Total number of cells: 2

Number of cells succeeded: 2
Number of cells failed: 0
Number of cells pending: 0
 Test validity of generated current profiles:
aplchk [-v] corner<name>.current

Recommended procedure (Cont’d)
Step 3 – run full blown APLDI

(Do Run Time/File Size estimation)
 Remove APL_SAMPLE_MODE FAST_CHECK from apl config. file
 Run apldi –j 2 <config_file>
 Check success rate in apldi.current.<time>.log
 Sanitize peak current and pulse width with aplreader <current_file>
cell=andX1
vdd=1.8 v; C1=0; R=0; C2=1; Slew1=11.667; Slew2=11.667
peak=74.02 uA; area=0.01577 pc; width= 0.456 ns vdd rise
peak=61.95 uA; area=0.01478 pc; width= 0.456 ns gnd rise
peak=72.51 uA; area=0.00573 pc; width= 0.133 ns vdd fall
peak=71.36 uA; area=0.00654 pc; width= 0.152 ns gnd fall

Common Issues: Missing include/model file(s)
 Symptom – in log file

##error## Can not find include file: models.all. Simulation stopped
 Reason – Device model files source other files

apldi.conf:
INC ../../models/tt.cor
tt.cor:
.inc "models.all“
 Solution – link all model files to $cwd

Common Issues: Missing vectors
 Symptom
##error## Can not find vector or scanvector for cell
'scc8q3rgenb_a2111o_0' in file './.apache/adsLib.output'. Exit.
 Reason
Cell is missing in .lib or has no function or state table
 Solution
fix your lib file or construct custom input vector

Common Issues: Undefined device models
 Symptom
##error## Undefined device model 'nch_bogus' … Simulation stopped.
 Diagnosis
Run just that cell in the FAST_CHECK mode
 Reason
There are transistor whose device models were not found in device model
files
 Solution
Load all necessary model with INCLUDE or DEVICE_MODEL_LIBRARY
statement (e.g. tt, hv_tt, lv_tt, dio)
 Workaround
Replace ‘nch_bogus’ with defined device model name. But check with the
designer first (likely input data error!)

Common Issues: Undefined MOS Models
 Symptom
##error## Undefined device model ‘nch' … Simulation stopped.
But … such model does exist in device model file(?!)
 Reason
Transistor width/lengths is outside bounds. Ex:
Mabc … nch l=0.15 w=0.000001
 Workaround
Verify transistor size in the netlist, check the scaling factor in the netlist

Debug on LSF
 Check whether the bsub command format is correct
 Check whether the data is accessible from the job running

machine (read/write permission)
 Check available disk space

APL-DI Runtime Estimation
 Factors affect total run time for a library characterization
- # of cells
- Char. Mode (# of samples)
- Cell types (gates, dff/latches)
- Computing resource (LSF farm)
- Total Run Time = K * mode * sum (cell# * T0) / LSF_machine
- T0: one sample run time
- Mode: char. Mode (sample#)
- Fast check: Mode=1 Default: Mode=70
- K: Overhead factor (network, job waiting, disk IO…) 1 < K < 10
- Example: 1000 std cell library, default mode, 10 LSF machines, T0=1sec
(gate), T0=20secs(DFF)
- Ideally, K=1, Total run time = 1 * 70 * (800*1 + 200*20) / 10 = 67.2K secs =
9.4hrs
- K=2, Total run time = 2 * 70 * (800*1 + 200*20) / 10 = 67.2K secs = 18.7hrs

APL-DI File Size Estimation
 Factors affect total file size for a library characterization
- # of cells
- Char. Mode (# of samples)
- Cell types (gates, dff/latches)
- Total File Size = K * mode * sum (cell# * S0)
- S0: one sample size (1 sample, 1 vdd, 70 current sample pts)
- gate: (0.8K binary)
- dff: (1.6K binary)
- Mode: characterization Mode (sample#, vdd#)
- Fast check: Mode=1 Default: Mode=70
- K: Overhead factor (header, step, cellname, mP/G…) 1 < K < 5
- Example: 1000 std cell library, default mode (70 pts), S0=0.8K (gate),
S0=1.6K(DFF)
- Total filesize = 3 * 70 * (800*0.8 + 200*1.6) = 168MBytes

Cell Functionality from .lib
 Function definition in library (com. & simple seq. cells)
function : "A&B&C";
 State table definitions (complex seq. cells)
statetable (" CLKIN EN TE","IQ") {

table : "L L L : - : L ,\
L L H : - : H ,\
L H L : - : H ,\
L H H : - : H ,\
H - - : - : N ";
}
 User provided vector (memory, user-defined full custom cell)

Custom Vector File
 Complex Cells can be characterized using custom vector files
 Vectors can be written in an ASCII file. Filename could be

<cell_name>.inv
 Vector files can be specified in a directory. This directory

name can be specified in APL config file using VECTOR_DIR
keyword
VECTOR_DIR ./vectors

Custom Vector File - example
<cell_name>.inv
dc pin_c vdd
dc pin_d 0
active_input a
active_output y
vector {
vname a b
tunit ps
vih 1.1
0 10
1 01
5 10
7 01
}

Multi-VDD APL Characterization
 Multi Vdd APL characterization captures current/decap profile

for different power pins separately (RH5v3)
 User Interface changes for mVdd APL char

- APLDI : Need to define LEF_FILES keyword in config
- For cells having multiple pgarcs, user need to provide PG arc
information through Custom Libs file
- Custom Lib file can be specified in the APL config file like this:
CUSTOM_LIBS_FILE {
<custom_lib_file>
}

Multi-VDD APL Characterization
 Multi Vdd APL characterization captures current/decap

profile for different power pins separately (available since
RH5v3)
 User Interface changes for mVdd APL char

- APLDI : Need to define LEF_FILES keyword in config. If LEF files are not
available, need to specify power, ground pins through Custom Libs File
- For cdev (decap) char of cells with multiple power, ground pins, user
also needs to provide PG arc information through PGarc specific
custom Lib file
- For decap cells characterization, value for each VDD pin should be
defined in config file

mVDD APL Characterization: Custom Lib File
 Custom Lib file can be specified in the APL config file like
this:
CUSTOM_LIBS_FILE {
<custom_lib_file>
}
 Example Custom Lib File for specifying power/ground pins :

cell LVL_IN_F12_PM {
pin VDDIN {
type vdd
}
pin VDD {
type vdd
}
pin VSS {
type gnd
}
}
NOTE: LEF files overwrites custom lib files if both are given

mVDD/mVSS cdev char:
PGarc specification
 Pgarc is required for cdev characterization of cells with multiple power,

ground pins.
 It defines decap components between Power and Ground pins
 APL-DI mode: use PGarc specific custom lib file to define pgarc
- Example in apldi.config:
LIB_FILES {
<lib_files>
pgarc.lib CUSTOM
}
Where pgarc.lib contains:
pgarc {
<vdd_pin_name> <vss_pin_name>
}
- Run Command: apldi –l list –c apldi.config
 APL-DD mode: .apache/apache.pgarc is created by RedHawk.

- APL will automatically search this file
- Run command: apldi –s 2 –l list –c apl.config

mVDD/mVSS Decap cell char
 Decap cells (non-function cells) are not present in .lib

 Decap cells’ PG Pin information is from PGarc custom lib file
similar to cdev as explained in previous slide.
 Additionally value for each vdd pin should be defined in APL
config file
DECAP_VDD_PIN {
vdd_name vdd_value
...
}
 If DECAP_VDD_PIN is not given, the vdd value specified by VDD keyword
will be used for all vdd pins.

APL char for Power gated designs
 Switch cell characterization

- Need to characterize header/footer switches in low power designs.
- Utility: aplsw <file containing list of switch cells & their configuration
files>
- Please refer RedHawk manual for details.
 PWL cap characterization

- Need to characterize cells in the design to get the piecewise linear
models for intrinsic capacitances, leakage currents, and effective
series resistance, as a function of voltage.
- APL utility “apldi –w <apl config file>
- Please refer RedHawk manual for details.

APL Pwcap Data
 Power gates are non-linear elements in different modes
 Transition from “off” to “on” state requires charge transfer
to/from design
 Design capacitance varies as function of node voltages
 Long simulation times to capture entire power-up process
 Required only for Powerup analysis; Not required for ON state
analysis
Non-linear capacitor modeling

Actual r7_ht_and2tc: cap modeling for ramp-up
Circuit 3.40E-03
3.20E-03
3.00E-03
2.80E-03
2.60E-03
RedHawk 2.40E-03
Equivalent 2.20E-03
2.00E-03
Circuit 0 0.5 1

APL Utilities - aplreader
 Function
- Read apl binary current profile (cell.spcurrent) and decap (cell.cdev)
files and present user-readable summary report
 Usage
- aplreader <cell.spcurrent> for current profile
- aplreader -c <cell.cdev> for decap file
- aplreader –pwc <cell.pwcap> for pwcap file
- Use '-l <cell_list_file>' to print only the cells in the given file.
Alternatively, use '-cells <name>' to specify cell name in the command
line
- Use '-pin <name>' to print given pins only

APL Utilities - aplchk
 Check APL results data integrity.

 aplchk [-c] [-pwc] [-ilimit] [-l <list_file>] [-w <output_file>] [-
a2b <output_file>] <input_file>
- -c : specifies checking cdev decap files

- -pwc : specifies checking pwcdev files
- -ilimit : ignore the error limit checks
- -l <list_file> : writes out result information on cells named in <list_file>
to the specified <output_file>

APL Utilities - aplmerge
 Check the compatibility of corner conditions (P, V, T) for similar

types of APL files and merge them into a single output file.
 aplmerge [-c] [-pwc] [-ilimit] [-rep] [-im] [-t] [-ahead <cell_list]
[-avm] [-l <cell_list>][-o <output_file>] [<file1> [<file2> [...]]]
[directory]
- -c : specifies merging intrinsic decap files
- -pwc : specifies merging piecewise linear decap files
- -ilimit : ignore the error limit checks
- -rep : specifies replacing cells in the first file with cells with the same
name in the second file. Cell information not duplicated in the second
file remains the same in the output file.
- -im : ignore model library difference
- -t : specifies turbo mode, which runs faster by skipping duplicate cell
checks

aplmerge - Options
 -ahead <cell_list> : merge binary cdev without header, a faked

header is used.
 -avm : ignore header difference in vmemory.current
 -l <cell_list> : defines the cells to be included in the merged

output file.
 -o <output_file> : defines the output file.

Current APL Limitations
 Power pin names for mVdd characterizations obtained from

LEF_FILES. sVdd power pin names still must be specified.
 Floating and Tie cells cannot be characterized with the same

configuration file.
 APL_VOLTAGES not supported for mVdd

IMPORTING DATA INTO REDHAWK

Importing APL Data into RedHawk
 APL files can be imported in GSR
APL_FILES {
<file> <type>
<dir> <type>
}
Example:
APL_FILES {
cell.current current
NOTE: keyword
cell.cap cap
cell.pwcap pwcap
avm.conf avm
./APL_OUT/corner1/CURRENT/ current
./APL_OUT/corner1/CAP/ cap
}
 Directories are assumed to have <cellname1.current>,

<cellname1.current>, <cellname3.current>, etc…
Importing APL Data into RedHawk (Cont’d)
 import apl/avm through TCL command file also

supported
- eg: import apl cell.current
import apl –c cell.cap
import avm avm.conf

MEMORY MODELLING

Memory Power Model Basics
mA
VDD VSS I(VDD)
ADDR T
Current waveform VDD

WE
Embedded Memory
CLK mA
CS
I(VSS)
DI DO T
Current waveform VSS
One current waveform per power port

(i.e. total current profile for the memory macro)

Memory Power Model
 For each memory master, each voltage, and each

vector input subset:
- Current profile
- Intrinsic decap data
- Leakage current value
 Typical vector subset
- Write operation
- Read operation
- NOP (stand-by) operation

Memory Characterization
Characterization for current profile creation
Triangular profiles Lib or user specified power
Data sheet based (AVM) Triangular / Trapezoidal profiles
Translation of user data Functional statement based translation of pre-

(sim2iprof) characterized current profiles

Memory Data Preparation
 Translate user provided current profiles:
User HSIM out files APL format

sim2iprof
Configuration file current profiles
 Use data-sheet or .lib based modeling
Datasheet or .lib files Current profiles

AVM
Configuration file Decap/Leakage
Triangular or
Trapezoidal
profiles

USING DATA SHEET INFORMATION “AVM”

Apache Virtual Memory (AVM)
 Apache Virtual Memory (AVM) utility offers a rule based

approach for generating current profiles for memories within
the RedHawk flow
 AVM offers a desirable compromise between the detailed
accuracy of sim2iprof and Liberty based power
 AVM uses the timing and power information from data
sheets to generate current waveforms that contain two
triangular waveforms - one for memory decode and the
second waveform for memory read/write

AVM (Cont’d)
 Sample AVM Configuration file:

Multi Voltage AVM – example config

AVM (Cont’d)
 AVM config file generation
- Starting RH version 7.1, RedHawk automatically generates AVM config
file for memories using the timing and power info from their .libs (Path:
adsPower/avm.conf in run directory)
- User can choose to provide his own config file for some or all memories
in design in which case they take precedence. GSR Keyword:
APL_FILES {
<path/to/avm/config/file> avm
}
- Besides, GSR keyword LIB2AVM can be set to ‘0’ to turn-off automatic
generation of AVM config file by RedHawk.
> LIB2AVM [ 0/OFF | 1/TRIANGULAR |2 /TRAPEZOIDAL ]

AVM (Cont’d)
 AVM usage
- RedHawk internally generates current profile (vmemory.current) and
cdev (vmemory.cdev) for memories by running utility called avm on the
AVM config file.
- AVM can also be run outside (avm <avm_configuration_file>) to create
current and cdev files which can be imported in RedHawk through GSR
APL_FILES {
<path to vmemory.current> current_avm
<path to vmemory.cdev> cap_avm
}

USING PRE-CHARACTERIZED DATA
“SIM2IPROF”

sim2iprof
 sim2iprof can be used to obtain characterization data for

memory with a faster run time
 sim2iprof utility uses third-party simulation output files, such

as fsdb, ta0, tr0, or pwl format files as inputs to obtain
Read/Write/Standby mode data for memories
 Generates current profiles in a <cell>.current file for

RedHawk power analysis.

Running sim2iprof
 To run the sim2iprof utility, use the following invocation:

- sim2iprof <config_file> [-o <current_output_file>] [-avm
<avm_config_file>]
 The Vdd current waveform is extracted and converted to

RedHawk <cell>.current format.
 To get decap information, you can specify the ‘-avm’ option,

which runs the AVM utility to get decap values, ESR and
leakage power and write the data to the <cell>.cdev file

sim2iprof
 Sample configuration file
Optional

Sample current profile
From third party tool –

Input to sim2iprof
From SIM2IPROF’s
cell.current

Multi-State support
 Until RH 7.1.5, only four default states could be defined for

cells
- For memories: read/write/standby-high/standby-low
 Multi-state provides the ability to have more than four

current profile modes
 AVM/sim2iprof/APLMMX provide support for multi-state

current profile capturing for custom and/or memory blocks
 Power calculation and Voltage drop analysis honors both the

state in GSC or the state in VCD-based mode

Multi-state current profile generation
 Following are the new keywords required for multi-state

current profile generation:
- Sim2iprof: CUSTOM_STATE_SIM_FUNC or
CUSTOM_STAE_SIM_TIME
- AVM: CUSTOM_STATE_FILE
 Sample config files in next few slides

Sample multi-state AVM config file
Specify custom state file (see

next slide)
Specify Cpd data for multiple

states in avm config file

Sample multi-state AVM config file (Cont’d)
Specify Custom states and

corresponding equations in
custom state file

Sample Multi-State sim2iprof configuration file

Multi-state current profile Usage
 For Vector less analysis: One can specify an instance to be
switching in any of the valid states (state for which current
profile is generated) using GSC file. Sample GSC_FILE
contents:
- #<inst_name> <state symbol>
- Instance1 WRITE
- Instance2 M0
 For VCD based analysis, activity on all control pins

associated with states are automatically tracked (from VCD)
inside RH; Whenever a valid event (state) occurs as
read/write/etc, corresponding current profile is
automatically used.

SUMMARY OF
LIBRARY CREATION ACTIVITIES

Memory Physical Views
Creation of DEF views of memory and other custom blocks
Utility Input Data Output Data
Configuration file
GDS file <macro_name>_adsgds.def
gds2def -m Layer mapping file <macro_name>_adsgds.lef
LEF view <macro_name>_adsgds.pratio
Spice netlist (optional)

I/O Cell Physical Views
Creation of DEF views of I/O cells
Configuration file
GDS file <macro_name>.def
gds2def
Layer mapping file <macro_name>_adsgds.lef
LEF view

Electrical Models for Standard Cells
APL Library Characterization
Library (.lib)
cell.spcurrent
apldi Spice models
cell.cdev
Spice netlist

Electrical Models for IO cells
Library (.lib)
Spice models cell.spcurrent
apldi
Spice netlist cell.cdev
Biasing information
Power consumption
AVM Profile widths None for user
avm.conf

Electrical Models for Memory cells
Functional statements (.lib)

cell.spcurrent
sim2iprof Spice characterization data
cell.cdev
Decap/Leakage estimates
Datasheet parameters
AVM None for user
avm.conf

How to get Help!!!
 Apache Online Customer Support Center
– http://support.apache-da.com
– Email: support@apache-da.com

THANK YOU !!!

Lec3 Library Preparation For RH Analysis 0

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Library Preparation for

 Library Preparation Overview

6/23/2010, 2 ©2010 Apache Design Solutions

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Physical Models: Electrical Models:

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 RedHawk is primarily a LEF/DEF cell-based flow

 Can take in GDS data as input

 Translates to DEF format using Apache utilities

 GDS to DEF translations done for:

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Full GDSII power grid

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 Where should current sinks/

 How to capture the temporal and

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Controlled Power Grid Extraction Current source / decap insertion

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Consider Metal1 and above everywhere

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GDSII Config file Layer map SPICE Netlist

Usage: gds2def [-m] <gds2def_configuration_file>

 gds2def <configuration file>

 gds2def –m <configuration file>

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 Output data [create in a central area for all groups to use]

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 Using SPICE netlist with XY locations (cont.)

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If no text layer number is available, it can be replaced by “-”. An example layer

In the above specification,

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 Output data [create in a central area for all groups to use]

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TOP_CELL top_cell TOP_CELL {

VDD_NETS { LEF_FILE <lef>

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 Provides switching current, leakage current,

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Cell current *Hspice compatible

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Sum of Instance Current (Design-dependent)

Total Supply Current (Design-dependent)

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Switching instance Non-switching instance

 On-chip power/ground network  R,L,C mesh

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 APL captures following for all the cells in the library

- Piecewise Intrinsic Capacitance and ESR – Voltage varying Capacitance

(Useful during ramp-up analysis)

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APL: Multi-dimensional current profiles Contains:

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Uses Nspice to capture

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