3.4 Mechatronics For example, memory locations are assigned with addresses from 8000 to 84FR and I/O devices are assigned with addresses from 8500 to 85FF. In this scheme all the data transfer instructions of microprocessor can be used for both memory as well as I/O devices. It is suitable only for small system. 3.2.2, I/0 MAPPED I/O SCHEME In this scheme, the addresses assigned to memory locations can also be assigned to V/O devices. Since the same address may be assigned to a memory location or an /O devices. The microprocessor has a signal to distinguish whether the address on the address bus is for a memory location or an I/O device. The 8085 has an IO/M signal for this purpose. When the signal is high, then address on the address bus is for an /O device. When the signal is low, then address on the address bus is for memory locations. Two extra instructions IN and OUT are used to address I/O devices. The IN instruction is used to read the data of an input device. The OUT instruction is used to send data to an input device. This scheme is suitable for a large system. 3.3. PROGRAMMABLE PERIPHERAL INTERFACE (PPI) INTEL 8255 _ A Programmable Peripheral Interface is a multiport device. The ports may be programmed in a variety of ways as required by the programmer. The device is very useful for interfacing peripheral devices. The 8255 is a general-purpose programmable I/O device used for poral de data transfer. It has 24 /O pins which can be grouped as 3 x 8 bit parallel ports of port A, port B and port C. The eight bits of port C can be used as individual bits (or) be grouped in two Acbit ports a8 Cyyer (Cy) aNd Cyyyee (Cy). The functions. of these ports are defined by ‘wpper writing a control word in the control register. The functions of the 8255 are classified according to 2 modes. () _ Bit Set/Reset (BSR) Mode. (ii) 1/0 Mode. (i) Bit Set/Reset Mode — The BSR Mode is used to set or reset the bits in port C.Programmable Peripheral Interface (3:5) (i) VO Mode ~ The 0 mode is further divided into three modes: (i) Mode 0 - Simple 1/0 ports. (ii) Mode 1 = 1/0 ports with handshake. (iii) Mode 2 - Bi-directional 1/0 data transfer. 3.3.1. FEATURES OF 8255 + The 8255 is a widely used, programmable, parallel I/O device. % It can be programmed to transfer data under various conditions from simple 1/O to interrupt 1/0. “It is compatible, with all Intel and most other microprocessors. Its bit set/reset mode allows setting and resetting of individual bits of port C. “The 8255 can operate in 3 I/O modes @ Mode 0 (ii) Mode 1 and (iii) Mode 2. “ Itis completely TTL compatible. 3.3.2. BLOCK DIAGRAM OF 8255 ‘The Internal Block Diagram of 8255 is shown in the figure 3.3. It consists of two 8-bit ports of port A and port B, two 4-bit ports of Port Cy and Port G,, data bus buffer, control logic, Group A and Group B Controls. ‘Also includes all the elements of a programmable device, port C performs functions similar to that of the status register in addition to providing handshake signals. Group A and Group B Controls The Group A and Group B Control Blocks receives control words from the CPU and issues appropriate commands to the ports associated with it. The Group A Control block controls port A and PC, ~ PC, while the Group B Control block controls Port B and PC, ~ PC,. Port A: It hasan 8-bit latched and buffered output and an 8-bit input latch. It‘can be programmed in three modes; Mode 0, Mode I and Made 2.[36] Mechatronic, Port B: It has an 8-Bit data I/O latch/buffer and an 8-bit data input buffer, It < be programmed in Mode 0 and Mode 1. Port C: It has one 8-Bit unlatched input buffer and an 8-bit output latch/butte, Port C can be separated into two ports and each can be used as contro] signals for port A and B in the handshake mode. It can be Programme for bit set/reset operation. pS te eee Can GROUP A PA PORTA —, Power f+sv GROUP | ®) PA7— Pag Suppl {2Sh0744 A Poe CONTROL eee =e GROUP A Bi-Directional PORT C. PC, Data Bu: UPPER ro DATA (4) 7—PCy BUS BUFFER D7—Do 8st GROUP B INTERNAL PORTC. Ge DATA BUS LOWER PC3-PCp (4) RD—-4 WR—-q READ/ GROUP, GROUP B PB Pome ARTEL User PORT B. Ay—~| CONTROL |CONTROL| (8) PB7— PB RESET Logic eat lion ier Figure 3.3 Block Diagram of 8255 Data Bus Buffer * It is a tri-state bi-directional buffer used to interface the internal data bus of 8255 to the system data bus. ‘The instruction executed by the microprocessor can read the data from the buffer or write the data into the buffer. Similarly, the control registers and the status registers all passed through the buffer. Control Logic The control logic block accepts control bus signals as well as inputs from the address bus and generates the commands to the individual group control of Group A and Group B.3 programmable Peripheral Interface 3.7 The Control Logic has six lines, They are FD Read): mR (Write): A,and A This control signal enables the Read operation. When the signal is low, the CPU reads data from a selected I/O port of the 8255. This control signal enables the Write operation. When the signal is low, the CPU writes data or controls word into 8255. The selection of input poit and control word register is done by using A, and A,. It specifies one of the I/O ports (or) the control register as given below. A Selected Ports/ A 0. Control Word Register 0 Port A 1 Port B 0 Port C 1 Control Word Register. RESET (Reset): CS (Chip Select): This is an active high signal; it clears the control register and sets all ports in the input mode. It is a Chip Select Signal. The low status of this signal enables communication between the CPU and the 8255. i.e, BS Selected 0 8255 is selected. 1 8255 is not selected. 3.3.3. OPERATING MODES OF 8255 ‘The functions of 8255 is classified. into two modes (). BSR Mode (i). YO Mode