EN-6110 Computer Architecture

EN-7110 Advanced Computer

Architecture
Lecture # 3
RISC-V Assembly Language

Dr. Syed Azhar Ali Zaidi

Assistant Professor
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Components of a Computer

2
Levels of Representation/Interpretation

3
Assembly Language

4
5
Mainstream ISA

6
Variables in Hardware

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Registers vs. Memory

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 RISCV Registers

– Registers are 32-bit (word), 64-bit (doubleword) and

128-bit (quadword) in RV32, RV64 and RV128 bit
variants.
• Why 32? Because smaller is faster. But too small
is bad.
• Also affect the number of bits in the instruction
format.
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 RISCV Registers
• x0 is special registers which holds value zero.
• Registers can also be accessed by their names
(discussed later)
• Operation in RISCV can only be performed on
registers.
• Compiler must carefully put together the code in
order to efficiently use registers.
• Registers have no type. The operation performed
determine how the data in register is treated.
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 RISCV Instructions
• Each line of assembly language contains at
most 1 instruction
• Instructions are closely related to the common
high-level language operations.
add x1, x2, x3
add x1, x1, x4

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 RISCV Instruction Syntax

• 1 operator, 3 operands
• Keep hardware simple via regularity.

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RISCV Addition and Subtraction

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RISCV Arithmetic: Example1

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RISCV Arithmetic: Example2

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 Zero Register

add x5, x0, x0 # x5 = 0

add x1, x2, x0 # x1 = x2

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 Constant or Immediate Operands

• Make common case fast! Constants are so frequent in programs.

• NOP – addi x0, x0, 0
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Memory Operands – Data Transfer

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Memory Operands – Data Transfer
• Load

• Store

• Different variations of load and store instructions:

– ld, lw, lh, lb, lwu, lhu, lbu
– sd, sw, sh, sb store 64-bit, 32-bit, 16-bit and 8-bit from the
low bits of register to memory
– In 128 bit variant lq and sq are added to load and store
128-bit values

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Memory is Byte-Addressed

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Big Endian vs. Little Endian

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Data Transfer Instructions - Examples

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Data Transfer Instructions - Examples

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Alignment Restriction

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RISC-V Logical Instructions

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RISC-V Logical Instructions

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Logical NOT Operation in RISCV

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Logical Shifting

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Arithmetic Shifting

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Decision Making Instructions

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Types of Branches

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Example if Statement

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Example if-else Statement

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Other Conditional Branch Instructions

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Loops in C/Assembly

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C Loop Mapped to RISCV Assembly

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