See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/221594932

Well tapping methodologies in power-gating design

Conference Paper · September 2011

DOI: 10.1109/SOCC.2011.6085133 · Source: DBLP

CITATIONS READS
2 2,083

2 authors, including:

David Tester
EnSilica Ltd
2 PUBLICATIONS   2 CITATIONS   

SEE PROFILE

All content following this page was uploaded by David Tester on 27 December 2018.

The user has requested enhancement of the downloaded file.

 WELL TAPPING METHODOLOGIES IN POWER-GATING DESIGN
Kaijian Shi1 and David Tester2
1 2
Cadence Design Systems, Dallas, USA and Structured Custom, Cambridge, UK
kaijians@cadence.com and david.tester@structured-custom.com
ABSTRACT
65nm and beyond CMOS designs are commonly
implemented with “tapless” library cells which do not
provide built-in n-well or substrate taps, improving cell
density. This cell efficiency results in additional layout
complexity for power-gating designs. Three well
tapping methods are described for production power-
gating designs considering design schedule, leakage
power, chip area and complexity.
I. INTRODUCTION
Tapless designs have been popular in 65nm and
beyond CMOS designs to increase cell density and
silicon area efficiency. In tapless designs, the logic is
implemented using cells which do not have built-in tap
contacts connecting n-well and p-substrate to power
and ground rails in the cells. To prevent latch-up and
maintain proper transistor back biasing, tap cells
which have built-in contacts to n-well and p-substrate
are inserted in the layout at required intervals to
connect n-wells to VDD and p-substrate to VSS,
based on design rules defined in the technology DRC
file. The n-wells of tapless logic cells extend out of the
cell boundaries to ensure n-well connections when
the cells are placed next to each other. Consequently,
n-well and p-substrate regions of the logic cells are
properly biased by power and ground supplies.
through the tap cells insertedin the design..
The tap insertion becomes complicated in power-
gating designs [1-6] where logic cells can be
powered-off while power management (PM) cells,
such as power switch cells, isolation cells, retention
registers and always-on logic cells, must remain
powered to maintain controllability and state retention
within the design. For power-gating designs that
implement header switches to shut off power supply,
the main challenge is to maintain proper n-well bias in
those logic cells that are powered-off and the PM cells
that remain alive.
Three well tapping methods are described in this
paper, addressing challenges in power-gating designs
using tapless standard cells. The methods have been
applied successfully to production designs meeting
different design goals and priorities.
The first method implements always-on tap cells to
keep n-well biased at VDD when the design operates
in the shutdown mode, i.e. power gated.
The second method requires built-in taps in the PM
cells to maintain well biasing of the PM cells when the
design is in the shutdown mode.
The third method partitions the design into always-
on and shut-down regions. The PM cells are placed
exclusively in the always-on region to sustain required
n-well biasing.
Each method has advantages and shortcomings.
The choice of method depends on the considerations
and priorities on leakage power, silicon utilization
efficiency and implementation complexity.
In the following part of the paper, the methods will
be described in detail. Considerations for reliable
production power-gating designs will be discussed.
Overheads and tradeoffs will be explained. Next, the
three methods will be compared in terms of impact on
leakage power, silicon utilization efficiency and
implementation complexity. Finally, recommendations
will be provided for selection of a method based on
design goals and priorities.
II. ALWAYS-ON TAP CELL BASED METHOD
The first method provides dedicated power supply
to n-wells using the tap cells to keep n-wells of the
design biased to VDD in shutdown mode. This
requires an always-on tap cell, since the normal tap
cells are not powered in the shutdown mode.
A. Always-on tap cell vs. normal tap cell
The normal tap cell is a simple design (Fig. 1a)
which has two metal contacts; one connects n-well to
VDD rail and the other connects p-substrate to VSS.
When the tap cells are inserted into a design, their
VDD and VSS rails are connected, by abutment, to
the power and ground network of the design to
provide n-well bias. In the power-gating design, the
power supply to VDD rails is shut-off in the shutdown
mode. To maintain the power supply to the n-well, the
n-well contact in the tap cell must be separated from
the VDD rail and directly connected to the power
supply. This design change is depicted in Fig. 1b
resulting in the always-on tap cell where the n-well
tap becomes a pin that can be connected to the chip
power supply. The p-substrate is still connected to
VSS rail to maintain well bias as the VS
SS rail remains
connected in the shutdown mode.
logic never reaches close to ground because the
switch cells are far from ideal and
a considerably leaky
in 40nm node and beyond. Also, A the size ratio is
determined by IR-drop constraints and power density
of the design in normal operration mode. Table 1
shows the leakage penalty of always-on n-well
biasing from SPICE simulation of a small test case in
different technology nodes and Vth’s. Size ratio of the
switch to logic cells is 0.096.

Table I. Ioff in gated nwell vs

s. always-on nwell
Ioff_well_off Iofff_well_on
Node/Vth Ioff_ratio
on tap cell
Figure 1 a) normal tap cell, b) always-o (nA) (nA)
28HP/LVt 16.2 77.4 4.78
B. Method description 28HP/SVt 15.78 153.4 9.72
For a single domain power-gating g design, the 28HP/HVt 12.9 57.65 4.47
always-on tap cells are inserted at the intervals
defined by the technology tapping rules. Then, the 40LP/LVt 0.169 1.06 6.27
n-well pins of the tap cells are routed to connect the 40LP/SVt 0.166 1.43 8.61
always-on VDD supply network in the design to get 40LP/HVt 0.143 1.05 7.33
constant power supply. Since n-wells of the tapless
logic cells are overlapped with adjacen nt cells in each 65LP/LVt 0.082 0.443 5.40
row in the layout, forming continuing n-w wells in the cell 65LP/SVt 0.081 0.439 5.42
rows, the n-wells of the logic cells are biased by the 65LP/HVt 0.070 0.467 6.67
always-on VDD through the tap cells’ n--wells.
The main advantage of the metho od is that it is
simple to implement, leveraging the e existing normal In power-gating designs with both always-on and
tap insertion flow. It also results in highest silicon power gated power domains, th he always-on tap cells
utilization efficiency compared with o other methods, are inserted in the power gatedd domains. For always-
due to no additional well spacing requ uirement in cell on domains, normal tap cells are a use to avoid VDD
placement. Moreover, it does not impo ose constraints power routing needed for always-on
a taps. An
on PM cell placement which helps physsical synthesis. example of the method implem mented in a two power
However, the method incurs a leakage power penalty domain design is shown in Fiig. 2. The bottom left
in the shutdown mode because n-w wells of pMOS domain is always-on with norm mal tap cells inserted
transistors are biased at VDD while the e power supply aligned to the rails. Always-on taps were implemented
to the transistors is shutoff. This createes a significant in the rest of the design with w tap n-well pins
bias from n-well to drain and gate of p pMOS resulting connected to the always-on VDD D straps next to them.
in higher junction and gate leakag ge in pMOS.
Consequently, the shutdown mode leakage of a III. TAP PM CELL BASED MET THOD
design can increase up to 10 times depending on For leakage critical designs, the leakage penalty in
technology nodes, Vth cell types and ssize ratio of the the always-on tap cell based method
m might not meet
switch and logic cells. At smaller tech hnology nodes the leakage target. In that case,, it is necessary to shut
this causes a higher leakage penaltty due to the off the power supply to the n-w well taps. However, PM
thinner tox and hence larger well lea akage. On the cells are active in shutdown modem so n-wells in the
other hand, lower Vth logic cells ha ave a smaller PM cells must remain being biased at VDD to be
leakage penalty because the reductio on of the sub- functional. To address this issue, the tap PM cell
threshold leakage from the reversed back biasing based method has been developed.
becomes more effective and the re elatively large The method implements sp pecially designed PM
leakage makes the n-well leakage co ontributing part cells containing built-in n-well taps that connect to
relatively less effective. As we look to th
he dependency their internal always-on power straps
s (Fig. 3) keeping
on the transistor size ratio of the sw witch and logic n-well biased in shutdown mode, This results in a
cells, a smaller ratio results in larger le
eakage penalty mixed tap and tapless design wherew PM cells are tap
due to lower shutdown voltage on the logic cells and cells and rest of the logic cells are
a tapless cells. In the
hence lower cell leakage and higher n-w well leakage. It shutdown mode, the power su upply to the tap cells
is worth mentioning that the shutdown voltage on the inserted in the tapless design re egions is shut off which
 Figure 3. Tap PM cell (double row)

Figure 2. Domain-based tap insertion e

example region based method describe ed in the next section.
PM cells can be freely placed in i optimal positions as
in turn shuts off power to the n-well of llogic cells. The long as their always-on VDD pin ns can be routed to the
n-well of the PM cells is biased through internal taps always-on power straps. Ho owever, the method
to the always-on VDD, maintaining norm mal operation. requires custom PM cells and area a wasted at left and
Since n-well of the PM cells is biased while right boundaries of the PM cell is significant lowering
surrounding n-well in the tapless lo ogic cells are silicon utilization efficiency cons
siderably since power-
shutoff, the n-well of PM cells can no longer overlap gating designs often impleme ent tens of thousands
n-well in surrounding tapless cells. Well spacing switches, always-on buffers and d isolation cells.
between PM cells and tapless cells m must satisfy the
hot-well spacing rule defined in the te echnology. It is IV. ALWAYS-ON REGION BAS SED METHOD
worth noting that the n-well of a tapless cell is This method has been developed to avoid the
extended beyond the cell boundary so n-wells of the leakage penalty of the first metthod and the design of
tapless cells are overlapped forming a continuous n- custom tap PM cells in the se econd method. In this
well. This tapless cell n-well extension wwill intrude into case, PM cells are all tapless cells requiring tap cell
the PM cell placed next to the tapless cell, and insertion to maintain n-well bias
s. To address the need
therefore must be considered in the ho ot-well spacing of separating n-wells of the PM M cells from the n-wells
check. Consequently, PM cells need d considerable of the logic cells, placement reg
gions, called always-on
space at cell boundaries, consuming ssilicon area. In regions, are created exclusively for PM cells. Each
production designs, cells are common nly mirrored on always-on region has its own dedicated always-on
e mirrored rows
adjacent rows and n-wells of cells in the VDD rails separated from rails outside
o the region. The
overlap. This is leveraged in designin ng the tap PM n-well of the cells in the regioon is connected to the
cells to occupy both mirrored rows to hide the n-wells always-on VDD through tap cells inserted in the
of the PM cell from the top and botttom of its cell region. These always-on region ns are placed cross the
boundaries and hence eliminate needs of the hot-well chip based on the prediction n of the needs and
spacing at top and bottom to improve a area efficiency. positions of the PM cellls in the physical
Fig. 3 shows an example PM cell. implementation. In the physic cal synthesis, the PM
Only those PM cells that require pM MOS transistors cells are only allowed to be pla aced in the always-on
to be active in shutdown mode need bu uilt-in well taps. regions. An illustration example is shown in Fig. 4.
For those isolation-low cells which imp plement a pull- The always-on regions are shown
s in red. The top
down nMOS at the output, there is no need for the tap and bottom regions are for switc ch cells. The region on
version cells, because pMOS transistors of the cell do the right is where the output iso
olation cells are placed.
not contribute to the isolation in the shhutdown mode The four regions in the middle of
o the block are created
and so isolation-low cells can be taplesss. to place always-on repeaters.
The main advantage of the method is low leakage Advantages of the method are a low leakage power
power in shutdown mode, since n-we ell of the logic in shutdown mode and no need d to create the custom
cells are not biased. Impact on the physical tap PM cells. However, the e method introduces
implementation is much smaller than the e always-on considerable physical implem mentation complexity.
 Moreover, the region creation and p placement are timing models of the tapless PM M cells, as modification
highly design dependent and difficultt to predict. It has minimal impact on fun nctional layout. Area
could often result in lower silicon utiliza
ation efficiency overhead of the method is usua ally less than 5%.
and negative impact on design timing an nd routability. The always-on region based method is much more
complicated to implement and less predictable in its
effect on the design. Moreove er, it often impacts the
design timing and routability. The area overhead
varies with the quality of the t always-on region
planning and could be significant. However, the
method does not introduce a leakage penalty, nor
requires development of custom m PM cells.
The choice of the method depends
d on the design
goals and priority in terms off design performance,
leakage power, schedule, and a silicon area. If
development schedule and pe erformance are higher
priorities than leakage power in n shutdown mode, the
always-on tap based method is the choice. On the
other hand, for battery operated designs where
shutdown mode leakage is critic cal and area efficiency
is less important, the tap PM cell
c based method is a
Figure 4. Always-on region based m
method good choice. In the case where e design resources are
not available to create the tap PM
P cells, the always-on
An always-on region can be created by either an region based method is an alterrnative method.
exclusive region or a custom placeme ent site. In the
former case, a special filler cell not containing n-well VI. SUMMARY
is needed at region boundaries to se eparate the n- Three well tapping methods have been developed
wells from outside. VDD rails in th he region are e tapless power-gating
to address the challenges in the
assigned to the always-on VDD and sseparated from designs. The methods are a described with
rails outside of the region. implementation details. Each method
m has advantages
ng is done after
In practice, always-on region plannin and shortcomings which are discussed and
initial physical implementation to scope how many PM compared. The proper choice of o the method depends
cells are needed and where they should be placed. on design goals and priorities in terms of design
Assuming PM cells can be clustered into regions, the performance, leakage power, development
d schedule,
always-on regions are created and pla aced based on and silicon area. The method ds have been applied
size and position requirements. To ensu ure the regions successfully to production pow wer-gating designs to
can hold the required PM cells, always--on regions are meet different design goals and priorities.
often created larger than actually needed. This
reduces silicon utilization efficiency. REFERENCES
[1] Kaushik Roy, Saibal Mukhopadhyyay, and Hamid Mahmoodi-
Always-on regions also add placeme ent constraints meimand, “Leakage current mecha anism and leakage reduction
and obstructions, impacting placemen nt and routing. techniques in deep-submicrometer CMOS circuits”, Proc.
This could result in sub-optimal physical synthesis. IEEE Vol. 91, no. 2, Feb. 2003
[2] M. Anis, S. Areibi and M. Elmasry,, “Design and optimization of
V. COMPARISON AND RECOMMEND DATION multi-threshold CMOS (MTCMOS)) circuits”, IEEE Trans. CAD-
ICS, 2003
Each method is appropriate for volu ume production [3] Benton H Calhoun, Frank A Honore and Anantha P
designs and has advantages and shorrtcomings. The Chandrakasan, “A leakage re eduction methodology for
always-on tap cell based method is simple to distributed MTCMOS”, IEEE J. Solid-State
S Circuits, vol. 39,
implement with little impact on timing, routability and no. 5, May, 2004, pp. 818-826
[4] Kaijian Shi and David Howard, “S Sleep Transistor Design and
silicon utilization efficiency at the expen
nse of leakage Implementation – Simple Concepts Yet Challenges To Be
power. Optimum”, Proc.. IEEE VLSI-DAT, April, 2006
The tap PM cell method is easy to implement with [5] David Flynn, Michael Keating, Robert Aitken, Alan Gibbons
little impact on timing and routability. IIt does require and Kaijian Shi , “Low Power Methhodology Manual for System-
on-Chip Design”, Springer, 2007
custom design of tap PM cells, though they can be
[6] Kaijian Shi, Zhian Lin, Yi-min Jian
ng, Lin Yuan “Simultaneous
relatively easy to create by adding well taps and Sleep Transistor Insertion and Po ower Network Synthesis for
extending cell boundaries of the taplesss version PM Industrial Power Gating Design ns”, Journal of Computer,
cells that are already available. It is fea
asible to reuse Academy Publisher Vol. 3 No.3 March,
M 2008

View publication stats