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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TII.2018.2815035, IEEE
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> TII-18-0138<
Fast Finite-Switching-State Model Predictive Control
Method without Weighting Factors for T-type Three-level
Three-phase Inverters
Yong Yang, Member, IEEE, Huiqing Wen, Member, IEEE, Mingdi Fan, Member, IEEE, Menxi Xie,
Rong Chen
 efficiency, electromagnetic interference (EMI), and reliability
Abstract—Model predictive control (MPC) suffers from high
computational burden and cumbersome tuning of weighting
factors especially for three-level three-phase inverters. Here a fast
finite-switching-state model predictive control (FSS-MPC)
algorithm without weighting factors is proposed. Firstly, the
deadbeat (DB) control is used to construct the voltage vector
reference. Then, the T-type three-level three-phase inverter
topology is selected and voltage vectors are carefully tuned in
order to minimize the neutral-point (NP) voltage fluctuation. The
voltage vectors that are far from the desired voltage vector
reference and go against balancing the NP voltage will not
participate in the cost function optimization. Thus, only three
effective voltage vectors instead of totally 27 vectors are required
in the implementation of the proposed FSS-MPC algorithm,
which saves computation time up to 53.3%. Furthermore, the
proposed algorithm makes the tuning of the weighting factor
unnecessary, which simplifies the practical implementation and
improves the portability of the algorithm. Finally, an
experimental prototype was established and main results
including the steady-state and dynamic performance were
presented to validate the effectiveness of the proposed algorithm.
Index Terms—Finite-switching-state model predictive control,
T-type three-phase three-level inverters, deadbeat control, NP
voltage, cost function.
I. INTRODUCTION
I NVERTERS, including two-level voltage source inverters
(2L-VSI), multi-level inverters, have been extensively
investigated with the quick development of electrical drives,
telecommunication, and especially renewable energy such as
solar energy, wind power and bio-energy in recent years [1-3].
As a bridge between the renewable energy sources and loads,
inverters need to meet the strict requirements in terms of both
steady-state and dynamic performance, such as harmonics,
Manuscript received October 1, 2017; revised December 13, 2017; accepted
February 27, 2018. This work was supported in part by the National Young
Natural Science Foundation of China (51407124), in part by China
Postdoctoral Science Foundation (2015M581857), and in part by Suzhou
prospective applied research project (SYG201640). Paper no. TII-18-0138.
(Corresponding author: Huiqing Wen.)
Y. Yang, M. Fan, M. Xie, R. Chen are the School of Rail Transportation,
Soochow University. Suzhou 215131, China (e-mail:yangy1981@suda.edu.cn,
mdfan@suda.edu.cn, xiemenxi@163.com, chrong@suda.edu.cn).
H. Wen is with the Xi’an Jiaotong-Liverpool University, Suzhou 215123,
China (e-mail: huiqing.wen@xjtlu.edu.cn)
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1
[4-6]. Conventionally, 2L-VSI is commonly used, however, it
suffers from high electrical stress and harmonics especially for
medium or high voltage applications. Compared with the
2L-VSI, multi-level inverters own obvious advantages such as
low harmonics of the output voltages and currents, higher
operation voltage and power, and reduced dV/dt, which are
beneficial for the EMI suppression. There are many 3L-VSI
topologies such as the neutral-point clamped (NPC) VSI, flying
capacitor VSI, cascaded H-bridge VSI and T-type three-level
three-phase inverters. Compared with the NPC inverters, the
T-type three-level three-phase inverter can reduce six power
diodes, improve the conversion efficiency for the 5-30 kHz
switching frequency range [7-9], and minimize the neutral point
(NP) voltage fluctuation. Thus, the T-type three-phase
three-level inverter is preferable for the distributed power
generation systems.
Control of the T-type three-level three-phase inverter is
another important issue for the performance improvement.
Among various control strategies for power converters such as
the grid voltage orientation vector control, direct power control,
current hysteresis control, current predictive control and power
predictive control [1-9], model predictive control (MPC) has
gained increasing attention with the development of powerful
microprocessors. The basic concept of MPC sets control
objectives and designs cost functions in order to predict the
future system state in finite time domain and determine the
current action. For the control of power converters, the
finite-switching-state model predictive control (FSS-MPC)
becomes increasingly popular since it can utilize fully different
combinations of switching states of power converters and
achieve the optimized performance [10-18]. Specifically, the
behavior of each switching combination is evaluated by the
FSS-MPC according to the set cost function, and the optimal
switching combination that satisfies the minimum cost function
is selected for the control of the power electronic converter
[10-18]. With the help of advanced digital signal processor
(DSP) technology, FSS-MPC provides improved steady-state
and dynamic performances when compared with other
strategies such as direct power control and hysteresis control.
Considering the online calculation of the predictive model
and the implementation of the cost function to achieve the
optimal performance, complex computation seems unavoidable
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for the practical implementation of the FSS-MPC. Furthermore,
the execution time becomes significantly longer with the
increasing complexity of power converters and the number of
switching states. For instance, 2L-VSI totally owns 8 switching
states, while 3L-VSI has 27 switching states. For 4L-VSI, there
are totally 64 switching states. Literature [19] points out that the
execution time of the FSS-MPC algorithm is 52 μs for
three-level three-phase inverters. However, as presented in [20],
the execution time of the FSS-MPC algorithm for the five-level
three-phase inverters is high up to 93 μs. In order to fully
exploit the advantages of the FSS-MPC algorithm especially
for multi-level inverters, the execution time of the FSS-MPC
must be reduced. Recently, many methods have been presented
to relieve the computational burden in FSS-MPC. In [21],
branch and bound techniques are used for very long prediction
horizons, which directly provide the optimal switching and
requires few computations. In [22], a deadbeat (DB) solution is
proposed for permanent-magnet synchronous motor drives,
which optimizes the selection of the best switching vector and
reduces the effective voltage vectors from eight to three. In [23],
a system model is built to predict the system behavior and
selects the most appropriate voltage vector. Furthermore, a
graphical algorithm is adopted to reduce the computational
burden in implementing FSS-MPC algorithm for three-phase
two-level inverters. In [24], a low-complexity FSS-MPC
algorithm is proposed and only one prediction is required to
allocate the best voltage vector according to the desired voltage
reference. According to a new direct torque control switching
table, a simplified algorithm is proposed in [25] and only three
voltage vectors instead of eight are employed for inductor
motor drive. However, most these methods have been
evaluated for 2L-VSIs, for a T-type three-level three-phase
inverter, some methods may become ineffectiveness
considering the significantly increased switching states. Many
algorithms have been proposed to address the computational
burden for multi-level multi-phase inverters applications. In
[26], a reduced number of FSS-MPC is proposed for a
three-level three-phase inverter fed motor according to the
stator flux position and the deviation of stator flux. In [27],
considering the torque and power control of wind turbine
system fed by three-level neutral-point clamped back-to-back
converters, two computationally efficient FSS-MPC methods
with hexagon candidate region and triangle candidate region
were presented, which effectively reduce the computational
time. In [28], the sphere-decoding algorithm is discussed in
FSS-MPC to reduce the execution time.
implementation of FSS-MPC algorithms. For a multi-objective
FSS-MPC design, the weighting factors are usually obtained by
trial and error procedures, which are time-consuming [30-31].
Furthermore, the actual performance is highly dependent on the
specific system parameters and operating point. Thus, it is vital
to find a novel FSS-MPC algorithm that can simultaneously
achieve good performance and remove the cumbersome
selection of weighting factors. In [32], based on a ranking
approach, a predictive torque and flux control without
weighting factors is proposed for three-phase 2L-VSIs. In [33],
by converting the torque and flux reference into an equivalent
stator flux reference, the weighting factor of stator flux is
eliminated in the improved model predictive torque control. For
the application of a permanent magnet synchronous motor fed
by a matrix converter, [34] proposed an improved FSS-MPC
without weighing factors by using a multi-objective
optimization. In [35], a novel cost function according to the
voltage vector tracking error is used in the predictive torque
control and eliminates the weighting factors. However, for the
multi-level converters, how to eliminate the weighting factor in
the FSS-MPC still needs further investigation.
This paper proposes a fast FSS-MPC without weighting
factors for T-type three-phase three-level inverters. The
performances in terms of algorithm execution time, harmonics,
NP voltage, and dynamic response have been extensively
investigated.
II. PROPOSED ALGORITHM
A. Predictive model of T-type three-level three-phase
inverters
Fig. 1 shows the structure of T-type three-level three-phase
inverter power generation system, which is composed by
renewable energy (such as photovoltaic and wind power),
T-type three-level three-phase inverters, L-type filter and loads.
In Fig.1, renewable energy is represented by the DC power
source Edc with its equivalent resistance Rdc. The T-type
three-level three-phase inverter is the power interface to
regulate the active power and reactive power. Vdc is the dc-link
voltage of the inverter; uan , ubn, and ucn represent the output
phase voltages of the T-type three-level three-phase inverter; ia ,
ib, and ic represent output currents of the inverter; L refers to
filter inductance; and R is the load.
P
ic2
Vp
Sa1 Sb1 Sc1
Loads
C Sa2 Sa3
uan ia L R

Another key issue for the implementation of the FSS-MPC is R dc

Vdc io Sb2 Sb3 ubn ib
n
the selection of weighting factors considering the Edc
o
Sc2 Sc3 ucn ic
multi-objective application. Different control targets, variables, ic1
Vn
and constraints are required to equip with appropriate C
Sa4 Sb4 Sc4
weighting factors in the predefined cost function. Considering
that the actual performance of a target is highly dependent on Renewable N
energy
the selection of the corresponding weighting factors, the tuning
of weighting factors for a multi-objective design becomes a Fig. 1. Structure of T-type three-level three-phase inverter
challenging task [29-31]. However, so far, no clear guideline generation systems.
has been provided for the selection of weighting factors in the In Fig. 1, according to different switching combinations,
each phase leg in the T-type three-level three-phase inverter

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may output the following three states: “P” state, “O” state and  R / L 0 0 S a11 / L S a12 / L 
A1   0 Sb 21 / L Sb 22 / L  . (5)
“N” state: (1) “P” state: Taking phase a as example, power
R / L 0
electronic switches Sa1 and Sa2 are simultaneously on while Sa3
and Sa4 are simultaneously off, and phase a output voltage is  0 0  R / L Sc 31 / L Sc 32 / L 
uaN =Vp+Vn when the point N is considered as the reference According to the circuit structure, switching states and phase
voltage; (2) “O” state: Power electronic switches Sa2 and Sa3 are currents, the NP current io of the T-type three-level three-phase
simultaneously on while Sa1 and Sa4 are simultaneously off, and inverter can be obtained as follows:
phase a output voltage is uaN =Vn ; (3) “N” state: Power io  ( S a 2  S a1 )ia  ( S b 2  S b1 )ib  ( S c 2  S c1 )ic  ic 2  ic1 . (6)
electronic switches Sa3 and Sa4 are simultaneously on while Sa1
Assuming that the inverter’s dc-link voltage Vdc is constant,
and Sa2 are simultaneously off, and phase a output voltage is
the lower dc capacitor current ic1 can be derived as follows:
uaN =0. According to switching combinations by three-level
three-phase inverters, the T-type three-level three-phase ic1  C dVn dt  C d (Vdc  Vp ) dt  C dVp dt  ic 2 . (7)
inverter generates 33=27 voltage vectors in total, whose By combining (5) and (6), it can be drawn as:
magnitudes and spatial positions are illustrated in Fig. 2 [36]. ic1   (( Sa 2  Sa1 )ia  ( Sb 2  Sb1 )ib  ( Sc 2  Sc1 )ic ) 2
 (8)
V19

V18 V17  ic 2  (( Sa 2  Sa1 )ia  ( Sb 2  Sb1 )ib  ( Sc 2  Sc1 )ic ) 2.
      By combining (4), (7) and (8), it can be obtained as:
V20
V7 V5 V16
 ia   ia 
i  i 
   
V8
 
V6
 
d  b   b
V9 V3
Vref
 ic   A 2  ic  (9)
V21 V0 V15 dt    
V p  V p 
V1

V2
V4
V10
V11 V13
Vn  Vn 
V22
   
V26 where matrix A 2 is defined as follows:
V12 V14
 R / L 0 0 S a11 / L S a12 / L 
 0 R / L 0 Sb 21 / L Sb 22 / L 
V23 V24 V25

A2   0 0 R / L S c 31 / L Sc 32 / L  (10)
Fig. 2. Output voltage space vectors of three-level three-phase  
 K1 / C K2 / C K3 / C 0 0 
inverter.   K1 / C K2 / C  K3 / C 0 0 
The inverter output voltage uan, ubn and ucn with respect to the
load neutral point n can be obtained as [20]: where
u an   2 S a1  S b1  S c1 2 S a 2  Sb 2  S c 2   K1  ( S a 2  S a1 ) 2
u   1   S  2S  S V  
 bn  3  a1 b1 c1  S a 2  2 S b 2  S c 2   p  . (1)  K 2  ( Sb 2  Sb1 ) 2 (11)
Vn   K  ( S  S ) 2.
 ucn    S a1  S b1  2 S c1  S a 2  S b 2  2 S c 2   3 c2 c1

The matrix can also be defined as: Assuming the sampling period Ts is very small, firstly, the
 2 S a1  Sb1  Sc1 2 S a 2  Sb 2  Sc 2   S a11
S a12  discrete formulation (9) is obtained by using forward-Euler
1 approximation. Then, coordinate transformation from the
  S a1  2 Sb1  Sc1  S a 2  2 Sb 2  Sc 2    Sb 21
Sb 22  . (2) stationary abc reference frame into the αβ reference frame is
3
  S a1  Sb1  2 Sc1  S a 2  Sb 2  2 Sc 2   Sc 31
Sc 32  carried out, it can be derived as
According to the current reference direction in Fig. 1, the  Ts
 i (k  1)  L ( S 11V p (k )  S 12Vn (k )  Ri (k ))  i ( k )
dynamic output currents of the T-type three-level three-phase 
inverter in stationary abc reference frame can be expressed as: i (k  1)  Ts ( S V (k )  S V (k )  Ri (k ))  i (k )
 L dia dt  uan  Ria  L
 21 p  22 n  

 
 L dib dt  ubn  Rib (3)  V (k  1)  V (k )  Ts ( K i (k )  K i (k )  K i ( k ))
 L di dt  u  Ri  p p
C
1a 2b 3c
 c cn c. 
By combining (1), (2) and (3), it can be derived as:  Vn (k  1)  Vn (k )  Ts ( K1ia (k )  K 2ib (k )  K3ic (k ))
 C
 ia  (12)
i 
ia   b where iα(k) and iβ(k) are the α component and β component
d   output currents of the inverter at the (k)th instant, Sα11, Sα12, Sβ21
i  A  
1 ic (4)
dt  
b
  and Sβ22 are the switching state functions of the inverter in the
 ic  Vp  αβ reference frame and it can be defined as
Vn 
 S 11 S 12  (2Sa1  Sb1  Sc1 ) / 3 (2Sa 2  Sb 2  Sc 2 ) / 3
where the matrix Α1 can be given as: S  .
  21 S  22   3( Sb1  Sc1 ) / 6 3( Sb 2  Sc 2 ) / 6 
(13)

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From the equation (13), it can be found that the predictive
dc-link bus capacitor voltages Vp (k+1) and Vn (k+1) at the
(k+1)th instant can be predicted by the present measured
capacitor voltages, the measured inverter output phase currents
and applied inverter switching states. Therefore, measuring the
dc-link bus top and bottom capacitor currents can be avoided.
B. FSS-MPC with weighting factors
Assuming that the inverter output currents can track the
given currents at the (k+1)th instant in the αβ reference frame, it
can be expressed as
 i ( k  1)  i* ( k )
 *
(14)
i ( k  1)  i ( k )
where i*α(k) and i*β(k) are the α component and β component
output reference currents of the inverter at the (k)th instant.
Considering the constant sampling period, according to the
Lagrange extrapolation theorem, the inverter current reference
at the (k+1)th instant can be expressed as followings [37]:
n
( n  1)! *
i* ( k  1)   ( 1) n  l i ( k  l  n). (15)
l 0 l !( n  1  l )!
The order number n should be no less than 2 for the
sinusoidal references. Here, two-steps-ahead prediction is used
and the parameter n is set as 2. Thus, the output current
references in the αβ reference frame can be expressed as:
 i* ( k  1)  3i* ( k )  3i* ( k  1)  i* ( k  2)
* (16)
* * *
i ( k  1)  3i ( k )  3i ( k  1)  i ( k  2).
For T-type three-level three-phase inverters, the
conventional FSS-MPC has two control objectives. The one
object is the accurate and fast tracking of the inverter reference
current, and the other target is the balance of the inverter NP
voltage. Thus, based on current predictive mode, the cost
function can be expressed as:
g1 ( k )  i* ( k  1)  i ( k  1)  i* ( k  1)  i ( k  1)
(17)
 v1 ( V p ( k  1)  Vn ( k  1) )
where λv1 is a weighting factor based on current model, which
sets the relative importance of the phase current tracking and
the NP voltage balancing.
From the equation (12) and (17), it can be observed that it
needs 27 current predictive model calculations, 27 predictive
capacitor voltage calculations and 27 cost function evaluations
for the conventional FSS-MPC algorithm based on current
predictive mode, which becomes time consuming for the
practical implementation of the conventional FSS-MPC
algorithm.
The FSS-MPC based on desired voltage vector is adopted to
reduce computation burden. The discrete form of (3) by using
forward-Euler approximation can be obtained as:
uan *
( k )  L[ia* ( k  1)  ia ( k )] Ts  Ria ( k )
 * * io  ib  ic .
 ubn ( k )  L[ib ( k  1)  ib ( k )] Ts  Rib ( k ) (18)
 * *
 ucn ( k )  L[ic ( k  1)  ic ( k )] Ts  Ric ( k )
where u*in(i=a,b,c)(k) represent phase reference voltage at the
(k)th instant, respectively.
Through coordinate transformation from three-phase
stationary frame to two-phase stationary frame, (18) can be
obtained as [20]
 u* n ( k )  L[i* ( k  1)  i ( k )] Ts  Ri ( k )
 * *
(19)
u  n ( k )  L[i ( k  1)  i ( k )] Ts  Ri ( k )
where u*αn(k) and u*βn(k) mean the α and β components of
reference voltages at the (k)th instant, respectively.
Expression (19) shows that the phase current tracking can be
ensured if the exerted voltage vector follows the voltage
reference computed with (19). By analyzing the output voltage
vector distribution in Fig. 2, an idea is inspired to adopt and
apply the voltage vector to achieve an accurate and fast tracking
of the inverter reference currents and the NP voltage balance.
Then, the cost function of the FSS-MPC based on desired
voltage vector can be updated as:
g 2 ( k )  u* n ( k )  u n ( k )  u * n ( k )  u  n ( k ) 
(20)
v 2 ( V p ( k  1)  Vn ( k  1) )
where λv2 is the weighting factor of balancing the NP voltage.
From (19) and (20), it can be found that the FSS-MPC based
on desired voltage vector avoids 27 inverter output current
predictions at the (k)th instant, which largely decreases the
computational burden.
C. Fast FSS-MPC without weighting factors
In order to further reduce the computation burden especially
the cost function calculation and predictive model computation
of dc-link bus top and bottom voltages, the voltage vectors that
are far from the inverter output voltage reference vector will not
participate in the cost function optimization calculation.
Assuming the reference voltage vector Vref (k)= u*αn (k)+j u*βn (k)
is located at the fourth small sector of the large sector I, as
shown in Fig. 2, the candidate voltage vectors for cost function
evaluations are V3 (POO), V4 (ONN), V15 (PNN) and V16 (PON).
Then, the candidate voltage vectors in other sectors can be
obtained.
The NP unbalance is one of main design challenges for
T-type three-level three-phase inverters and it will affect the
reliability and lifetime of the inverter system [37-38]. Voltage
vectors of the inverter can be classified as large, middle, small
and zero voltage vectors in the total 27 voltage vectors of
3L-VSI. The NP voltage will not be influenced for large and
zero voltage vectors, but both the middle and small voltage
vectors affect the NP voltage fluctuation. Furthermore, small
voltage vectors can be further classified as positive small
voltage vectors and negative small voltage vectors considering
different effects on the NP voltage. Effects of the switching
states (POO, ONN) on the NP voltages of the inverter are
illustrated in Fig.3. As displayed in Fig. 3(a), regarding the
effect of the positive small voltage vector (POO) on the inverter,
the neutral point current io can be obtained as:
(21)
Regarding the effect of the negative small voltage vector
(ONN) on the inverter, the neutral point current io can be
expressed as:
io  ia . (22)

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In a balanced system, three-phase currents of the inverter properly, thus, the predictive mode calculations for the positive
meet the following constraint: and negative dc-link capacitor voltages, which are necessary
ia  ib  ic  0. (23) for the conventional FSS-MPC algorithms, are also eliminated.
TABLE I
CANDIDATE VOLTAGE VECTORS WHEN Vp ≥ Vn
L R L R
Sector Candidate voltage Sector Candidate voltage
Number vectors Number vectors
I-1 V1, V3, V5 II-1 V1, V5, V7
I-2 V3, V5 ,V16 II-2 V5, V7 , V18,
I-3 V5, V16, V17 II-3 V7, V18, V19
I-4 V3, V15, V16 II-4 V5, V17, V18
(a) (b) III-1 V1, V7, V9 IV-1 V1, V9, V11
III-2 V7, V9, V20 IV-2 V9, V11, V22
Fig. 3. Effects of different small voltage vectors on NP voltages. III-3 V9, V20, V21 IV-3 V11, V22, V23
(a) Positive small voltage vector POO. (b) Negative small III-4 V7, V19, V20 IV-4 V9, V21, V22
voltage vector ONN. V-1 V1, V11, V13 VI-1 V1, V3, V13
From (21) to (23), it can be found that the positive small V-2 V11, V13, V24 VI-2 V3, V13, V26
V-3 V13, V24, V25 VI-3 V3, V15, V26
voltage vector and the negative small voltage vector have V-4 V11, V23, V24 VI-4 V13, V25, V26
opposite effect on the NP voltage. Therefore, the NP voltage TABLE II
can be well regulated by setting small voltage vectors properly. CANDIDATE VOLTAGE VECTORS WHEN Vp < Vn
The aforementioned analysis shows that the NP voltage can be Sector Candidate voltage Sector Candidate voltage
Number vectors Number vectors
well regulated by setting action times of small voltage vectors I-1 V1, V4, V6 II-1 V1, V6, V8
properly. Thus, when implementing FSS-MPC algorithms, it is I-2 V4, V6 ,V16 II-2 V6, V8 ,V18,
possible to completely eliminate the item of the NP voltage I-3 V6, V16, V17 II-3 V8, V18, V19
I-4 V4, V15, V16 II-4 V6, V17, V18
balancing in the cost function. Thus, the new cost function III-1 V1, V8, V10 IV-1 V1, V10, V12
without weighting factors at the (k)th instant can be expressed III-2 V8, V10, V20 IV-2 V10, V12, V22
as: III-3 V10, V20, V21 IV-3 V12, V22, V23
III-4 V8, V19, V20 IV-4 V10, V21, V22
g 3 ( k )  u* n ( k )  u n ( k )  u* n ( k )  u  n ( k ) . (24) V-1 V1, V12, V14 VI-1 V1, V4, V14
V-2 V12, V14, V24 VI-2 V4, V14, V26
Fig. 4 illustrates the comparison of the proposed FSS-MPC V-3 V14, V24, V25 VI-3 V4, V15, V26
and the conventional FSS-MPC in terms of the operation V-4 V12, V23, V24 VI-4 V14, V25, V26
principle when the reference voltage vector is located in the
D. Delay time compensation
fourth small sector in the large sector I. According to the
reference voltage vector, the upper dc-link bus voltage and the In the real-time implementation of FSS-MPC algorithm, a
lower dc-link bus voltage, the candidate voltage vectors for the time delay is introduced due to the online calculation. The
proposed FSS-MPC algorithm can be determined. As shown in switching signals for power electronic devices of the inverter
Fig. 4, the number of voltage vectors involved in the cost are generated for the next instant, which represented by the
function optimization can be reduced from 27 to 3. Furthermore, (k+1)th instant and the current voltage vectors adopted at the
according to the location of the reference voltage vector and the (k)th instant needs to be updated. In the proposed FSS-MPC
dc-link bus top and bottom capacitor voltages, the candidate algorithm, a two-step prediction is adopted to compensate the
voltage vectors participating in the cost function optimization delay time [39]. And the cost function (20) of the FSS-MPC
can be determined, as summarized in Table I and Table II for based on desired voltage vector can be updated as:
different conditions. Table I depicts the candidate voltage g 2 com ( k  1)  u* n ( k  1)  u n ( k  1) 
vectors when Vp ≥ Vn and Table II shows the corresponding (25)
results under “Vp < Vn”. u * n ( k  1)  u  n ( k  1)  v 2 ( V p ( k  2)  Vn ( k  2) ).

V0
V26
(a)
Fig. 4. Principle and possible voltage vectors for the two
methods. (a) Conventional FSS-MPC method. (b) Proposed
method.
The above analysis indicates that the proposed FSS-MPC
requires only one calculation for the predictive voltage model
and three evaluations for the cost function, which greatly
simplifies the computational burden. In addition, the proposed
FSS-MPC algorithm eliminates the weighting factor for NP
voltage balance by utilizing the small redundant voltage vectors
Therefore, the cost function (24) of the proposed algorithm
  can be further updated as:
V3 or V4
V15 g 3com ( k  1)  u* n ( k  1)  u n ( k  1)  u * n ( k  1)  u  n ( k  1) .
V16
(26)
E. Implementation Steps
(b) Considering a time delay due to digital implementation, the
complete control of the proposed FSS-MPC algorithm with
delay compensation for T-type three-phase three-level inverters
can be given as: Step 1: Measure three phase currents iɑ(k),
ib(k) , ic(k) and dc-link voltages Vp(k) and Vn(k) at the (k)th
instant. Step 2: Calculate reference currents i*α (k+1) and
i*β(k+1) at the (k+1)th sampling period. Step 3: Apply the
optimal voltage vector determined in the previous control
period and compute Vref (k+1) at the (k+1)th instant. Step 4:

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Determine the location of the reference voltage Vref(k+1). Step Then,

5: Select 3 voltage vectors using the lookup Table I or II L *
according to the location of Vref (k+1) and the relationship of u *xn (k )  u xn (k ) 
ix ( k  1)  ix ( k  1) x  , . (30)
Ts
dc-link top voltages Vp(k) and the dc-link bottom voltage Vn(k).
Step 6: Evaluate the cost functions (26) for the selecting voltage Substituting (30) into (28), it can be expressed as:
vectors. Step 7: Select the voltage vector that has the minimum u*xn (k )  L[i*x (k  1)  ix (k )] Ts  Rix (k ) x   , 

cost function and apply it in the next control cycle. Return to  Ts * *
 g (k )  ( u n (k )  u n (k )  u n (k )  u n (k ) )
step 1. According to above analysis, the control strategy of the  L
fast FSS-MPC without weighting factors is shown in Fig. 5.  Switch(k ) : min  g (k ) , Control Set  Triangle(Vref (k )).

P (31)
ia L R
It can be found that the only difference between two cost
Rdc C
io ib L
functions based on desired voltage vector (27) and current
predictive model (28) is the positive multiplication factor Ts/L.
Edc
C ic L Therefore, the stability characteristics of the two predictive
models are essential the same [40].
N
ia (k ) ib (k ) ic (k )
The discrete Lyapunov function can be defined as [41-45]:
S j (k )
1
L y (I error ( k ))  [I error ( k )]T [I error ( k )] (32)
V p (k ) 2
g 3com (k  1) where Ierror(k) is current error vector and it can be given as
I error ( k )  (ia* (k )  ia (k ))  j (i* (k )  i ( k )). (33)
Vn (k )
g 2 com (k  1) Since there are limited switching states with the FSS-MPC,
the expected voltage vector Vexp(k) can be expressed as:
u* n (k  1) u* n (k  1)
i* ( k  1)
Vexp (k )  Vref (k )  δ(k ) (34)
ia (k ) i* (k )
ib (k ) i ( k  1)
*
where Vexp(k) is the actual generated inverter voltage vector and
ic ( k ) i* (k )
δ(k) is the quantization error vector at the (k)th instant. The
Fig. 5. System control diagram for T-type three-level quantization error vector must satisfy the following expression:
three-phase inverters including both the traditional and δ( k )   with   0. (35)
proposed algorithms.
The change rate of the Lyapunov function for the inverter
F. Stability Analysis can be derived as [41-45]:
The general expression of the proposed FSS-MPC algorithm Ly (I error (k ))  L y (I error (k  1))  Ly (I error (k ))  (1/ 2)[I inv (k )
for T-type three-level three-phase inverters is shown as  (Ts / L)( Vref (k )  δ(k )  RI inv ( k ))  I*inv ( k  1)]T  [I inv (k ) 
follows:
u*xn (k )  L[ix* (k  1)  ix (k )] Ts  Rix (k ) x   ,  (Ts / L)(Vref (k )  δ(k )  RI inv (k ))  I*inv ( k  1)] 
 (1/ 2)[I error (k )]T [I error ( k )]
* *
 g (k )  u n (k )  u n (k )  u n (k )  u n (k )
 (36)
 Switch(k ) : min  g (k ) , Control Set  Triangle(Vref (k )) where I*inv(k) and Iinv(k) are the inverter output current
(27) reference vector and the actual output current vector, and can be
where the Triangle function represents the process of defined as
allocating the candidate vectors within the triangle small  I*inv ( k )  i* (k )  ji* (k )
 (37)
sector shown in Fig. 2. The candidate vectors for each sector
I inv (k )  i (k )  ji (k ).
are summarized in Table I and Table II.
The predictive model and the cost function based on current The solutions of the inverter load current dynamics in (28)
predictive model are given as [40, 42]: are uniformly and ultimately bounded once the continuous
 Ts function Ly(Ierror(k)) satisfies the following conditions [41-45]:
ix (k  1)  L [u x (k )  Rix (k )]  ix (k ) x   ,   L (I (k ))  c I (k ) l , I (k )  G
  y error 1 error error
* * (28)
 g (k )  i (k  1)  i (k  1)  i (k  1)  i (k  1)  l
  Ly (I error (k ))  c2 I error (k ) , I error (k )   (38)
 Switch(k ) : min  g (k ) , Control Set  Triangle(Vref (k )).  l
  Ly (Ierror (k  1))  Ly (I error (k ))  c3 Ierror (k )  c4

According to (12) and (19), the expression can be obtained
where c1, c2, c3 and c4 are positive constants, l ≥ 1, G⊆ Rn is a
as:
control positive invariant set, and Γ⊂ G is a compact set.
 u xn ( k )  L[ix (k  1)  ix ( k )] Ts  Rix (k ) x  ,  Combining (28), the rate of change of the Lyapunov function
 * (29)
*
u xn (k )  L[ix ( k  1)  ix ( k )] Ts  Rix (k ) x  , . can be expressed as:

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1 1 T Case 5: The amplitude of the reference currents is set to 2.5

L y (I error (k ))   [I error ( k )]T [I error ( k )]  ( s ) 2  2 . (39) A and the inverter output current angular frequency is set to
2 2 L
In order to satisfy (38), the constants in (38) can be derived ω*=314.15 rad/s.
as: A. NP Voltage Balancing Performance
 c1  c2  1; c3  1/ 2 The NP voltage ripples by using both algorithms are

 1 2 2
(40) compared. With the conventional FSS-MPC, according to the
c4  2 (Ts / L)  . cost function (20), the weighting factor λv2 is used to balance
Therefore, all signals in the system are uniformly and the NP voltage. Thus, a larger λv2 will result in better NP
ultimately bounded. The rate of change of the Lyapunov voltage balancing performance. However, the inverter output
function in (39) can be derived as: current quality will be deteriorated. A trade-off between the NP
L y (I error ( k ))  2c3 L y (I error ( k ))  c4 . (41) voltage ripple and the output current harmonics is essential in
the practical design. Simulation tests have been carried out to
This inequality implies the current control errors converge to evaluate the performance of NP voltage ripple at different
the compact set when time increases, and the compact set is values of weighting factor λv2. The maximum NP voltage ripple
given as: △VPN is used for the evaluation and its expression can be given
  { I error ( k ) I error ( k ) }  c4 / c3 . (42) as followings:
Therefore, all signals of the FSS-MPC algorithm in (28) are VPN  max( V p  Vn ) (44)
uniformly and ultimately bounded.
where max( ) represents the maximum value for the function.
Fig. 6 shows the obtained THD (total harmonic distortion) of
III. SIMULATION EVALUATION
phase a current and the maximum NP voltage ripple △VPN at
Main parameters for the simulation are listed in Table III and different weighting factors λv2 under case 2. Fig. 6 indicates that
the system control diagram is illustrated in Fig.5. The filter the obtained THD of the phase a current is almost linearly
inductance is set with respect to the inverter output current increased with the weighting factors λv2 for λv2 ≤25. Then, the
ripple and the expression is: THD value shows a sudden increase for λv2 ＞25. Regarding the
Vdc maximum NP voltage ripple △VPN, the value is firstly
L (43)
8 3 f sw iout decreased slowly for λv2 ≤20 and then almost kept constant for
where fsw is the switching frequency of the inverter; ᇞiout is the λv2 ＞20.
allowed current ripple of the inverter and it will be limited to
about 20% of the peak of the rated output current.
TABLE III
SYSTEM PARAMETERS
Parameter Description Values
Edc (V) Dc input voltage 160
Rdc (Ω) Dc input equivalent resistor 0.1
ω* (rad/s) Given Inverter output frequency 314.16
C (μF) Dc-link bus capacitor 500
R (Ω) Loads 20
em (V) Maximum phase grid voltage 60
L (mH) Filter inductance 10
fs (kHz) Sampling frequency 12 Fig. 6. Simulated THD of phase a current and the maximum
Two important design issues, NP voltage balance and NP voltage ripple △VPN at different weighting factors λv2 with
voltage vector selection, are evaluated through simulation. In the conventional FSS-MPC.
order to test the performance of the inverter for different Similarly, in order to evaluate the performance of the
FSS-MPC algorithm, different test conditions are shown as balancing NP voltage with the proposed FSS-MPC, the
followings: maximum NP voltage ripple △VPN at different modulation
Case 1: The amplitude of the reference currents is set to 1.9 indexes is simulated using Matlab/simulink [38]. The
A and the inverter output current angular frequency is set as modulation index m can be defined as:
ω*=314.15 rad/s. m  3Vout Vdc (45)
Case 2: The amplitude of the reference currents is given as where Vout is the amplitude of the reference voltage vector Vref.
3.8 A and the inverter output current angular frequency is given The magnitude of the phase a current reference can be
as ω*=314.15 rad/s. obtained as:
Case 3: The amplitude of reference currents are suddenly
ia*  3mVdc /(3 R2  (2 fL)2 ) (46)
stepped from 1.9 A to 3.8 A, and the inverter output current
angular frequency is set to ω*=314.15 rad/s. where f is the frequency of the output currents.
Case 4: The amplitude of reference currents are suddenly The magnitude of the phase b and phase c current references
changed from 3.8 A to 1.9 A, and the inverter output current is set the same as the phase a. Therefore, the phase a reference
angular frequency is set to ω*=314.15 rad/s. current is given by
ia* (t )  3mVdc cos(*t ) /(3 R 2  (2 fL) 2 ). (47)

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Fig. 7 shows the maximum NP voltage ripple △VPN at the voltage vectors of participating FSS-MPC optimization are
different modulation indexes for the proposed FSS-MPC significantly reduced, the same dynamic performance can be
method under case 2. It shows that the △VPN increases with the achieved with the proposed algorithm.
modulation index. The △VPN is about 2.2 V when the
modulation index m is one, which is only 1.3% of the rated
dc-link voltage. Thus, the proposed FSS-MPC without
weighting factors is effective to balance the NP voltage in the
whole range of modulation index.
 

Fig. 7. Simulated the maximum NP voltage ripple △VPN at (a)

different modulation indexes by using the proposed algorithm.
B. Impact of Selected Voltage Vectors
In order to evaluate the impacts of the selected voltage
vectors on the steady-state process and the dynamic
 
performance, simulation tests were carried out with both the
conventional and the proposed FSS-MPC algorithms. Fig. 8
displays the simulated steady-state waveforms including the
phase a current and selected voltage vectors for two FSS-MPC
algorithms under case 2. It indicates that a similar steady-state
performance can be achieved by using the proposed algorithm.
However, the weighting factors have been removed and the
number of voltage vectors has been reduced from 27 to 3.

(b)
Fig. 9. Simulated dynamic waveforms of phase a current and
selected voltage vectors. (a) Traditional FSS-MPC. (b)
Proposed FSS-MPC.

IV. EXPERIMENTAL EVALUATION

(a)
(b)
Fig. 8. Simulated steady-state waveforms of phase a current and
selected voltage vectors. (a) Traditional FSS-MPC. (b)
Proposed FSS-MPC.
Fig. 9 shows simulated dynamic waveforms, including the
phase a current and selected voltage vectors for two FSS-MPC
algorithms under case 3. It indicates that the same voltage
vectors, V15 and V16, are selected for both two FSS-MPC
algorithms during the process of dynamic test. Therefore,
although the weighting factors are completely eliminated and
In order to verify the feasibility and advantages of the
proposed algorithm, the experimental test was conducted by
using the Texas Instruments 32-bit DSP chip (TMS320F2808).
The inverter output phase currents and the dc-link voltages are
sampled by the internal 12-bit A/D unit of TMS320F2808, and
PWM signals of the inverter are generated by the chip internal
event manager of DSP combined with the complex
programmable logic control device (CPLD) EPM7256. The
programmable DC power supply is used as DC power supply.
The whole experimental setup is depicted in Fig. 10. Main
experimental parameters are given in Table III.
A. Comparison of execution time
The execution time of the proposed FSS-MPC and the
traditional one is compared experimentally. Specifically, an
input/output (I/O) port of DSP is utilized to calculate the
execution time of different FSS-MPC algorithms. The voltage
level of the I/O port becomes high when executing the
FSS-MPC program, and will become low when the algorithm
implementation is finished. The oscillation frequency of Texas

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Instrument TMS320F2808 DSP is set as 100 M. The interrupt
time is set the same as the sampling frequency, which is 83.3 μs.
Fig. 11(a) depicts the execution time for the FSS-MPC based on
desired voltage vector using the cost function (25). Fig. 11(b)
shows the execution time for the proposed FSS-MPC algorithm.
In the process of implementing the algorithm, it takes 12.6 μs to
implement ADC process and other auxiliary tasks. As
displayed in Fig. 11, it can be seen that it totally takes 51.8 μs
(64.4 μs -12.6 μs) for the FSS-MPC and only 24.2 μs (36.8 μs
-12.6 μs) for the proposed FSS-MPC. It shows that the
execution time of the proposed FSS-MPC is only about 46.7%
of the traditional one, which greatly improves the
computational efficiency.
Fig. 10. Experimental setup.
(a)
Fig. 11. Execution time comparison for different FSS-MPC
algorithms. (a) Traditional FSS-MPC. (b) Proposed FSS-MPC.
B. Steady-state experimental evaluation
Since the NP voltage balancing weighting factor of the cost
function (25) affects the performance of NP voltage, here the
weighting factor is tuned to achieve an equivalent NP voltage
oscillation for the steady-state operation. Through the test, the
weighting factor for NP voltage balancing is finally set as
λv2=0.2 for the conventional FSS-MPC. Fig. 12(a) and Fig. 12(c)
show the experimental waveforms of phase a current ia, phase b
current ib, inverter output line voltage uab , negative dc-link bus
voltage Vn and the harmonic spectrum of ia under the case 1
when using the traditional FSS-MPC algorithm. Fig. 12(b) and
Fig. 12(d) illustrate the corresponding experimental waveforms
for the proposed FSS-MPC method under the case 1. The
corresponding results by using different FSS-MPC methods are
illustrated in Fig. 13 under case 2.
From the steady-state experimental waveforms in Fig. 12 and
Fig. 13, it can be seen that both the traditional FSS-MPC and
the proposed fast FSS-MPC without weighting factors can
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achieve tracking the given currents, sinusoidal output currents.
As shown in Fig. 12 and Fig. 13, the oscillation of negative
dc-link bus voltage is small and less than 2 V for both
FSS-MPC algorithms, which illustrates that the proposed
FSS-MPC can effectively balance the NP voltage. The level
number of the output line voltage is 5 for the T-type three-phase
three-level inverter, and it is only 3 for three-phase two-level
inverters. Therefore, the T-type three-level inverter can
improve performances of the inverter compared with two-level
inverters. As displayed in Fig. 12 and Fig. 13, it can be found
that the harmonic spectrum of phase a current is scattered over
different frequency and variable switching frequency for both
FSS-MPC control due to utilizing only a voltage vector per
every control cycle. From Fig. 12 and Fig. 13, it can be obtained
that the total harmonic distortion (THD) of phase a current is
6.62% under case 1 and 4.66% under case 2 for the traditional
FSS-MPC. For the proposed FSS-MPC, the THD of phase a
current is 7.03% under case 1 and 5.01% under case 2.
uab (100V/div) uab (100V/div)
ia , ib (2A/div) Vn (25V/div) ia , ib (2A/div) Vn (25V/div)
t (10ms/div) t (10ms/div)
(a) (b)
(c) (d)
Fig. 12. Steady-state experimental waveforms under case 1. (a)
Waveforms with the conventional FSS-MPC. (b) Waveforms
with the proposed FSS-MPC. (c) Harmonics with the
conventional FSS-MPC. (d) Harmonics with the proposed
FSS-MPC.
uab (100V/div) uab (100V/div)
(b)
Vn (25V/div)
ia , ib (2A/div) Vn (25V/div) ia , ib (2A/div)
t (10ms/div) t (10ms/div)
(a) (b)
(c) (d)
Fig. 13. Steady-state experimental waveforms under case 2. (a)
Waveforms with the conventional FSS-MPC. (b) Waveforms
with the proposed FSS-MPC. (c) Harmonics with the
conventional FSS-MPC. (d) Harmonics with the proposed
FSS-MPC.
From the comparative steady-state experimental waveforms,
it can be seen that the steady-state performance of inverter
output currents for the traditional FSS-MPC is a slightly better
than the proposed FSS-MPC method. The main reason that the
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number of voltage vectors for cost function optimization is 27
for the traditional FSS-MPC and only 3 for the presented
FSS-MPC. As illustrated in Fig. 12 and Fig. 13, it is clearly
seen that the steady-state performance for both FSS-MPC
algorithms is good and very similar. From Fig. 12 (c) and
Fig.12 (d), it can be seen that the THD of phase a current is
larger than 5% with both FSS-MPC algorithms. Compared with
the traditional SVPWM (Space Voltage Pulse Width
Modulation) method, the current ripple of the output currents
and the measured THD are higher by using the FSS-MPC
algorithm. The difference can be explained by the number of
the voltage vector in the control implementation. For the
FSS-MPC algorithm, there is only one voltage vector selected
and applied for every control cycle, while three voltage vectors
nearest to the reference voltage will be selected and applied for
every control cycle by using the traditional SVPWM.
C. Dynamic-state experimental evaluation
To investigate the transient behavior of the proposed strategy,
different conditions for the proposed and classical FSS-MPC
are tested. Fig. 14(a) and Fig. 14(c) display the dynamic
experimental waveforms of inverter output line voltage uab,
negative dc-link bus voltage Vn , phase a load current ia and
phase b load current ib for the conventional FSS-MPC under
case 3 and case 4 conditions, respectively. In addition, Fig. 14(b)
and Fig. 14(d) show the corresponding dynamic experimental
waveforms for the proposed FSS-MPC under the same test
conditions.
uab (100V/div)
Vn (25V/div)
ia ib (2A/div) ia
t (4ms/div)
(a)
uab (100V/div)
Vn (25V/div)
ia ib (2A/div) ia
t (4ms/div)
(c)
Fig. 14. Dynamic experimental waveforms with different
control methods. (a) The traditional FSS-MPC under case 3. (b)
The proposed FSS-MPC under case 3. (c) The traditional
FSS-MPC under case 4. (d) The proposed FSS-MPC under case
4.
It is evident from Fig. 14 that the inverter currents reach the
reference currents with less than 2 ms under given current step
change for both FSS-MPC algorithms, which proves that both
FSS-MPC methods are characterized by good transient
response due to absence of modulation stage for FSS-MPC
method. Furthermore, from the dynamic experimental
waveforms in Fig. 14, it also can be seen that both FSS-MPC
methods have very similar transient response, and the
fluctuation of the NP voltage is small for both FSS-MPC
algorithms even in the dynamic process. From the dynamic
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experimental waveforms of the NP voltage, both FSS-MPC
methods have good balance of the NP voltage.
D. Balancing NP voltage evaluation
In order to further evaluate the performance for balancing NP
voltage, a resistor Rx (80 Ω) is deliberately connected in parallel
with the negative dc-link voltage. Fig. 15(a) presents the
experimental waveforms of phase a current ia and the negative
dc-link bus voltage Vn under case 5 for the classical FSS-MPC.
Fig. 15(b) shows the corresponding experimental results for the
proposed FSS-MPC. As shown in Fig. 15, the balancing of the
NP voltage has been maintained and the oscillation of the NP
voltage is less than 2 V even with the abruptly connecting or
disconnecting the resistor, which illustrates that both FSS-MPC
algorithms can effectively balancing the NP voltage. As
displayed in Fig. 15, the voltage drops are about 3 V and 2.5 V
for the traditional FSS-MPC and the proposed FSS-MPC,
respectively, which demonstrates that the proposed FSS-MPC
has a slight better performance than the traditional FSS-MPC in
balancing the NP voltage when abruptly adding a resistor in the
negative dc-link voltage.
ia (2A/div)
Vn (25V/div)
ia (2A/div)
Vn (25V/div)
t (1s/div) t (1s/div)
(a) (b)
uab (100V/div) Fig. 15. Experimental waveforms of NP voltage balancing with
different FSS-MPC methods under case 5. (a) Traditional
Vn (25V/div) FSS-MPC. (b) Proposed method.
ib (2A/div)
E. Grid-connected Mode Test
For the grid-connected conditions, the predictive model will
t (4ms/div) be changed as:
(b) uan *
( k )  L[ia* (k  1)  ia (k )] Ts  ea (k )
uab (100V/div)
 * *
 ubn ( k )  L[ib (k  1)  ib (k )] Ts  eb (k ) (48)
 * *
 ucn ( k )  L[ic (k  1)  ic ( k )] Ts  ec ( k )
Vn (25V/div)
ib (2A/div) where ei(i=a,b,c)(k) represent grid phase voltage at the (k)th
instant.
The cost function for both the resistive load and the
t (4ms/div) grid-connected conditions is kept the same. Therefore, the
(d) control strategy shown in Fig. 5 can be used for the
grid-connected model. Main experimental parameters are listed
in Table III. With the conventional FSS-MPC, Fig. 16(a) and
Fig. 16(c) illustrate the experimental waveforms, including the
inverter output line voltage uab , inverter output phase current ia,
grid phase a voltage ea, negative dc-link bus voltage Vn and the
harmonic spectrum of ia with unity power factor under the case
2. The space angle θ of grid voltages is acquired by phase
locked loop (PLL). Fig. 16(b) and Fig. 16(d) show the
corresponding experimental waveforms with the proposed
FSS-MPC method under the same condition.
As can be seen in Fig. 16, the steady-state performance of
grid-connected model of the inverter is very similar with that of
the resistive load mode. Both FSS-MPC algorithms have good
steady-state performance and capacity to balance the NP
voltage. However, the THD of phase a current for the proposed
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TII.2018.2815035, IEEE
FSS-MPC method is a little larger than the traditional
FSS-MPC. The THD of phase a current increases from 5.35%
to 5.59% for the proposed FSS-MPC algorithm. The some
conclusion can be obtained with the resistive load mode since
totally 27 candidate voltage vectors are used for the
conventional method while only 3 candidate voltage vectors are
used for the proposed algorithm.
uab (250V/div)
uab (250V/div)
Vn (20V/div)
ea (50V/div) ea (50V/div)
ia (5A/div) ia (5A/div)
t (4ms/div) t (4ms/div)
(a) (b)
(c) (d)
Fig. 16. Experimental waveforms for the grid-connected mode
under case 2. (a) Waveforms with the conventional FSS-MPC.
(b) Waveforms with the proposed FSS-MPC. (c) Harmonics
with the conventional FSS-MPC. (d) Harmonics with the
proposed FSS-MPC.
V. CONCLUSION
In this paper, a fast FSS-MPC without weighting factors for a
T-type three-phase three-level inverter is proposed. A
comprehensive comparison of the proposed FSS-MPC
algorithm with the conventional method has been conducted in
terms of algorithm execution time, harmonics, NP voltage
balancing, and dynamic response. Based above analysis, main
conclusions can be drawn as: (1) Compared with the traditional
FSS-MPC, the number of voltage vectors involved in predictive
model and cost function evaluation is reduced from 27 to 3 by
using the proposed FSS-MPC algorithm, and the execution
time is about 46.7% of the conventional method, which greatly
improves the computational efficiency. (2) The cost function of
the proposed FSS-MPC eliminates weighing factors, which
greatly simplifies the algorithm implementation. (3) Both
FSS-MPC methods have good steady-state performance and
fast dynamic response.
In summary, by maintaining all advantages of the traditional
FSS-MPC algorithms, the proposed method improves
computation efficiency and avoids the tedious adjusting
weighting factors. Therefore, it has a good application
prospects especially for multi-level multi-phase inverters.
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12
Yong Yang (M’15) was born in Hunan, China, in
1981. He received the B.S. degree in automation
from Xiangtan University, Xiangtan, China, in 2003,
the M.S. degree in Electrical Engineering from
Guizhou University, Guiyang, China, in 2006, and
the Ph.D. degree in Electrical Engineering from
Shanghai University, Shanghai, China, in 2010.
He is currently an Assistant Professor with the
School of Rail Transportation, Soochow University.
From December 2017 to December 2018, he is
working as a Visiting Scholar with Center for High Performance Power
Electronics of The Ohio State University, Columbus, USA. His current
research interests include model predictive control in power electronic
converters, distributed energy resource interfacing and high-performance
motor drive control.
Huiqing Wen (M’13) received his B.S. and M.S.
degrees in Electrical Engineering from Zhejiang
University, Hangzhou, China, in 2002 and 2006,
respectively; and his Ph.D. degree in Electrical
Engineering from the Chinese Academy of Sciences,
Beijing, China, in 2009. From 2009 to 2010, he was an
Electrical Engineer working in the Research and
Development Center, GE (China) Co., Ltd., Shanghai,
China. From 2010 to 2011, he was an Engineer at the
China Coal Research Institute, Beijing, China. From
2011 to 2012, he was a Postdoctoral Fellow at the
Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates.
He is presently working as an Associate Professor at the Xi’an
Jiaotong-Liverpool University, Suzhou, China. His current research interests
include bidirectional DC-DC converters, power electronics in flexible AC
transmission applications, electrical vehicles, and high-power, three-level
electrical driving systems.
Mingdi Fan (M’16) was born in Shandong, China, in
1987. He received B.S. and Ph.D. from Northwestern
Polytechnical University, Shaanxi, China, in 2008 and
2014. From 2010 to 2011, he worked as a visiting
scholar in Kassel University, Germany.
He is currently an Assistant Professor with the
School of Rail Transportation, Soochow University.
His current research interests include model
predictive control for power converters and motor
drives.
Menxi Xie was born in Gansu, China, in 1984. He
received the B.S. and M.S. degrees in electrical
engineering from Lanzhou Jiaotong University,
Lanzhou, China, in 2006 and 2009 respectively, and
he received Ph.D. degree in signal and information
processing from Soochow University, Suzhou, China,
in 2018.
Since 2010, he joined the School of Rail
Transportation, Soochow University. His current
research interests include phase-locked loop, power
converter control methods, and motor drives.
Rong Chen was born in Jiangsu, China, in 1983. She
received the B.S. degree in communication
engineering from Soochow University, Suzhou, China,
in 2006, the M.S. degree in communication and
information system from Soochow University in 2009,
and the Ph.D. degree in signal and information
processing from Soochow University in 2013.
Currently, she is a lecturer working in the School of
Rail Transportation, Soochow University. Her
research interests include signal processing and
synchronous phasor measuring.