DGS355 - Lab 06 – Parameterized Counters

DGS355 - Lab 06 – Parameterized Counters

Name: Student ID: Date: Mark: /30 (2%)
Note: This handout is an adaptation of Lab 24 of Dueck, Robert K., Digital Design with CPLD
Applications and VHDL, 2/e for the Online Delivery.

Learning Outcome:
• Create a block diagram file in Quartus 20.1.1.720 that contains a counter from the Altera
Library of Parameterized Modules (LPM).
• Customize the LPM counter to select required ports and parameters of the correct active
level and value.
• Create on LPM counter in VHDL.
• Test the LPM counter on a DE10_lite FPGA test board.

Book Reference:
• Chapter 9: Counters and Shift Registers.

Part 1 - Introduction:
• Altera offers a library of components that can be used in Quartus 20.1.1.720 as part of a VHDL
or graphic design file. These LPM (Library of Parameterized Modules) components can be
easily modified to create designs of any required size. For example, a parameter called
LPM_WIDTH can be set to a given value to make a counter or shift register from 1 to 256
bits wide, subject to the number of logic cells available in a given CPLD.
• A list of LPM components and a summary of their functions are given in the document
lpm.pdf, available on the CD that accompanies Digital Design with CPLD Applications and
VHDL, 2/e, in the folder called Student_Lab_Files. We will examine the use of a
parameterized counter (lpm_counter). A parameterized shift register will be examined in
another lab.
• An LPM module is specified by ports and parameters. A port is an input or output of the
device, with a function such as clock, clear, or load. A parameter is a property of the block,
such as LPM_WIDTH, a parameter that specifies how many bits its parallel input or output
has. Port names are written in lower case; parameter names are in upper case, in the form
LPM_parameter. Some ports and parameters, such as clock and LPM_WIDTH, must be
used in all instances of lpm_counter. Others, such as aclr and LPM_DIRECTION, are
optional.
• Figure 1 shows the symbol for the lpm_counter component with its complete set of ports and
parameters. The function of each port and permissible values of the parameters are listed in
the Help for each component, accessible from the Properties dialog box or the Quartus
20.1.1.720 Help menu. Table 9.13 in Digital Design with CPLD Applications and VHDL 2/e
lists the required ports and parameters for various functions of lpm_counter.

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DGS355 - Lab 06 – Parameterized Counters

• When using an LPM component in a VHDL file, the component requires a library reference
at the beginning of the file:

Figure 1: Available Port and Parameters for an LPM Counter.

Part 2 - Procedure
Step 1: LPM Counter (Block Diagram File)
• Use the Quartus 20.1.1.720 Block Editor to create a 4 bit LPM counter with the ports and
parameters shown in Figure 2. Save the file as ct4lpm.bdf. Compile the project.
• In Quartus 20.1.1.720, LPM counter is find at:
Symbol -> c:/interfpga… -> megafunctions -> arithmetic -> lpm_counter
• Refer to Lab 4 for adding Debouncer for the clock signal and ground all the Unused LEDs.

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DGS355 - Lab 06 – Parameterized Counters

• Create a simulation of the counter that tests all of the functions according to the following
checklist:
a. Tests one full cycle of the count sequence (requires a modified end time)
b. Shows that load is really synchronous
c. Shows the difference between count enable and clock enable functions
d. Tests asynchronous reset
• Bug Fix: In Quartus 20.1.1, in order to run simulation, you must have to fix a simulation bug.
Refer to a separate document named “Quartus 20.1.1 - Bug Fix” to know how to fix this bug.

Step 2: LPM Counter (VHDL)

• Refer to Altera’s LPM Quick Reference or Quartus 20.1.1.720 Help to find the functions of the
following ports and parameters for lpm_counter: updown, sset, LPM_MODULUS,
LPM_DIRECTION,and LPM_SVALUE.
• Write a VHDL file that uses an the smallest possible LPM counter to perform the following
functions:
a. count up or down, depending on the state of an input called direction;
b. synchronously set the counter output value to 2AH (4210) with an active-LOW input
called setn;
c. set the counter modulus to 5010.
• Create a simulation file that demonstrates these functions.

Call the instructor for the demonstration. Instructor Initials: _____________

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 DGS355 - Lab 06 – Parameterized Counters

Step 3: 4-bit LPM Counter (Testing on DE10_lite FPGA test board)

• Project must be successfully complied before testing it on the board.
• Please carefully pull out the shelf to have access to the DE10_lite board and verify if it’s properly
connected to the computer via USB.
• Please refer to the two separate documents named “How to Program DE10 board” and
“DE10_lite - Pin Assignment Table” to know how to download and test the program on the
DE10 board.
• For this lab, please use table 1 to assign the LPM Counter I/O pins to DE10 board.
• Compile the project again.
• Test your project on the DE10_lite board and call the instructor for the demonstration.
Instructor Initials: _____________
Counter I/O Pins DE10 board Pins Description

50 MHz clock input

CLK PIN_P11
(Hardwired)
pn_in PIN_B8 Push-button[0]

Count_EN PIN_B14 Slide Switch[8]

CLK_EN PIN_F15 Slide Switch[9]

RESET PIN_A14 Slide Switch[7]

LOAD PIN_C10 Slide Switch[0]

PIN_C11 Slide Switch[1]

PIN_D12 Slide Switch[2]
p[3..0]
PIN_C12 Slide Switch[3]
PIN_A12 Slide Switch[4]

PIN_A8 LED [0]

PIN_A9 LED [1]
q[3..0]
PIN_A10 LED [2]
PIN_B10 LED [3]

PIN_D13
q[4..9] to Unused LEDs
PIN_B11

Table 1 Pin Assignment

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