Sequential circuits.

Flip-flops
RS latch, D and JK flip-flops
Ing. Michal Lucki, PhD.
Czech Technical University in Prague
Faculty of Electrical Engineering
Department of Telecommunication
RS latch (RS = reset, set)

In the latch’s
normal mode of operation, the
value on -q, is the inverse, or
complement, of the q value.

the RS latch‘s ability to

remember previous input values is
based on feedback
Ing. Michal Lucki, PhD.
D-latch (D = data type) – RS + ENABLE
The combination of two ANDs and NOT
produces three possible combination of
binary values: 00, 01, 10 (00,01,10,11 is
converted to 00,01).

The combination 11 at the output of

two AND gates (being at the input of
the RS part) doesn’t occur and the
unstable state is avoided.

Ing. Michal Lucki, PhD.

D-latch (D = data type) – RS + ENABLE
When ENABLE is placed in its active (logic 1),
and if the data input changes while enable
being 1, the outputs will respond to reflect
the new value.

Ing. Michal Lucki, PhD.

D-latch (D = data type) – RS + ENABLE
When ENABLE returns to its inactive state (0),
any change of data doesn’t have effect on
outputs (Data values are now “don’t care”
values).
The outputs remember their values until the
next activation of ENABLE.

Ing. Michal Lucki, PhD.

D-type flip-flop
Positive edge triggered D-type flip flop -
whenever it’s a rising edge of the clock, data
from D is copied
to Q. Non-Q is complementary to Q. Otherwise,
i.e. during the clock or at its falling edge, data are
not copied and the state value at Q and non-Q
are remembered.

Negative edge triggered D-type flip flop -

whenever it’s a falling edge of the clock, data
from D is copied to Q. Non-Q is
complementary to Q. Otherwise, i.e. during
the clock or at its rising edge, data are not
copied and the state value at Q and non-Q are
remembered.
Ing. Michal Lucki, PhD.
Negative vs. positive edge triggered flip-flop

Ing. Michal Lucki, PhD.

D-type flip-flop in a TTL series

D-type flip-flop pin organization. 7474 in a TTL series of integrated circuits

Ing. Michal Lucki, PhD.

D-type flip-flop with
asynchronous/synchronous clear
Some flip-flops have an additional
input called ~clear, which forces q to
0, irrespective of the value on the data
input. In the asynchronous case, the
effect of ~clear going active is
immediate.

In the synchronous case the

effect of ~clear is
synchronized to the active
edge of the clock.

Ing. Michal Lucki, PhD.

T flip-flop (Toggle)

T: there are no data inputs, the outputs are inversed at each active
edge of the clock input.

Ing. Michal Lucki, PhD.

JK flip-flop
JK: When both the j and k inputs
are 1, an active edge on the
clock causes the outputs to
toggle to the inverse of their
previous values.

Ing. Michal Lucki, PhD.

Transition tables for flip-flops

Note that for a D-type flip-flop, D is identical to Q’ value. It makes the design simpler – to implement any
transition between Q and Q’ values, you must know what binary data at D must be sent to it to trigger such
transition. Practically, you know that D is equal to Q’. So if you want the flip-flop to set a 1, send it a 1 at the D
input, if you want the flip-flop to set a 0, send it a 0 at the D input. This shortcut cannot be used for the
remaining flip-flops, you have to carefully check up with the above tables, what to send in order to achieve the
required updates at the output(s)

Ing. Michal Lucki, PhD.

Thank you for your attention

Ing. Michal Lucki, PhD.