CHAPTER 3

OPERATIONAL AMPLIFIER
(OP-AMP) -
-Ts. Aidawati binti Mustapha-
 Chapter 3 : Operational Amplifier (Op-Amp)

3.1 General Op-Amp circuit design

3.2 Characteristics of ideal Op-Amp
3.3 Components of Differential Amplifier block diagram
3.4 Theory of Op-Amp in electronic circuits
 3.1.1 The general Op-Amp design philosophy
i.The most basic active components in an analog
system.
ii.Very high differential gain, high input impedance,
and low output impedance.
iii.Provide voltage amplitude changes (amplitude
and polarity).
iv.Used oscillators, filter circuits, and many
types of instrumentation circuits.
v.Accumulate a very high gain by multiple stages.
vi.Operational amplifiers are available in IC
packages of either single, dual or quad op-amps
within one single device.
vii.The most commonly available and used of all
operational amplifiers in basic electronic kits and
projects is the industry standard μA-741.
3.1.1 The general Op-Amp design philosophy
( cont.…)

Design of Op-Amp
(Closed Loop / Feedback)
Op Amp IC 741 Pin Configuration
 Op Amp IC 741 Pin Configuration (cont.…)

NUMBER OF PIN FUNCTION

Pin 1 : Offset Null Offset voltage is nulled by application of a voltage of
opposite polarity to the offset.
Pin 2 : Inverted Input All input signals at this pin will be inverted at output pin 6

Pin 3 : Non-Inverted Input All input signals at this pin will be processed normally
without inversion
Pin 4 : -Vcc Supply The negative supply voltage terminal
[-4.5 volts (minimum) to -18 volts (max) ]
Pin 5 : Offset Null See pin 1
Pin 6 : Output Output signal's polarity will be the opposite of the input's
when this signal is applied to the op-amp's inverting input.

Pin 7: + Vcc Supply The positive supply voltage terminal

[+4.5 volts (minimum) to +18 volts (max) ]
Pin 8 : N/C N/C = Not Connected. There is nothing connected to this
pin, it is just there to make it a standard 8-pin package.
3.1.2 Symbol of Op-amp
 Single-Ended Input
+
V o
• + terminal : Source
• – terminal : Ground
~ Vi • 0o phase change


1 input.

+
V o • + terminal : Ground
• – terminal : Source
 • 180o phase change

~
V i
1 input.
Double-Ended Input
V d
+
V o Vd  V  V
~
• Differential input

2 input. • 0o phase shift change
between Vo and Vd
+
V o

~ V1

~
V 2

2 input.
Double-ended Output

• Differential input
•Differential output
3.1.3 The block diagram of an Op-Amp
3.1.3 The block diagram of an Op-Amp
(cont.…)

Internal Block diagram circuit of an Op-amp

3.1.3 The block diagram of an Op-Amp
(cont.…)

Differential • provides low noise amplification

high input impedance, usually a
Amplifier differential output

Gain • pro v i d e s hi g h v o l t a g e g a i n , a
single-pole frequency roll-off,
Stages usually single-ended output.

• provides high current driving capability,

Output Stage low output impedance, current limiting
and short circuit protection circuitry
 3.1.3 The block diagram of an Op-Amp
(cont.…)

(i) Input stage: Differential Amplifier

Ø The input stage is a differential
amplifier.
Ø The differential amplifier used as an
input stage provides differential
inputs and a frequency response
down to d.c.
Ø Special techniques are used to
provide the high input impedance
n e c e s s a r y fo r t h e o p e rat i o n a l
amplifier.
 3.1.3 The block diagram of an Op-Amp
(cont.…)

(ii) Gain (Second) Stage: Gain Amplifier

Ø The second stage is a high-gain
voltage amplifier.
Ø This stage may be made from several
transistors to provide high gain.
Ø A typical operational amplifier could
have a voltage gain of 200,000.
Ø Most of this gain comes from the
voltage amplifier stage.
 3.1.3 The block diagram of an Op-Amp
(cont.…)

(iii) Output amplifier stage:

Push pull Amplifier
Ø The output stage (a class B amplifier)
provides high current.
Ø The output amplifier provides low output
impedance.
Ø The actual circuit used could be an
emitter follower.
Ø The output stage should allow t h e
operational amplifier to deliver several
mA to a load. Notice that the operational
amplifier has a positive power supply (+V
CC) and a negative power supply (-V EE).
Dynamic Parameters:
(1) Open-Loop Voltage Gain (Aol)
The output to input voltage ratio of the op-amp without external
feedback.

1. Gain--infinite
2. Input impedance--infinite
3. Output impedance--zero
4. Bandwidth--infinite
5. Voltage out--zero (when voltages into each other are equal)
6. Current entering the amp at either terminal--extremely small
(2) Large-Signal Voltage Gain
This is the ratio of the maximum voltage swing to the
charge in the input voltage required to drive the output
from zero to a specified voltage (e.g. 10 volts).

(3) Slew Rate (SR)

The time rate of change of the output voltage with the op-
amp circuit having a voltage gain of unity (1.0).
Characteristics of Op-Amp
(1) Infinite Open Loop gain (voltage)
- The gain without feedback V1
- Equal to differential gain
+
Vo
- Zero common-mode gain V2 
- Pratically, Gd = 20,000 to 200,000

(2) Infinite Input impedance

i1~0 +
- Input current ii ~0A
Vo
T- in high-grade op-amp
-
i2~0 
- m-A input current in low-grade op-amp
Characteristics of Op-Amp
(3) Zero Output Impedance
- act as perfect internal voltage source
- No internal resistance
- Output impedance in series with load
- Reducing output voltage to the load
- Practically, Rout ~ 20-100  Rout
Vo' +
Rload

R load
V load  V o
R load  R out
Characteristics of Op-Amp
(4) Zero Input offset voltage (Voi)
-This is the voltage that must be applied to one of the input pins to give a
zero output voltage. Remember, for an ideal op-amp, output offset
voltage is zero.

(5) Input Offset Current (Ios)

-This is the difference of the two input bias currents when the output
voltage is zero.

(6) Infinity Bandwidth

Ideal vs. Practical Op-Amp
Ideal op-amp Practical op-amp
+ AVin +
Zin Zout
Vin ~ Vout Vin Vout
~
 Zout=0  AVin
Ideal vs. Practical Op-Amp
Ideal Practical

Open Loop gain A  105

Bandwidth BW  10-100Hz
Input Impedance Zin  >1M
Output Impedance Zout 0 10-100 
Output Voltage Vout Depends only on Vd = Depends slightly on
(V+V) average input Vc =
Differential mode (V++V)/2 Common-
signal Mode signal

CMRR  10-100dB
 3.2 DIFFERENTIAL AMPLIFIER
Circuit Construction
ØHave two inputs marked V1 and V2.
ØThe two identical transistors TR 1
and TR2 are both biased at the same
operating point with their emitters
connected together and returned to
the common rail, -V e e by way of
resistor Re.
Circuit Operation
From a dual supply +V cc and -V ee which ensures a constant
supply. The voltage that appears at the output, V out of the
amplifier is the difference between the two input signals as
the two base inputs are in anti-phase with each other. So as
the forward bias of transistor, TR 1 is increased, the forward
bias of transistor TR2 is reduced and vice versa. Then if the two
transistors are perfectly matched, the current flowing through
the common emitter resistor, Re will remain constant.
 Differential Amplifier
Input bias current
Since the DC of each transistor in the first stage is slightly different, the base currents in the
differential amplifier above are slightly different. The input bias current is defined as the average
of the DC base currents:

I B1  I B 2
I IN ( base ) 
2
The bias current is typical in nano-amperes (BJT) or pico-amperes (FET) and will flows through
the resistances between the bases and ground. These resistances may be discrete resistances or
they may be the Thevenin resistances of the input sources.
 Differential Amplifier
Input offset current
The input offset current is defined as the difference of the DC base currents:

I in( off )  I B 2  I B1
Ø This difference in the base currents indicates how closely the transistors TR1 and TR2 are
matched.

Ø If the transistors are identical, the input offset current is zero because both base currents will be equal,
but almost always, the two transistors are slightly different and the two base currents are not equal.

Ø The base currents can cause output voltage error in precision applications. A compensate
resistor may be use to eliminate the effect of the input offset current as shown in the following figure:-
 Differential Amplifier
Input offset Voltage
More errors caused by the imperfect match of the differential amplifier stage
are collector resistances (RC1 RC2) and base-emitter voltages (VBE1VBE2)
as shown in figure below (Figure 3.5 DC error Inputs) :
 Differential Amplifier
The input offset voltage is defined as the input voltage that would produce the same output error
voltage in a perfect differential amplifier.

V
V  error
in( off ) A
Total error : V  V  V
in 1 2
V  A( V  V )
out 1 2

DC error inputs :
V (R R )I
1err B1 B 2 in( bias )
V  1 (( R  R )I )
2err 2 B1 B 2 in( off )
V V
3err  in( off )
V  A( V V V )
err 1err 2err 3err
 Differential Amplifier
Common Mode Operation +
Same voltage source is applied at V o
both terminals 
I d e a l l y, t wo i n p u t a re e q u a l l y
amplified
Vi ~

Output voltage is ideally zero due to

differential voltage is zero
Practically, a small output signal can
still be measured
Note for differential circuits:
Opposite inputs - highly amplified
Common inputs - slightly amplified
 Common-Mode Rejection
Differential Amplifier
Common Mode Gain
Ø This is known as the Common Mode of Operation with the common mode gain of the
amplifier being the output gain when the input is zero.

Ø Its simply the ratio of the differential gain Av over the common-mode gain Acm.

Differential Gain Common-Mode Gain

Av = Vo / (v+ - v-) Acm = Vo / Vcm

This is your basic open- Here's the gain with the inputs
loop gain of an op amp. tied together at Vcm = v+ = v-.
 Common Mode Rejection Ratio (CMRR)
I think about common-mode rejection (CMRR) often, even
outside of work!

I am an avid college football fan and when watching games

on Saturday at my house I am often interrupted by the
common noise of my wife or daughter asking me to do
various other things such as chores.

I use my ability to reject this noise and only focus on the

signal that matters…the game.

How much of their signal comes through and interrupts the

game is analogous to amplifiers CMRR.
 Differential Amplifier
Common Mode Rejection Ratio (CMRR)
Ideal Operational Amplifiers, if an identical signal is applied to both the inverting
and non-inverting inputs there should no change to the output.

However, in real amplifiers there is always some variation and the ratio of the
change to the output voltage with regards to the change in the common mode
input voltage is called the Common Mode Rejection Ratio or CMRR.

The CMRR is a measure of how well the device rejects a common-mode signal.
 Differential Amplifier
Common Mode Rejection Ratio (CMRR)
Substituting the gains above into CMRR will get us

Rearrange it a little and we get

Past Year Structure Question

Referring to figure above, define Common Mode Rejection Ratio (CMRR).

Then calculate the CMRR and express it in Decibel (dB). Its common gain
is 0.001. Rf

1000k

R1
-
15k
OUT Vout
0 V1 = 2.5 Vpp +
Gain Amplifier
Ø Use npn and pnp BJT.

Ø Having both polarities of transistors allows for more kinds of amplifiers

and makes biasing easier.

Ø For example, a complementary cascade amplifier is shown below. The

second (CE) stage uses a pnp BJT. In a representation similar to the power-
supply voltage sources, the input voltage source is implicit by the vi label at
the input node. Also, the + terminal of vo is labeled by "vo" and is
understood to be taken with respect to ground (as the - terminal).
Gain Amplifier
 Its gain equation is the same as the all-npn cascade.

 The advantage of the complementary cascade amplifier is that the CB-stage collector
supply (ground) must be at a lower voltage than that of the base, allowing a ground-
referenced output.

 For the all-npn cascade, +VCC adds to the output voltage developed across RL instead.

 Many other amplifiers of two or more transistor stages can perform better than the
three one-transistor configurations.
Push Pull Amplifier
• During the positive half-cycle of the AC input,
transistor Q1 (npn) is conducting and Q2 (pnp) is off.

 During the negative half-cycle of the AC input,

transistor Q2 (pnp) is conducting and Q1 (npn) is off.

• Each transistor produces one-half of an AC cycle. The

transformer combines the two outputs to form a full
AC cycle.