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L14 2 f09
L14 2 f09
Administrative issues
Midterm exam postponed to Thurs. Nov. 5th o You can only bring one 8x11 paper with your own written notes (please do not photocopy) o No books, class or any other kind of handouts/notes, calculators, computers, PDA, cell phones.... o Midterm includes material covered to end of lecture 14
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 1
EE247 Lecture 14
D/A converters
D/A converters: Various Architectures (continued)
Charge scaling DACs (continued) R-2R type DACs Current based DACs
Practical aspects of current-switched DACs Segmented current-switched DACs DAC dynamic non-idealities DAC design considerations
Data Converters- DAC Design 2009 Page 2
+
4C
b5 Vref
Vout
Cse rie s =
Split array reduce the total area of the capacitors required for high resolution DACs E.g. 10bit regular binary array requires 1024 unit Cs while split array (5&5) needs 64 unit Cs Issue: Sensitive to parasitic capacitor
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 4
Disadvantages:
Process needs to include good capacitive material with standard digital process Requires large capacitor ratios Not inherently monotonic (more later)
EECS 247 Lecture 14: Data Converters- DAC Design
not compatible
2009 Page 5
Segmented DAC
reset 32 C b5 16C b4 8C b3 4C b2 2C b1 C b0 C
Vout
. . . . . . . . . .
2R
2R R R
VEE
VEE
2R R
2R R
2R
2R
2009 Page 9
I3 VB
Q3
I2
Q2 2Aunit 4Aunit
I1
Q1 Aunit
IT
QT Aunit
I3 VB
Q3 4Aunit
I2
Q2 2Aunit
I1+IT
2Aunit
VEE
2R R
2R R
2R
2R
VEE
2R R
2R R
2009 Page 10
I3 VB
Q3
I2
4Aunit
I1+IT
Q2 2Aunit 2Aunit
I3 VB
Q3 4Aunit
I2+I1+IT
Q2 4Aunit
VEE
2R R
2R R
VEE
2R R
I I I I3 = I2 + I1 + IT I3 = T ot al , I2 = T ot a l , I1 = To t al 2 4 8
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 11
Iout VB
4Aunit 2Aunit Aunit
Aunit
4I VEE
2R 2I R
2R R
I 2I
2R I
2R
4I
Vout
VB 16I VEE
2R 8I R 2R 2I R 2R R
2R 4I R
I 2I
2R I
2R
16I
8I
4I
Trans-resistance amplifier added to: - Convert current to voltage - Generate virtual ground @ current summing node so that output impedance of current sources do not cause error - Issue: error due to opamp offset
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 13
R RTotal -
Vos
Vout
Offset Model
G i ves r i s e t o I N L & DN L
2009 Page 14
Disadvantages:
Total device emitter area
Not practical for high resolution DACs
AEunitx 2B
Iout
Iref
Iref
Iref
Iref
Iref
Unit elements or thermometer 2B-1 current sources & switches Suited for both MOS and BJT technologies Monotonicity does not depend on element matching and is guaranteed Output resistance of current source gain error Cascode type current sources higher output resistance less gain error
Data Converters- DAC Design 2009 Page 16
+
Vout
Iref
Iref
Iref
Iref
- Current source output held @ virtual ground - Error due to current source output resistance eliminated - New issues: offset & speed of the amplifier
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 17
2B-1 Iref
4 Iref
2Iref
Iref
Binary weighted B current sources & switches (2B-1 unit current sources but less # of switches) Monotonicity depends on element matching not guaranteed
2009 Page 18
Random variations
Lithography etc Often Gaussian distribution (central limit theorem)
*Ref: C. Conroy et al, Statistical Design Techniques for D/A Converters, JSSC Aug. 1989, pp. 1118-28.
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 19
Iref
Iref
Iref
Iref -I Iref +I
Iref
Iref
Simplified example:
3-bit DAC Assume only two of the current sources mismatched (# 4 & #5)
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 20
7 Iref R 6 5 4 3 2
DN L[ 4 ] = I / I [ LSB ] DN L[ 5] = ( I + I )R IR IR
DN L[ 5 ] = I / I [ L S B ] IN Lmax = I / I [ L S B ]
1xIref R
0
Digital Input
*
pdf [f(x1,x2)] pdf [f(x3,x4)] pdf [f(xm,xn)] Gaussian pdf
*
EECS 247 Lecture 14:
....
*
2009 Page 22
Gaussian Distribution
Probability density p(x)
0.4 0.3
0.2
p( x ) =
1 e 2
x ) 2 2
0.1 0
-3
-2
-1
2 variance
EECS 247 Lecture 14:
(x-) /
2009 Page 23
Yield
Probability density p(x)
In most cases we are interested in finding the percentage of components (e.g. R) falling within certain bounds:
P ( X x + X ) = = 1 2
+X X x2
P(-X x +X)
2 dx
X/
2009 Page 24
Yield
X/ 0.2000 0.4000 0.6000 0.8000 1.0000 1.2000 1.4000 1.6000 1.8000 2.0000
EECS 247 Lecture 14:
P(-X x X) [%] 15.8519 31.0843 45.1494 57.6289 68.2689 76.9861 83.8487 89.0401 92.8139 95.4500
X/ 2.2000 2.4000 2.6000 2.8000 3.0000 3.2000 3.4000 3.6000 3.8000 4.0000
P(-X x X) [%] 97.2193 98.3605 99.0678 99.4890 99.7300 99.8626 99.9326 99.9682 99.9855 99.9937
2009 Page 25
Example
Measurements show that the offset voltage of a batch of operational amplifiers follows a Gaussian distribution with = 2mV and = 0. Find the fraction of opamps with |Vos| < 6mV:
X/ = 3 99.73 % yield
2009 Page 26
Component Mismatch
Example: Resistors layouted out side-by-side
400
No. of resistors
300
R
200
100 0 988
After fabrication large # of devices measured & graphed typically if sample size large shape is Gaussian
992
996
1000
1004
1008 1012 R[ ]
E.g. Let us assume in this example 1000 Rs measured & 68.5% fall within +-4OHM or +-0.4% of average 1 for resistors 0.4%
2009 Page 27
Component Mismatch
Probability density p(x) Example: Two resistors layouted out side-by-side
0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0
R=
R1 + R2 2
dR = R1 R2
3 2
3
R
dR
2 dR R
1 Are a
For typical technologies & geometries 0.02 to 5% 1 for resistors In the case of resistors is a function of area
Data Converters- DAC Design
2009 Page 28
Vref
w h ere Rmedian =
Ri o
2B
Iref
i = Ri I ref
= dR R
median
dR Ri
median
DNL = dRi
Ri
To first order DNL of unit element DAC is independent of resolution! Note: Similar results for other unit-element based DACs
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 29
D NL = dR
Ri
Example: If dR/R = 0.4%, what DNL spec goes into the DAC datasheet so that 99.9% of all converters meet the spec?
2009 Page 30
Yield
X/ 0.2000 0.4000 0.6000 0.8000 1.0000 1.2000 1.4000 1.6000 1.8000 2.0000
EECS 247 Lecture 14:
P(-X x X) [%] 15.8519 31.0843 45.1494 57.6289 68.2689 76.9861 83.8487 89.0401 92.8139 95.4500
X/ 2.2000 2.4000 2.6000 2.8000 3.0000 3.2000 3.4000 3.6000 3.8000 4.0000
P(-X x X) [%] 97.2193 98.3605 99.0678 99.4890 99.7300 99.8626 99.9326 99.9682 99.9855 99.9937
2009 Page 31
D NL = dR
Ri
Example: If dR/R = 0.4%, what DNL spec goes into the datasheet so that 99.9% of all converters meet the spec? Answer: From table: for 99.9% X/ = 3.3 DNL = dR/R = 0.4% 3.3 DNL = 3.3x0.4%=1.3% DNL= +/- 0.013 LSB
2009 Page 32
A=n+E
B E A
Ideal n N-n
Variance n.2
B=N-n-E
(N-n).2
n
Input [LSB]
N=2B-1
E = A-n r =n/N N=A+B = A-r(A+B) = (1-r). A - r.B Variance of E: 2 =(1-r)2 . 2 + r 2 . 2 E B =N.r .(1-r).2 = n .(1- n/N).2
2009 Page 33
DAC INL
E2 = n 1
n 2 N N 4
INL/
(2B-1)0.5/2
T o f i n d ma x. var i a nce : n = N / 2 E2 = 2
d E 2 dn
=0
n/N
0.5
INL depends on both DAC resolution & element matching While DNL = is to first order independent of DAC resolution and is only a function of element matching
Ref: Kuboki et al, TCAS, 6/1982
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 34
INL
1 B 2 1 2
INL
B 2 + 2log 2
= 1% Bmax = 8.6bits = 0.5% Bmax = 10.6bits = 0.2% Bmax = 13.3bits = 0.1% Bmax = 15.3bits
Note: In most cases, a number of systematic errors prevents achievement of above results
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 35
Simulation Example
12 Bit converter DNL and INL
2
DNL [LSB]
1 0 -1 2
500
1000
bin
INL LSB]
1 0 -1
Computed INL: INLmax = 0.32 LSB (midscale) Why is the results not as expected per our derivation?
2009 Page 36
500
1000
bin
EECS 247 Lecture 14: Data Converters- DAC Design
2B-1 Iref
4 Iref
2Iref
Iref
I8 8Iref
I4 4Iref
I2
I1 Iref
6 5 4
2Iref
3 2
1
0
DNL2/ 2
14 244 1424 4 3 3
10
0111...
1000...
2 2B
DNLma x = 2B / 2 INLmax
2 4 6 8 10 12 14
1 2 2B 1
1 2
DNLmax
Example:
0 B = 12, = 1% DAC Output [LSB]
Id1
Id2
Iref
dId Id = dW L
W L
Switch Array
64 ....1
Example: 8bit Binary Weighted Advantages: Can be very fast Reasonable area for resolution < 9-10bits
DN L =
1 IN L 2 2 B
S = 2B
S=B
DN L = IN L 2
B 2
DN L 2 = 3 2
B 2
= 1 6
INL 2
= 16
S = 2B = 1 0 24
S = B = 10
2009 Page 44
Note: =2%
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 45
10Bit DAC DNL/INL Comparison Plots: RMS for 100 Simulation Runs
Ref: C. Lin and K. Bult, "A 10-b, 500MSample/s CMOS DAC in 0.6 mm2," IEEE Journal of Solid-State Circuits, vol. 33, pp. 1948 - 1958, December 1998.
Note: =2%
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 46
VAnalog
BTotal = B1+B2
INL: unaffected same as either architecture DNL: Worst case occurs when LSB DAC turns off and one more MSB DAC element turns on Same as binary weighted DAC with (B2+1) # of bits Number of switched elements: (2B1-1) + B2
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 48
Comparison
Example: B = 12, B1 = 5, B1 = 6,
MSB
B2 = 7 B2 = 6
LSB
DNL 2 I NL 2
( B2 +1)
= 2 I NL
Assuming: = 1%
S = 2B1 1 + B2
INL[LSB] 0.32 0.32 0.32 0.32 DNL[LSB] 0.01 0.113 0.16 0.64 # of switched elements 4095 63+6=69 31+7=38 12
2009 Page 49
DAC Architecture (B1+B2) Unit element (12+0) Segmented (6+6) Segmented (5+7) Binary weighted(0+12)
EECS 247 Lecture 14:
N to (2N-1) decoder
2009 Page 51
2009 Page 52
Register
Latched NAND gate: CTRL=1 OUT=INB
EECS 247 Lecture 14:
IN
Register
2009 Page 53
+ -
Iref =(VDD-Vref ) / R
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 54
+ -
LSB
MSB
2009 Page 56
Ideal
5 0 1 1.5 2 2.5 3
Early
10 5 0
Late
10 5 0
1.5
2.5
1.5
Time
2.5
2009 Page 58
Glitch Energy
Glitch energy (worst case) proportional to: dt x 2B-1 dt error in timing & 2B-1 associated with half of the switches changing state LSB energy proportional to: T=1/fs Need dt x 2B-1 << T or dt << 2-B+1 T Examples:
fs [MHz]
1 20 1000
B 12 16 12
dt [ps]
<< 488 << 1.5 << 0.5
Timing accuracy for data converters much more critical compared to digital circuitry
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 59
To minimize control and clock feed through to the output via G-D & G-S of the switches
Use of low-swing digital circuitry
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 60
Current copiers:
D. W. J. Groeneveld et al, A Self-Calibration Technique for Monolithic High-Resolution D/A Converters, JSSC December 1989, pp. 1517
8x8 array
2009 Page 62
Two sources of systematic error: - Finite current source output resistance - Voltage drop due to finite ground bus resistance
2009 Page 63
VGSM 2 = VGSM 1 4RI VGSM 3 = VGSM 1 7RI VGSM 4 = VGSM 1 9RI VGSM 5 = VGSM 1 10RI I2 = k (VGSM 2 Vth )
2 2
Iout
VDD VG
M1
I1
M2
I2
M3
I3
M4
I4 M5 I5
Rx4I
Rx3I
Rx2I
RxI
Iout VDD
M1
I1
M2
I2
M3
I3
M4
I4 M5 I5
Rx4I
Rx3I
Rx2I
RxI
INL [LSB]
Input
Example: 7 unit element current source DAC- assume gmR=1/100 If switching of current sources arranged sequentially (1-2-3-4-5-6-7) INL= +0.25LSB If switching of current sources symmetrical (4-3-5-2-6-1-7 ) INL = +0.09, -0.058LSB INL reduced by a factor of 2.6
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 66
Input
Example: 7 unit element current source DAC- assume gmR=1/100 If switching of current sources arranged sequentially (1-2-3-4-5-6-7) DNLmax= + 0.15LSB If switching of current sources symmetrical (4-3-5-2-6-1-7 )
DNLmax = + 0.15LSB
EECS 247 Lecture 14:
DNLmax unchanged
2009 Page 67
Two sources of systematic error: - Finite current source output resistance - Voltage drop due to finite ground bus resistance
2009 Page 68