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DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

EC6009 - ADVANCED COMPUTER ARCHITECTURE

UNIT- III

PART-A
1. Define VLIW.
A style of instruction set architecture that launches many operations that are
defined to be independent in a single wide instruction.

2. What is called reservation stations?

A buffer within a functional unit that holds the operands and the operation. 15.
Give the major limitation of pipelining technique. If an instruction is stalled in the
pipeline, no later instructions can proceed. Thus, if there is a dependency
between two closely spaced instructions in the pipeline, it will stall.

3. How will you split ID pipe to introduce out-of-order execution?

Issue - Decode instructions, check for structural hazards; Read operands - Wait
until no data hazards, then read operands.

4. What you meant by register renaming?

As instructions are issued, the register specifiers for pending operands are
renamed to the names of the reservation station in a process called register
renaming. This combination of issue logic and reservation stations provides
renaming and eliminates WAW and WAR hazards.

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5. Consider a nonpipelined machine with 6 execution stages of lengths 50 ns, 50 ns,

60 ns, 60 ns, 50 ns, and 50 ns. - Find the instruction latency on this machine. -
How much time does it take to execute 100 instructions? Instruction latency =
50+50+60+60+50+50= 320 ns Time to execute 100 instructions = 100*320 =
32000 ns 19. What is Flynn’s Classification? In 1966, Michael Flynn proposed a
classification for computer architectures based on the number of instruction
steams and data streams (Flynn‘s Taxonomy). Flynn uses the stream concept for
describing a machine's structure A stream simply means a sequence of items
(data or instructions). The classification of computer architectures based on the
number of instruction steams and data streams (Flynn‘s Taxonomy).

6. Give the Flynn’s Classification Of Computer Architectures.

Flynn‘s Taxonomy
SISD: Single instruction single data -Classical von Neumann architecture
SIMD: Single instruction multiple data
MISD: Multiple instructions single data - Non existent, just listed for
completeness
MIMD: Multiple instructions multiple data Most common and general parallel
machine

7. Describe about SIMD.

SIMD (Single-Instruction stream, Multiple-Data streams) Each instruction is
executed on a different set of data by different processors i.e multiple processing
units of the same type process on multiple-data streams. This group is dedicated
to array processing machines. Sometimes, vector processors can also be seen as
a part of this group.

8. Describe In-Order Issue with Out-of-Order Completion

With out-of-order completion, a later instruction may complete before a
previous instruction Out-of-order completion is used in single-issue pipelined
processors to improve the performance of long-latency operations such as divide

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When using out-of-order completion instruction issue is stalled when there is a

resource conflict (e.g., for a functional unit) or when the instructions ready to
issue need a result that has not yet been computed.

9. Define – Issue Slots and Issue Packet

Issue slots are the positions from which instructions could be issued in a given
clock cycle. By analogy, these correspond to positions at the starting blocks for a
sprint.
Issue packet is the set of instructions that issues together in one clock cycle; the
packet may be determined statically by the compiler or dynamically by the
processor.

10. Define – VLIW

Very Long Instruction Word (VLIW) is a style of instruction set architecture that
launches many operations that are defined to be independent in a single wide
instruction, typically with many separate opcode fields.

11. Define – Superscalar Processor

Superscalar is an advanced pipelining technique that enables the processor to
execute more than one instruction per clock cycle by selecting them during
execution. Dynamic multipleissue processors are also known as superscalar
processors, or simply superscalars.

12. What is meant by loop unrolling?

An important compiler technique to get more performance from loops is loop
unrolling, where multiple copies of the loop body are made. After unrolling,
there is more ILP available by overlapping instructions from different iterations.

13. What is meant by anti-dependence? How is it removed?

Anti-dependence is an ordering forced by the reuse of a name, typically a
register, rather than by a true dependence that carries a value between two
instructions. It is also called as name dependence. Register renaming is the

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technique used to remove anti-dependence in which the registers are renamed

by the compiler or hardware.

14. What is the use of reservation station and reorder buffer?

Reservation station is a buffer within a functional unit that holds the operands
and the operation. Reorder buffer is the buffer that holds results in a dynamically
scheduled processor until it is safe to store the results to memory or a register.

15. Differentiate in-order execution from out-of-order execution.

Out-of-order execution is a situation in pipelined execution when an instruction
is blocked from executing does not cause the following instructions to wait. It
preserves the data flow order of the program. In-order execution requires the
instruction fetch and decode unit to issue instructions in order, which allows
dependences to be tracked, and requires the commit unit to write results to
registers and memory in program fetch order. This conservative mode is called
in-order commit.

16. What is meant by hardware multithreading?

Hardware multithreading allows multiple threads to share the functional units of
a single processor in an overlapping fashion to try to utilize the hardware
resources efficiently. To permit this sharing, the processor must duplicate the
independent state of each thread. It Increases the utilization of a processor.

17. What are the two main approaches to hardware multithreading?

There are two main approaches to hardware multithreading. Fine-grained
multithreading switches between threads on each instruction, resulting in
interleaved execution of multiple threads. This interleaving is often done in a
round-robin fashion, skipping any threads that are stalled at that clock cycle.
Coarse-grained multithreading is an alternative to fine-grained multithreading. It
switches threads only on costly stalls, such as last-level cache misses.

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PART – B
1. Discuss the need for parallelization multimedia and explain the architecture of
GPU with neat diagrams.
2. Explain data level parallelism in vector architecture.
3. Describe loop level parallelism.
4. Describe about vector architecture in detail.
5. Explain about detecting and enhancing loop level parallelism
6. Explain about SIMD instruction set extension for multimedia.

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