Mux 2x1

module mux2x1(d, sel,y);

input [1:0]d;
input sel;
output y;
wire sbar, w1, w2, y;
not G1 (sbar, sel);
and G2 (w1, d[0], sbar);
and G3 (w2, d[1], sel);
or G4 (y, w1, w2);
endmodule

test Bench
module mux2x1test;
reg [1:0] d;
reg sel;
wire y;
mux2x1 mux(d, sel,y);
initial
begin
d=2'b00; sel=0;
#50 d=2'b01; sel=0;
#50 d=2'b10; sel=0;
#50 d=2'b11; sel=0;

#50 d=2'b00; sel=1;

#50 d=2'b01; sel=1;
#50 d=2'b10; sel=1;
#50 d=2'b11; sel=1;

#100 $stop;
end

endmodule

Mux 8x1

module mux8x1(d, sel,y);

input [7:0]d;
input [2:0]sel;
output y;
wire [2:0]sbar;
wire[7:0] w;
not ng1 (sbar[0], sel[0]);
not ng2 (sbar[1], sel[1]);
not ng3(sbar[2], sel[2]);

and ag1 (w[0], d[0], sbar[2],sbar[1],sbar[0]);

and ag2 (w[1], d[1], sbar[2],sbar[1],sel[0]);
and ag3 (w[2], d[2], sbar[2],sel[1],sbar[0]);
and ag4 (w[3], d[3], sbar[2],sel[1],sel[0]);
and ag5 (w[4], d[4], sel[2],sbar[1],sbar[0]);
and ag6 (w[5], d[5], sel[2],sbar[1],sel[0]);
and ag7 (w[6], d[6], sel[2],sel[1],sbar[0]);
 and ag8 (w[7], d[7], sel[2],sel[1],sel[0]);

or G4 (y, w[0],w[1], w[2],w[3],w[4],w[5],w[6],w[7]);

endmodule

test Bench
m
module mux8x1test;
reg [7:0] d;
reg [2:0]sel;
wire y;
mux8x1 mux8x1(d, sel,y);
initial
begin
#30 d=7'b00000001; sel=3'b000;
#30 d=7'b00000010; sel=3'b001;
#30 d=7'b00000100; sel=3'b010;
#30 d=7'b00001000; sel=3'b011;
#30 d=7'b00010000; sel=3'b100;
#30 d=7'b00100001; sel=3'b101;
#30 d=7'b01000000; sel=3'b110;
#30 d=7'b10000000; sel=3'b111;
#100 $stop;
end

endmodule

Mux 16x1

module mux16x1using2x1(d,sel,y);
input [15:0]d;
input [3:0]sel;
output y;
wire [7:0]m17;
wire[3:0]m23;
wire [1:0]m31;
mux2x1 m1(d[1:0],sel[0],m17[0]);
mux2x1 m2(d[3:2],sel[0],m17[1]);
mux2x1 m3(d[5:4],sel[0],m17[2]);
mux2x1 m4(d[7:6],sel[0],m17[3]);
mux2x1 m5(d[9:8],sel[0],m17[4]);
mux2x1 m6(d[11:10],sel[0],m17[5]);
mux2x1 m7(d[13:12],sel[0],m17[6]);
mux2x1 m8(d[15:14],sel[0],m17[7]);
mux2x1 m9(m17[1:0],sel[1],m23[0]);
mux2x1 m10(m17[3:2],sel[1],m23[1]);
mux2x1 m11(m17[5:4],sel[1],m23[2]);
mux2x1 m12(m17[7:6],sel[1],m23[3]);
mux2x1 m13(m23[1:0],sel[2],m31[0]);
mux2x1 m14(m23[3:2],sel[2],m31[1]);

mux2x1 m15(m31[1:0],sel[3],y);
endmodule

Test bench

module mux16x1using2x1test;
reg [0:15] d;
reg [0:3] sel;
wire y;

mux16x1using2x1 m16x1(d,sel,y);

initial

begin

#30 d=16'b0000000000000001; sel=4'b0000;

#30 d=16'b0000000000000010; sel=4'b0001;
#30 d=16'b0000000000000100; sel=4'b0010;
#30 d=16'b0000000000001000; sel=4'b0011;
#30 d=16'b0000000000010000; sel=4'b0100;
#30 d=16'b0000000000100000; sel=4'b0101;
#30 d=16'b0000000001000000; sel=4'b0110;
#30 d=16'b0000000010000000; sel=4'b0111;
#30 d=16'b0000000100000000; sel=4'b1000;
#30 d=16'b0000001000000000; sel=4'b1001;
#30 d=16'b0000010000000000; sel=4'b1010;
#30 d=16'b0000100000000000; sel=4'b1011;
#30 d=16'b0001000000000000; sel=4'b1100;
#30 d=16'b0010000000000000; sel=4'b1101;
#30 d=16'b0100000000000000; sel=4'b1110;
#30 d=16'b1000000000000000; sel=4'b1111;
#50 $stop;
end
endmodule