EECS 413 Project

A Low Voltage Bandgap Reference Circuit with Current Feedback

Tao Li, Bhaskar Mitra, and Kabir Udeshi

AbstractThis paper describes the design of a bandgap reference, implemented in 0.25m CMOS technology. The circuit generates a reference voltage of 1.157V and has a temperature coefficient of 0.03mV/K at 27C. It can operate with supply voltages between 2.25V and 2.75V and between 0C and 85C. It has a PSRR of 59dB under normal operating conditions. This circuit works in a current feedback mode, and it generates its own reference current, resulting in a stable operation. A startup circuit is required for successful operation of the system.

II. CIRCUIT DESCRIPTION A reference voltage is generated by adding two voltages that have temperature coefficients of opposite sign with suitable multiplication constants. The resulting voltage obtained is independent of temperature. The diode voltage drop across the base-emitter junction, VBE, of a Bipolar Junction Transistor (BJT) changes Complementary to Absolute Temperature (CTAT) [1]. Whereas if two BJTs operate with unequal current densities, then the difference in the base emitter voltages, VBE, of the transistors is found to be Proportional to Absolute Temperature (PTAT). The PTAT relationship is given by [2], (1) V BE = VT ln m ; VT = kT / q where, k is Boltzmanns constant, T is the absolute temperature, q is the electron charge and m is the ratio of the current densities of the two BJTs. The PTAT voltage may be added to the CTAT voltage with suitable weighting constants to obtain a constant reference voltage. Figure 1 shows the block diagram of the badgap reference circuit designed. By using a supply independent current source, a current ISS is passed through BJT A. The same current ISS flows through m transistors connected in parallel, identical to A. Thus the current density of A is m times the current density of the m BJTs identical to A, connected in parallel. The voltages at node X and Y are maintained at the same value, VBE using a feedback network through a differential amplifier. This results in a voltage of VBE, across the resistor R. The voltages VBE and VBE are added to
Startup Circuit Supply Independant Current Source

NE of the essential building blocks of many analog circuits is a voltage reference, which should exhibit little dependence on supply and process parameters and a well defined dependence on temperature. For example, accurate biasing voltages are critical for many circuit schemes; in ADC, a reference voltage is required to quantify an input, while in DAC, it is required to define the output full-scale range. As a well-established reference generator technique, bandgap reference is most popular for both Bipolar and CMOS technologies. The principle of the bandgap circuits relies on two groups of diode-connected BJT transistors running at different emitter current densities. By canceling the negative temperature dependence of the PN junctions in one group of transistors with the positive temperature dependence from a PTAT (proportional-to-absolute-temperature) circuit which includes the other group of transistors, a fixed DC voltage which doesnt change with temperature is generated. This voltage is typically 1.26 volts, which is approximately the band gap of silicon. [3][4] There are many different implementation reported, while essentially a bandgap reference circuit consists of a supplyindependent biasing circuit, a diode connected BJT transistor generating a voltage with negative temperature coefficient, a PTAT circuit and some kind of feedback mechanism to improve the performance. In this work, a measurement and addition circuit is implemented to output the reference voltage. Current mirrors with current feedback mechanism are used to minimize supply dependence. Feedback mechanism is implemented by simple 2-stage single-ended differential amplifier. The circuit has been optimized for minimum temperature and supply dependence with simplest implementation.

I. INTRODUCTION

Iss X Delta VBE R1

Iss Y

VBE Measure & Add Voltages mA A

Fig. 1: Block diagram of Bandgap Reference Circuit.

EECS 413 Project

C p+

E p+

B n+ n-well

arrangement to generate the reference voltage while conserving voltage headroom. The circuit has a stable operating point at which no current to flows through it. An arrangement must be made to force the saturation when the supply is turned on. This function is carried out by the startup circuit. III. CIRCUIT ANALYSIS A. Bandgap Core The bandgap reference voltage is generated by adding the base emitter voltage, VBE, of a BJT to the difference in base emitter voltage, VBE, of BJTs with a ratio of current density m. In order to generate a stable circuit, it is necessary to keep the BJT in the exponential region. By simulating the transistor characteristics it was found that the minimum value of collector current that could be used is 10 A (Figure 4). By selecting a current density ratio of 8, and a minimum collector current of 12.5 A, we obtain a VBE of 52 mV using Equation 1. The total collector current is 100 A, which allows the resistor R1 to be in the order of hundreds of ohms. It would be difficult to implement a smaller value of resistance using the 0.25 m IBM process. The value of the resistor R1 is calculated buy dividing the voltage by the current and turns out to be a value of 465 (Equation 2). By setting R2 we determine the multiplication constant of the circuit. R2 is calculated using Equation 3 and turns out to be 4.65 K. The transistors in the circuit are sized to operate with a VDSAT of 0.4 V. We use the current equation [1] to determine the size of the current source transistors, TP1 and TP2. (4) 1 W 2 V DSAT I D = C OX 2 L
OPAMP

p-substrate
Fig. 2: pnp BJT using CMOS process..

obtain the reference voltage. The circuit also requires a startup circuit since there exists a stable state at which no current flows through the circuit. The startup circuit forces the transistors to turn on and the circuit to operate at its other stable state to generate the reference voltage. It should be noted that an ideal BJT is not available in CMOS technology. A pnp BJT is made using the n-well normally associated with a PFET [1] (Figure 2), the psubstrate behaving as the collector. In order to generate supply independent current and carry out an addition of the CTAT and PTAT voltages, the circuit in Figure 3 is used. The OPAMP provides the base voltage to the transistors which are connected as current mirrors. By selecting the value of R1 and current ISS, the circuit may be designed to operate at the desired operating point. The value of R1 is given by, (2) R1 = V BE / I SS Since the same current ISS flows through R2, the voltage at the output reference voltage nodes is given by, (3) R1 Vref = V BE + V BE . R2 Thus by selecting the value of R2 the weighting constant may be set. This arrangement provided an elegant
Startup Circuit Add CTAT and PTAT Voltages

Bandgap Core with supply independant current source VDD TP2 TP1 TP5

TN2

TP4

TP3

TP6

TN3

VBE.R2/R1 TN1 + VBE

Iss

Iss

Iss

TP7

TP8

TN7

R2

VBE

R1 VBE TN4 TN5 TN6

mA

Fig. 3: Schematic of Bandgap Reference Circuit showing the supply independent current source and generation of reference voltage..

EECS 413 Project

TABLE I DEVICE SIZES Component TP1,TP2, TP3, TP5, TP6 TP7, TP8 TP4 TN1, TN3 TN2 TN4, TN5 TN6, TN7 R1 R2 Value (m) 52/2 26/2 2/5 20/1 2/5 6.6/2 13/2 464 4.13 K

Fig. 4: The relation between the base-emitter voltage and the collector current of the BJT ceases to be logarithmic below about 10 A of collector current.

Where, ID is the drain current, is the mobility of the carriers, COX is the oxide capacitance per unit area, W is the width, and L the length of the transistors. The value of the W/L is 26. A length of 2 m was used to reduce the effect of channel length modulation. The dependence on the OPMAP gain may be reduced if channel length modulation is minimized. A longer channel also improves circuit symmetry making it less sensitive to process variation and giving it the ability to generate stable currents. In order to have the VBE of a BJT vary linearly with temperature, the collector current of the BJT must be constant. However, in the circuit used the collector current changes with temperature. The variation of VBE with temperature can be expressed using the relation [1], (5) V BE V BE ( 3 + m )VT Eg / q = T T Where, Eg is the bandgap voltage of the semiconductor material, q is the electron charge and T is the temperature in K. This relationship can be solved only numerically and is plotted in Figure 4. By using the analytical estimation we see that VBE does not change linearly with temperature. Using this relationship the estimation of change of the reference voltage with temperature is estimated to be 0.011 V over the temperature range from 300 to 385 K. (6) V V BE Vref = BE dT T T 300 K T B. OPAMP The OPAMP was used to maintain equal node voltages and provide a feedback to maintain the drain currents constant and insensitive to supply variations. A high gain of the OPAMP would result in better voltage tracking of nodes X and Y (Figure 1). The common mode voltages play an important role in determining the OPAMP topology. The input common mode was determined by the base emitter voltage of the BJT, which is 0.8 V at 100 A of collector current. In order to meet the input common mode condition an active current

mirror circuit with a PMOS driver was selected. The output common mode voltage corresponds to the gate voltage of the current mirror transistors. In order to have a VDSAT of 0.4 V for these transistors the output common mode should be ideally about 1.5 V. A second stage was added to the OPAMP to increase gain and shift the common mode voltage up by using an NMOS driver. The NMOS driver only provided an output common mode of about 0.4 V. By adding a diode-connected transistor, TN7, to the second stage, the output voltage was pushed up to about 1.3 V without any effect on the gain of the stage. The voltage drop accress the diode connected transistor is about 1.2 V corresponding to VTH + VDSAT. The gain of each of the stages of the OPAMP is given by (7) Av = gm .R O where, Av is the gain, gm is the transconductance of the driving transistor and RO is the effective output resistance at the output node. The gain of each stage is about 42; the differential pair with a non-inverting gain and the single stage with an inverting gain

Temperature (K)
Fig. 5: Analytical estimation of nonlinearity of rate of change of VBE with temperature.

C. STARTUP CIRCUIT Transistors TN1, TN2, TN3 and TP4 constitute the startup circuit. Initially all the transistors start off in off state. The voltage at the gate of TN1 is low and so it remains in off state. TP4 being diode connected is always on and so the transistor TN2 turns on forcing the drain to a low value. The current mirror stack turns on and the gate voltage of TN1 rises and it starts to conduct. At this point there is a competieion between the output of the amplifier TP6, and

EECS 413 Project TN2 for the current source load. TN2 is designed to be a weak transistor with W/L of 1/5 so the amplifier takes control of the current mirror gate. When the bandgap voltage is high enough ( ~1V) the transistor TN1 turns on. TN1 in linear region has to compete with TN2 in saturation so it is designed to be a big transistor. It draws all the current from TP2 and the base voltage of TN2 falls till it turns off. In this state the gate voltage at TN2 is about 0.6 V. This is high enough for the transistor TN1 to be conduct slightly. A diode connected transistor TN3 is added to increase the threshold voltage at the gate of TN3 to turn off. The transistor TP4 is designed to be a weak device so that low current flows through the parasitic path when the circuit is in full operation. IV. RESULTS The bandgap reference voltage gives a voltage of 1.1570V when adjusted to have a zero temperature coefficient at 27C. Figure 1, shows the result of the simulation. It can be adjusted to give a voltage of 1.26V, by sacrificing the zero temperature coefficient at 27C, but this leads to a much more degraded response. Figure 5, shows the result of the simulation. As can be seen an overall temperature coefficient of 0.1mV/K is obtained between 0C and 85C, which corresponds to about 0.5% variation. The response it worse for temperatures from 65-85C with a temperature coefficient of 0.2mV/K. Below these temperatures the temperature coefficient is 0.03mV/K.

Figure 7: Variation of the reference voltage with supply voltage at 27C

Figure 8 shows the a.c response. A PSRR of 59dB is obtained at d.c at the high frequency corner of 10Mhz, the PSRR starts to degrade ans is about 10dB for a frequency of abou 20Mhz. This problem can be solved by putting a 100pF capacitor between Vdd and ground to suppress the noise in Vdd. This would probably be done external to the chip as it is not feasible to put the supply bypass capacitor on-chip.

Figure 8: PSRR of the circuit at 27C

The D.C characteristics at 85degrees are shown in figure 9. The variation with Vdd is much worse in this case. The nominal value at 2.5V is still 1.1570V but at low Vdd it degrades to 1.100V, a 6%variation in voltage.
Figure 6: Variation of bandgap reference with temperature at Vdd=2.5V

Figure 7 shows the variation when the supply voltage is varied from 2.5V to 2.75V. The relative variation is 0.32%. at 27C. Even here the response shows a two fold characteristic. The response is much better in the high voltage range 2.2-2.75 than in the low voltage range (2.25V-2.4V). So the worst case operation of the device is at 85C and a supply voltage of 2.25V.

Figure 10, shows the PSRR of the circuit at 85C. It comes down from 60dB at 27C to about 30dB in this case. This degradation in characteristics is probably due to degradation in the gain of the amplifier, which increases the error voltage that needs to be sustained to drive the circuit.

EECS 413 Project VI. CONCLUSION

Figure 9: Variation with Supply Voltage at 85C (absolute worst case)

A bandgap reference with a current feedback mode has been designed. The circuit uses no external current sources and is designed to have a zero temperature coefficient at 27C. The design is implemented with 0.25m CMOS process and consumes very little headroom. The output voltage is 1.1570V at the nominal operating condition of 27C temperature and 2.5V supply voltage. It has a temperature coefficient of 0.03mV/K from 0-60C. It has a PSRR of 59dB and a large signal variation of 0.32% with Vdd under nominal operating conditions. The circuit performance degrades at higher temperatures and lower voltages. In the worst case corner of high temperature (85C) and low supply voltage (2.25V) the circuit puts out 1.100 volt, a 5% variation from the nominal value. TABLE 2: REFERENCE VOLTAGE OBTAINED UNDER DIFFERENT
SUPPLY VOLTAGES AND TEMPERATURES

27C 85C

2.5V 1.157V 1.156V

2.25V 1.1555V 1.100V

2.75V 1.1573V 1.157V

REFERENCES
Figure 10: PSRR at 85C [1] [2] B. Razavi, Design of Analog CMOS Integrated Circuits. New york, NY: 2001, ch 11. D. Hilbiber, A New Semicondictor Voltage Standard, IEEE J. of Solid-State Circuits, vol. 8, pp. 222-226, June 1973. Robert A. Pease, The Design of Band-Gap Reference Circuits: Trials and Tribulations, IEEE Proc. of the 1990 Bipolar Circuits and Technology Meeting, Minneapolis, Minnesota , Sept. 1990 K. Lasanen, V. Koorkala, etc., Design of A 1-V Low Power CMOS Bandgap Reference Based on Resistive Subdivision, IEEE 2002 T. Brooks and A.C Westwisk, A low power differential CMOS bandgap Reference, ISSCC Dig. Of Tech. Papers, pp 248-249, Feb 1994 K. Lasanen, et. Al, Design of a 1-V low power bandgap reference based on Resistive Subdivision, Proceedings of the 45th IEEE Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, USA, August 2002

V. LAYOUT Figure 9 shows the layout. The chip occupies a total area of . The chip has been optimized by combining all the FETs. Most of the area is taken up by the pnp transistors, so it cannot be optimized too much

[3] [4] [5] [6]

Figure 7: Layout of the bandgap reference circuit

. APPENDIX The simulation files are in /afs/engine.umich.edu/class/f03/eecs413/group3/bandgap/bandgap/concept_low_volt_test_sim