ECE 224, Fall 2016 Assignment Questions

Assignment 5. Analog Interfacing [96 marks total]

Q1) Ideal Operational Amplifiers (Op-Amps) [5 marks]

Name five characteristics of an ideal operational amplifier.

Q2) Inverting Operational Amplifier Circuit [5 marks]

Sketch an inverting operational amplifier circuit. Express the transfer function ( VVout
in
) for the circuit,
assuming the use of an ideal operational amplifier.

Q3) Integrating Operational Amplifier Circuit [5 marks]

Sketch an integrating operational amplifier circuit. Derive an expression for Vout (t).

Q4) Binary Weighted Resistor Ladder DACs [4 marks]

Consider the following 4 bit binary weighted resistor ladder DAC:

Vref
B3 R3

B2 R2

B1 R1 Rf

if
B0 R0
V-
- Vout
iin +
V+

GND

Figure 24: 4 Bit Binary Weighted Resistor Ladder DAC

a. If R0 has a value of 200 Ω, what should the values of R1 , R2 , and R3 be?

b. If Vref = 5 V and the operational amplifier may sink a maximum of 35 mA at its output, are the
resistor values suitable?

Q5) R-2R Ladder DAC [2 marks]

Why is an R-2R ladder DAC preferred over a binary weighted resistor DAC?

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ECE 224, Fall 2016 Assignment Questions

Q6) R-2R Ladder DAC Performance [15 marks]

Consider the following R-2R ladder DAC:

Vref
2R B3

R
2R B2

R 2R B1 R

R if
2R B0 iin
V-
- Vout
+
V+
2R

Figure 25: 4 Bit R-2R Ladder DAC

For the purpose of this question, assume that Vref = 5 V and the nominal resistance R = 1 kΩ. The
ladder circuit would have the currents and voltages illustrated in Figure 26.

5.000 V

5.000 mA

2 kΩ
5.000 V

2.500 mA
2.500 mA 1 kΩ

2 kΩ
2.500 V

1.250 mA
1.250 mA 1 kΩ

2 kΩ
1.250 V

0.625 mA
0.625 mA 1 kΩ

2 kΩ
0.625 V

0.313 mA
0.313 mA 2 kΩ

Req = 1 kΩ

Figure 26: Original 4 Bit R-2R Ladder DAC

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ECE 224, Fall 2016 Assignment Questions

The R-2R ladder DAC’s summed input currents (iin ) and output voltages (Vout ) are shown in Table 8.

Table 8: Currents and Voltages for R-2R Original Circuit

Bit Pattern Current (in mA) Voltage (in V)
0000 0.000 0.000
0001 0.313 0.313
0010 0.625 0.625
0011 0.938 0.938
0100 1.250 1.250
0101 1.563 1.563
0110 1.875 1.875
0111 2.188 2.188
1000 2.500 2.500
1001 2.813 2.813
1010 3.125 3.125
1011 3.438 3.438
1100 3.750 3.750
1101 4.063 4.063
1110 4.375 4.375
1111 4.688 4.688

a. How would the behaviour of the R-2R ladder DAC differ if all of the resistances increased by
exactly 10%?

b. How would the behaviour of the R-2R ladder DAC differ if all of the R resistances are increased
by 10%?

c. How would the behaviour of the R-2R ladder DAC differ if all of the 2R resistances are increased
by 10%?

Q7) DAC Selection [4 marks]

For a 0 V to 10 V DAC, which is the better choice, a 10 bit DAC with a differential non-linearity (DNL)
error of 0.05% full scale or a 12 bit DAC with the same error specification?

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ECE 224, Fall 2016 Assignment Questions

Q8) DAC Analysis [10 marks]

Suppose you have a 3 bit DAC with proportionality constant k = 81 .

a. What value of Vref should you use if you want the output of the DAC to be 1.4 V at full scale?

b. If the full scale output voltage is 1.4 V, what is the value of one LSB, in volts?

c. When testing your DAC, the following values were recorded:

Table 9: DAC Measured Outputs

DAC Input Measured Output (in V)
000 0.10
001 0.30
010 0.20
011 0.44
100 0.80
101 1.12
110 1.45
111 1.47

What is the value of the offset error (in V)?

d. Given the information in Part C, what is the differential non-linearity (DNL) error expressed in
LSB?

e. Given the information in Part C, what is the integral linearity error (ILE) expressed in LSB?

Q9) ADC Conversion Times [5 marks]

Complete Table 10 by indicating the number of iterations (or clock cycles) required to complete a single
data conversion. For each converter listed, assume a resolution of n bits.

Table 10: ADC Conversion Times

Converter Type Minimum Conversion Time Maximum Conversion Time
Binary Ramp
Successive Approximation
Flash
Single Slope
Dual Slope

Q10) Binary Ramp ADC [4 marks]

Assume you have a 3 bit binary ramp ADC that has a voltage reference Vref = −8 V.

a. What is the smallest input voltage that results in a full scale digital output (Bmax = (111)2 = 7)?

b. For Vin = 2.7 V, what is the binary code that is output by the binary ramp ADC?

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ECE 224, Fall 2016 Assignment Questions

Q11) Successive Approximation ADC [5 marks]

Suppose you are given a 4 bit successive approximation ADC that outputs 2 V at zero scale (Bmin =
(0000)2 = 0) and 17 V at full scale (Bmax = (1111)2 = 15). For Vin = 8.1 V, sketch the output of the
internal DAC during conversion of the input signal. What is the binary code that is output when the
conversion is complete?

Q12) ADC Clocking [2 marks]

Suppose the internal DAC that is used for a binary ramp ADC has a settling time of 5 ns for a change
of 1 LSB. What is the maximum clock frequency that can be used by the ADC?

Q13) Dual Slope ADC [6 marks]

A 4 bit dual slope ADC has R = 40 kΩ, C = 50 nF, Vref = −4 V, and clock frequency f = 8 kHz. The
input to the dual slope ADC is a time-varying signal. The input signal does not pass through a sample
and hold circuit.

a. For Vin = 2 V, sketch the output of the internal integrating operational amplifier circuit over time.
What binary code will be output from the ADC when the conversion is complete?

b. If Vin changes instantaneously from 2 V to 1 V at time 2.5 ms, what binary code will be output
from the ADC when the conversion is complete? (HINT: You may need to sketch the output of
the internal integrating operational amplifier circuit over time).

c. If Vin changes instantaneously from 2 V to 1 V at time 1 ms, what binary code will be output
from the ADC when the conversion is complete? (HINT: You may need to sketch the output of
the internal integrating operational amplifier circuit over time).

Q14) ADC Bias [5 marks]

For each of the converters indicated in Table 11, indicate whether the converter (as presented in the
lecture slides) biases high, low, or depends upon the implementation.

Table 11: ADC Bias

Converter Type Bias
Binary Ramp
Successive Approximation
Flash
Single Slope
Dual Slope

Q15) Sample and Hold [4 marks]

Suppose the maximum rate of change for a signal is 4 Vs , and it is to be sampled using a 10 bit 0 V to
10 V ADC. What is a suitable aperture time for the sample and hold to ensure that the signal does not
change by more than 14 LSB during the aperture time?

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ECE 224, Fall 2016 Assignment Questions

Q16) Analog Interfacing [15 marks]

An embedded system is to use a 16 bit successive approximation ADC that interfaces to a parallel port.
To stabilize the analog signal during conversions, a separate sample and hold circuit is used at the
input of the ADC. The output of the ADC provides persistent data. Draw a block diagram showing
the connections between the embedded system components. Write a C function to convert an analog
value into a digital value and then read the digital value. Use tight polling for synchronization. Make
any assumptions necessary to complete the design of the hardware and software systems.

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