Operating system

Vikram Verma
AP
PIET , Samalkha
 Syllabus

11/20/2022 Vikram Verma 2

 Books
Text Books:

1.Operating Systems , PP Choudhary by PHI Learning Pvt Ltd.

Reference Books:

1.Operating Systems : Internals and Design Principles, William

Stallings, Pearson

2.Operating System Concepts”, Abraham Silberschatz, Peter

Baer Galvin, and Greg Gagne, Wiley

11/20/2022 Vikram Verma 3

 Interaction with OS in Mainframe systems
• In a company's data processing centre, the mainframe serves
as the core data repository or hub.

• Users are connected to the mainframe through less powerful

devices such as workstations or terminals.

• Mainframe systems are used to support thousands of

applications, input devices, and output devices to serve and
support thousands of users simultaneously.

• Early mainframe systems were housed in enormous, room-

sized metal boxes or frames, which is probably how the
term mainframe originated.

11/20/2022 Vikram Verma 4

 Why centralizing the data?

• It is more likely that the data is up-to-date when it is

centrally stored in a single mainframe repository
because customers don't have to handle updates to
many copies of their company data.

• The distinction between centralized and distributed

computing, however, is rapidly blurring as smaller
machines continue to gain in processing power and
mainframes become ever more flexible and
multipurpose.

11/20/2022 Vikram Verma 5

 PSW
• How a CPU comes to know which instruction to execute next?

• How is this instruction located ?

• The answer is Program Status Word ( PSW)

• Program status word contains the information required for

proper program execution.

• PSWs are used to transfer control between problem programs

and the supervisory (system) program and to resume where
the program left off after an interruption.

11/20/2022 Vikram Verma 6

 PSW
• How a CPU comes to know which instruction to execute next?

• How is this instruction located ?

• The answer is Program Status Word ( PSW)

• 64 bit in length ( double word)

• 1st double word in main memory and occupying bytes 0 to 7

• Last 03 bytes contain next instruction address.

• As program is executed , PSW fields will go on changing

11/20/2022 Vikram Verma 7

 PSW format

Channel Key AMWP Interrupt ILC CC Prog Inst

Mask code Mask Address
8 4 4 16 2 2 4 24
0-7 8-11 12-15 16-31 32-33 34-35 36-39 40-63

11/20/2022 Vikram Verma 8

 Fields of PSW – Channel Mask
Channel Mask : Also known as system mask

– 8 bit from 0 to 7

– Each bit is associated with interrupting device

– Bits 0-6 enable 0-6 channels

– Bit 7 : enable timer , interrupt key , external signal

– If the bit is ON (1 )then associated source may cause interrupt

– If the bit is 0 then associated source may cause interrupt

• Ex 01110000 would permit I/O interrupts only from selector

channels 1-3
11/20/2022 Vikram Verma 9
 Fields of PSW – Key
Protect Key:

– 4 bit from 8 to 11

– Main memory is allocated to individual programs in 2K byte

blocks.

– In multi programming there is a possibility that one program

destroys or modifies another . To avoid this IBM devised the
memory protection which is activated through “key”.

– The same “key” is assigned to all blocks associated with the

same program

11/20/2022 Vikram Verma 10

 Fields of PSW – AMWP
AMWP:

– 4 individual bits from 12 to 15

ASCII mode : OFF its EBCDIC , ON it is ASCII mode

Machine check : Enables / disables Machine check interrupts

Wait state : When OFF, CPU running ; When ON, CPU in

wait state

Problem state : OFF , supervisor mode ; ON , User mode i.e

prevent the use of instructions reserved for supervisor state.

11/20/2022 Vikram Verma 11

 OS and interrupt

• An operating system is basically

an interrupt driven program .

• If nothing is required of the

computer system, the OS
remains silent and idles in main
memory.

11/20/2022 Vikram Verma 12

 PSW format
Channel Key AMWP Interrupt ILC CC Prog Inst
Mask code Mask Address
8 4 4 16 2 2 4 24

0-7 8-11 12-15 16-31 32-33 34-35 36-39 40-63

• Channel mask : Each bit channel mask is associated with interrupting device

• In multi programming there is a possibility that one program destroys or

modifies another . To avoid this the memory protection “key”.

• AMWP : ASCII mode , Machine check , Wait state , Problem state

11/20/2022 Vikram Verma 13

 Fields of PSW – Interrupt Code
CPU goes through 02 distinct steps
a) fetch cycle
b) execution cycle.

Following sequence of operations :

1. Find instructions address stored in PSW
2. Get the instruction from that address
3. Increment the instruction address by the length of current
instruction – it now points to the new instruction
4. Decode instruction
5. Enter execution cycle
6. Go back to step 1

11/20/2022 Vikram Verma 14

 Fields of PSW – Interrupt Code

Interrupt code:

– 16 bits from 16 to 31

A CPU interrupt code is a code sent by software or hardware to CPU

to suspend the execution of all processes until the process requested
in the interrupt is complete.

In short it handles various unexpected interruptions / exceptions

11/20/2022 Vikram Verma 15

 Fields of PSW – ILC
Instruction length code :

– 02 bits ; 32 and 33

– It tells the length of current instruction

– The ILC is set, at the time of an interrupt, to 01 , 10 or 11 for 1,2

or 3 half-words depending upon the length of the last instruction

– The ILC is used to track back to the address of the currently

executing instruction should an error occur.

• Ex : if the instruction address in the old PSW is 3000 and the ILC setting
is 3 (binary 11), the op code of the last instruction executed before the
interrupt is located at address 2994 (i.e, 6 bytes less than the "next"
instruction address).

11/20/2022 Vikram Verma 16

 Fields of PSW – CC
Condition codes :

– 02 bits ; 34 and 35

– How does computer know whether to branch or not following a

conditional branch instruction ?

– A condition code is set after a comparison or arithmetic

instruction.

– This condition code is checked by the conditional branch

instruction, and if it meets the condition stated in the
instruction, the branch is executed.

11/20/2022 Vikram Verma 17

 Fields of PSW – Program mask
Program mask:

– 04 bits from 36 to 39

– These bits are set aside for particular programme exceptions

that occasionally aren't to be handled as programme checks.

– To prevent interruptions caused by these exceptions, the

corresponding program mask bits must be made zero, as follows:

MASK Bit PROGRAM EXCEPTION

36 Fixed-point overflow
37 Decimal overflow
38 Exponent underflow
39 Significance

11/20/2022 Vikram Verma 18

 Controlling I/O
• IO devices are slow as compared to CPU speed

• Channel is a small special purpose processor placed in between

I/O device and CPU

• Functions of Channel:
– Buffering
– Counting bytes
– Incrementing a main memory address

• Channel functions are performed in parallel with CPU

operations

11/20/2022 Vikram Verma 19

 Controlling I/O through channels
• There are 02 types of channels: selector and multiplexor.

• Selector channels are used for the attachment of high-speed

devices such as magnetic tapes, files, and drums.

• Multiplexor channels are intended primarily for low-speed devices

such as card readers , printer , punches etc .

11/20/2022 Vikram Verma 20

 Controlling I/O - Channel
• How does channel know what to do ?

• Where does the channel get its instructions?

• How does the channel know how many bytes to move ?

• Wherein the main memory can the data be found ?

• Where in main memory new data to be placed ?

• Channel communicates through 03 fields : CAW , CSW and

CCW

11/20/2022 Vikram Verma 21

 Input / Output Operation Initiation
• Commands constitute the channel program.

• The channel programs are held in main storage until an I/O operation is
initiated by a START I/O instruction.

• If the necessary channel and device facilities are available, START I/O is
accepted and the CPU continues its program.

• The channel independently governs the I/O device specified by the

instruction.

• Successful execution of START I/O causes the channel to fetch CAW from
the main-storage location 72.

• The CAW specifies the byte location in main storage where the channel
program begins.
11/20/2022 Vikram Verma 22
 Channel organization - CAW
Channel Address Word
– Fixed location in memory , byte address 72

– Contains the memory address of 1st CCW

– The channel program address is placed in CAW just prior to the

actual beginning of the I/O operation

– Following the initial contact , the channel keeps track on its own
of its next command

Channel CAW CCW1

CCW2
……..
11/20/2022 Vikram Verma 23
 CAW format

• Bits 0-3 specify the storage-protection key that will govern the
I/O operation.

• Bits 4-7 must contain zeros.

• Bits 8-31 specify the location of the first channel command word

Key 0000 CCW address

4 4 24

0 – 3 4 – 7 8 – 31

11/20/2022 Vikram Verma 24

 Channel organization - CCW
Each channel has its own program in main storage, and this program
must be initiated by the supervisory program.

Channel needs instruction to operate .

A channel program consists of series of CCW

CCW : Channel Command Word

Command Data Address Flags 000 Ignored Byte count

code
8 24 5 3 8 16

0-7 8-31 32-36 37-39 40-47 48 – 63

11/20/2022 Vikram Verma 25

 CCW

The 1st CCW is fetched during the execution of Start I/O.

Each additional CCW in the chain is obtained when the operation has
progressed to the point where the additional CCW is needed.

• Bits 0-7 specify the operation to be performed. There are 06

valid commands:
– Read Write Read Backward
– Control Sense Transfer In Channel

• The data address specifies the location of data in main storage. It

is the 1st location referred to in the area designated in the CCW

11/20/2022 Vikram Verma 26

 CCW
• Flag register indicates command modes.

• These flags serve to chain data or commands for series of CCW's,

interrupt the processing unit, skip a portion of a record, suppress
length indication, or terminate the operation.

• Flag register is updated with each new CCW

• Bits 37-39 must contain zeros.

• Bits 40-47 are ignored

• Bits 48-63 specify the number of bytes in the operation. The count
specifies the number of bytes for a data transfer operation.

11/20/2022 Vikram Verma 27

 Channel status Word ( CSW)
• Information relating to the status of a channel is passed to the
CPU through the CSW

Key 0000 Command Address Status Count

4 4 24 16 16
0 - 3 4 - 7 8 - 31 32-47 48 - 63
• Bits 0-3 contains the storage-protection key

• Bit 4-7 contain zeros.

• Bits 8-31 specify the location of the last CCW used.

• Bits 32-47 contain an I/O device-status byte and a channel status byte.
The status bytes provide such information as device busy , data check,
chaining check, control-unit end, etc.

• Bits 48-63 contain the residual count of the last CCW used.

11/20/2022 Vikram Verma 28

 Interrupt types

• IBM system / 360 has 05 distinct types of interrupts :

1. Machine check : It indicates that the self checking circuitry has

detected a H/W fault. If an instruction is executing and m/c
check occurs , the instruction is terminated,

2. External interrupt : It can come through 03 sources – a)

Operator’s console b) Another CPU / some other device c) The
timer. Prime importance is timer interrupt.

3. Supervisor call interrupt : The programmer does not control any

IO device but needs help of OS. The programmer links to this OS
module through supervisor call (SVC) interrupt

11/20/2022 Vikram Verma 29

 Interrupt types

IBM system / 360 has 05 distinct types of interrupts :

4. Program : A program interrupt is brought by programming error .

The CPU recognizes such errors and implements the appropirate
hardware function

5. Input/output interrupts : Channel and CPU work independently.

When a channel completes input or output or for some other
reason requires the attention of CPU an interrupt is sent

11/20/2022 Vikram Verma 30

 Interrupt concept

When an interrupt occurs the machine first determines the general

class of interrupts involved, and then proceeds to:

• Store the current PSW in the appropriate old PSW location.

• Fetch a new PSW from the appropriate location in and load it as

the current PSW. This new PSW "points" to the first instruction of
the interrupt-handling routine, which is part of the supervisory
control program.

• The interrupt routine now proceeds to analyze the cause of the

interrupt, stored in the old PSW location. and then takes the
appropriate action required for the type of interrupt involved.

11/20/2022 Vikram Verma 31

 Interrupt concept

• Depending on the cause of interrupt, this may consist of initiating

an I/O operation, branching to a “fixup routine" to correct the
problem, calling for a dump program, etc.

• After the interrupt has been taken care of, the instruction
sequence of the original problem program may be resumed from the
point of interruption, if desired. This is accomplished by the last
instruction (“Load PSW") of the interrupt-handling routine.

• The Load PSW instruction recalls the old PSW from its location in
storage and makes it again the current PSW; thus we are back in
the problem program.

11/20/2022 Vikram Verma 32

 Interrupt concept

11/20/2022 Vikram Verma 33

11/20/2022 Vikram Verma 34
 Interrupt Priority
• What happens if all the 05 interrupts hit the CPU simultaneously ?

• Machine check serviced 1st

• Program interrupt

• External interrupt

• I/O interrupt

11/20/2022 Vikram Verma 35

 Interrupt cycle
In computing environment 03 types of computing events may occur :

• Synchronous events ( synchronized by clock)

• An event whose occurrence is expected at some time in respect of

execution steps of program instructions . Ex arithmetic instruction .
On completion of execution , arithmetic processor causes an event
to inform CPU about the status and result of execution.

• Events whose occurrence are not expected . Ex S/w error such as

divide by zero

• Point 2 and 3 fall under asynchronous events.

11/20/2022 Vikram Verma 36

 Interrupt cycle
Two probable schemes to handle asynchronous events :

Software polling : Occurrence of asynchronous events checked through

programmed instructions. The CPU continuously checks the status of
the devices to find whether they require attention. This restricts
overlapping of I/O operations with CPU execution.

Interrupt scheme : This scheme sets an interrupt flag by the event.

The CPU recognizes the ON state of flag and switches over to the
execution of ISR ( Interrupt Service Routine).

11/20/2022 Vikram Verma 37

 System V IPC
• System V is one of the 1st commercial versions of the Unix OS.

• System V Release 4 (SVR4) was the most successful version

• Unix System V IPC package consists of three things

• Message Queues – allows processes to send formatted data

streams to arbitrary processes

• Shared memory - allows processes to share parts of their virtual

address space.

• Semaphores - allow processes to synchronise execution.

11/20/2022 Vikram Verma 38

 Message Queue
• A Message Queue is a linked list of message structures stored
inside the kernel’s memory space and accessible by multiple
processes

• Synchronization is provided automatically by the kernel

• New messages are added at the end of the queue

• Messages may be obtained from the queue either in a FIFO manner

(default) or by requesting a specific type of message (based on
message type)

• A process can create a new message queue, or it can connect to an

existing one.

11/20/2022 Vikram Verma 39

 Message Structs
• The kernel stores each message in the queue within the
framework of a structure

• Each message structure must start with a long message type:

struct mymsg {
long msg_type; /* type of message , represented by a +ve number */
char mytext[512]; /* rest of message */
int somethingelse;
float dollarval;
};
 Message Queue Limits
• Each message queue is limited in terms of both the maximum number
of messages it can contain and the maximum number of bytes it may
contain

• New messages cannot be added if either limit is hit (new writes will
normally block)

• On linux, these limits are defined as (in /usr/include/linux/msg.h):

– MSGMAX 8192 /*total number of messages */

– MSBMNB 16384 /* max bytes in a queue */
 How to connect to a queue
In order to create a new message queue , or access an existing queue
msgget ( ) system call is used
– int msgget (key_t key, int msgflg);
– Msgget () returns the message queue ID on success, or -1 on
failure
● Arguments

– key is a system-wide unique identifier describing the queue you

want to connect to (or create).
– Every other process that wants to connect to this queue will
have to use the same key.
– msgflg tells msgget ( ) what to do with queue in question. To
create a queue, this field must be set equal to IPC_CREAT bit-
wise OR'd with the permissions for this queue.