VLSI Design (21EL3101)

Course Coordinator

Dr. K. Venkata Ratnam

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CO - 1

TECHNOLOGY
INTRODUCTION

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i) Small Scale Integration:- (10-100) transistors => Example: Logic gates

ii) Medium Scale Integration:- (100-1000) => Example: counters

iii) Large Scale Integration:- (1000-20000) => Example:8-bit chip

iv) Very Large Scale Integration:- (20000-1000000) => Example:16 & 32 bit

v) Ultra Large Scale Integration:- (1000000-10000000) => Example: Special

processors, virtual reality machines, smart sensors

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 IC Technology

Moore’s Law
Definition: As Gordon Moore(one of the founder of Intel)
predicted in the early 1970s that number of transistors per chip
continued to double every one and half year or 18 months at the
same time dimension of the transistor is dropped down from
25µm in 1960 to 0.18µm in 2000

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Transistors integrated on a chip

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METAL OXIDE SEMICONDUCTOR (MOS) AND RELATED
VLSI TECHNOWGY
•For nMOS technology, the design methodology and the design rules are easily
learned, thus providing a simple but excellent introduction to structured design
for VLSI.

• nMOS technology and design processes provide an excellent background for

other technologies. In particular, some familiarity with nMOS allows a
relatively easy transition to CMOS technology and design.

• For GaAs technology some arrangements in relation to logic design are

similar to those employed in nMOS technology. Therefore, understanding the
basics of nMOS design will assist in the layout of GaAs circuits.

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Symbols for n-MOS and P-MOS

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Cont…

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• We have PMOS and nMOS transistors.
• They are Enhancement mode and Depletion mode of operation

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Mask Layout Encoding Styles for Different materials

BLUE

RED

GREEN

DARK YELLOW

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Accumulation

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Depletion Mode

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Inversion
http://www.kenfreed1.com/flash/mosfet1.html

After forming Channel

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Simulation

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 Enhancement mode Transistor
• In Enhancement mode transistor channel is going to form after giving a
proper gate voltage.

•If gate is connected to a suitable positive voltage with respect to the source,
then the electric field established between the gate and the substrate gives rise
to a charge inversion region in the substrate under the gate insulation and a
conducting path or channel is formed between source and drain.

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 n-Mos Depletion mode Transistor

• In Depletion mode transistor channel will be present by the implant. It can be

removed by giving a proper negative gate voltage.

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The application of a negative voltage of suitable magnitude  Vt between gate
and source will give rise to the formation of a channel (p-type) between the
source and drain and current may then flow if the drain is made negative with
respect to the source. In this case the current is carried by holes as opposed to
electrons.

In consequence, pMOS transistors are inherently slower than nMOS, since hole

mobility p is less, by a factor of approximately 2.5, than electron mobility n
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