Types of ASICs

 Full custom ASICs

 Stand cell based ASICs
 Gate array based ASICs
 Channeled gate arrays
 Channel less gate arrays
 Structured gate arrays

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Full custom ASICs

 In a full-custom ASIC an engineer designs some or all of the logic cells, circuits,or layout
specifically for one ASIC
 You may need to use full-custom design if the ASIC technology is new or so specialized that
there are no existing cell libraries or because the ASIC is so specialized that some circuits
must be custom designed.
 Fewer and fewer full-custom ICs are being designed because of the problems with these
special parts of the ASIC

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Stand cell based ASICs

 A cell-based ASIC (cell-based IC, or CBIC, pronounced sea-bick) uses predesigned logic
cells (AND gates, OR gates, multiplexers, and flip-flops, for example) known as standard
cells
 The standard-cell areas may be used in combination with larger predesigned cells, perhaps
microcontrollers or even microprocessors, known as megacells . Megacells are also called
mega functions, full-custom blocks, system-level macros (SLMs), fixed blocks, cores, or
Functional Standard Blocks (FSBs).
 The ASIC designer defines only the placement of the standard cells and the interconnect in a
CBIC

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Cont..

A Cell based ASIC(CBIC)

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Cont..

Routing path of the CBIC Dept of ECM

Gate-Array Based ASICs

 In a gate array (GA) or gate-array based ASIC the transistors are predefined on the silicon
wafer.
 The predefined pattern of transistors on a gate array is the base array or Primitive Cell
 Only the top few layers of metal, which define the interconnect between transistors, are
defined by the designer using custom masks.
 To distinguish this type of gate array from other types of gate array, it is often called a
masked gate array ( MGA ).
 The designer chooses from a gate-array library of predesigned and pre-characterized logic
cells.
 The logic cells in a gate-array library are often called macros

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 Cont..

There are the following different types of MGA or gate-array based ASICs:
Channeled gate arrays.
Channelless gate arrays.
Structured gate arrays.

There are two common ways of arranging the transistors on a MGA:

 In a channeled gate array we leave space between the rows of
transistors for wiring;
 The routing on a channelless gate array uses rows of unused
transistors
Channeled gate arrays
The important features of this type of MGA are:
 Only the interconnect is customized.
 The interconnect uses predefined spaces between rows of base cells.
 Manufacturing lead time is between two days and two weeks.
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Cont..

Channelless Gate Array

Fig shows a channelless gate array (also known as a channel-free gate array , sea-of-gates
array , or SOG array).
The important features of this type of MGA are as follows:
 Only some (the top few) mask layers are customized the interconnect.
 Manufacturing lead time is between two days and two weeks.
 The key difference between a channelless gate array and
channeled gate array is that there are no predefined areas set
aside for routing between cells on a channelless gate array

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Structured Gate Array

• An embedded gate array or structured gate array (also known as masterslice) combines
some of the features of CBICs and MGAs.
• One of the disadvantages of the MGA is the fixed gate-array base cell. This makes the
implementation of memory, for example, difficult and inefficient.
• In an embedded gate array we set aside some of the IC area and dedicate it to a specific
function.
• This embedded area either can contain a different base cell that is more suitable for building
memory cells, or it can contain a complete circuit block,such as a microcontroller.

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Cont..

 Fig shows an embedded gate array. The important features of this type of MGA are the
following:
 Only the interconnect is customized.
 Custom blocks (the same for each design) can be embedded.
 Manufacturing lead time is between two days and two weeks.

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 Programmable Logic Devices

A programmable logic device (PLD) die. The macro-

cells typically consist of programmable array logic
followed by a flip-flop or latch. The macro-cells are
connected using a large programmable interconnect
block.

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Comparison Between ROM,PLA and PAL

ROM PLA PAL

The Decoder(or AND The AND array The AND array
array) implements all implements a limited no implements a limited no
minterms of Product terms of Product terms
AND array is not AND array is AND array is
programmable programmable programmable
OR array is OR array is OR array is not
programmable programmable programmable
Additional inputs doubles Additional inputs does Additional inputs does
the size of AND and OR not require doubling of not require doubling of
array size size
It can implement SOP It can implement SOP It can implement SOP
with any no of terms with any no of terms with limited no of terms

Costlier than PAL Cheaper than PLA

Least flexible Extremely flexible Moderate flexible

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Macrocell

CLK OE

M O/P
U
X

I/P

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Macrocell

• Macrocell : the section of an SPLD which

implements one SOP output through a register is
known as a macrocell
• Macrocell consists AND-OR combinational logic
function and optional Flip-Flop
• The D Flip-Flop is edge triggered and changes state
on clock edge
• The output of Flip-Flop is connected to Mux which is
controlled by OE signal
• The output of Flip-Flop is fed back to the input of the
AND array

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Field Programmable Gate Array

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Cont..

 Fig illustrates the essential characteristics of an FPGA

 None of the mask layers are customized.
 A method for programming the basic logic cells and the interconnect.
 The core is a regular array of programmable basic logic cells that can
 implement combinational as well as sequential logic (flip-flops).
 A matrix of programmable interconnect surrounds the basic logic cells.
 Programmable I/O cells surround the core.
 Design turnaround is a few hours.

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ASIC Design Flow

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Cont..

 Design entry: Enter the design into an ASIC design system, either using a hardware
description language ( HDL ) or schematic entry .
 Logic synthesis: Use an HDL (VHDL or Verilog) and a logic synthesis tool to produce a
netlist a description of the logic cells and their connections.
 System partitioning: Divide a large system into ASIC-sized pieces.
 Prelayout simulation: Check to see if the design functions correctly.
 Floorplanning: Arrange the blocks of the netlist on the chip.
 Placement: Decide the locations of cells in a block.
 Routing: make the connections between cells and blocks
 Extraction: determine the resistance and capacitance of the interconnect
 Postlayout simulation: check to see the design still works with the added loads of the
interconnect
Steps 1-4 are part of logical design and steps 5-9 are part of physical design
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•
Economics of ASICs

• Comparison Between ASIC Technologies

• Product Cost
Total product cost = fixed product cost + variable product cost x products sold
ASIC fixed costs
Training cost
Hardware and software cost
Non Recurring Engineering(NRE) cost
Test-program development cost

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Cont..

ASIC variable costs

Wafer size
Wafer cost
Moore’s law
Gate density and utilization
Die size
Die per wafer
Defect density
Yield
Die cost
Profit margin
Price per gate
Part cost

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Difference between FPGA and ASIC

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A typical CAD System

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Objectives of CAD system

 Netlist extraction
 Technology mapping
 Placement
 Routing
 Static timing analysis

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Synthesis

Stages included in synthesis process

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Gate optimization
An accumulator circuit

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 Technology mapping

Different modes of FPGA Logic block

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Cont..

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Physical Design

Phases in physical design

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placement

The placement phase chooses a location on the target device for each logic
block in the technology-mapped netlist
An example of a placement result is given in Figure . It shows an array of
logic blocks in a small portion of an FPGA chip.
The white squares represent unoccupied blocks and the grey squares show
the placement of blocks that implement the circuit of Figure accumulator .
There is a total of 53 logic blocks in this circuit, including the technology
mapping circuit

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Cont..

Placement of a circuit

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Routing
Once a location in the chip is chosen for each logic block in a circuit, the routing phase
connects the blocks together by using the wires that exist in the chip

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Static timing analysis

After routing is complete the timing delays for the implemented circuit are known, because
the CAD system computes the timing delays of all blocks and wires in the chip.
A static timing analysis tool examines this delay information and produces a set of tables that
quantify the circuit’s performance.

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Some CAD tool products

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