1.

Memory-mapped I/O and Isolated I/O are two different addressing mapping techniques used in
computer system.
a. What is the difference between memory-mapped I/O and isolated I/O? [4 Marks]
Memory-mapped I/O - Single address space is used for both memory location and I/O devices.
Also same instructions are used to access both memory and I/O devices.
Isolated I/O - Address space for I/O is isolated from memory address space. Use memory r/w
and I/O command lines which specify whether the address refers to a memory location / an
I/O device.

b. List down 2 advantages and disadvantages of both methods. [6 Marks]

Memory mapped I/O Isolated I/O
Advantages 1. Efficient programming - Use same 1. The full range of addresses
instructions for I/O transfers or memory may be available for both.
transfers. 2. Programming is cleaner
2. Simple CPU architecture. compared to Memory mapped
3. No additional control lines are needed I/O.
on the bus to distinguish memory
commands from I/O commands.
4. Addressing is more flexible.
Examples: The various addressing
modes of the instruction set can be used,
and various registers can be used to
exchange data with I/O modules
Disadvantages 1. Memory-mapped I/O uses memory- 1. Programming is critical
reference instructions, which in most compared to memory mapped
machines are longer than I/O I/O technique.
instructions. The length of the program 2. Additional control lines are
therefore is longer. necessary on the bus to
2. The hardware addressing logic to the differentiate the memory
I/O module is more complex, because commands from I/O
the device address is longer. commands.

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 c. Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two
fields: the first byte contains the opcode and the remainder the immediate operand or an
operand address.
i. What is the maximum directly addressable memory capacity (in bytes)? [5 Marks]
No of bits used in operand address = 24
So directly addressable memory capacity = 224 bytes = 24 * 220 bytes = 16MB
ii. Discuss the impact on the system speed if the microprocessor bus has
1. a 32-bit local address bus and a 16-bit local data bus,
Because the address bus is 32 bit, the whole address can be transferred at
once and decoded in memory.
But the data bus is only 16 bits, so it will require 2 cycles to fetch a 32-bit
instruction or operand.
2. a 16-bit local address bus and a 16-bit local data bus. [10 Marks]
The 16 bits of the address placed on the address bus can't access the whole
memory. Thus a more complex memory interface control is needed to latch the
first part of the address and then the second part (because the microprocessor
will end in two steps).
For a 32-bit address, one may assume the first half will decode to access a
"row" in memory, while the second half is sent later to access a "column" in
memory. In addition to the two-step address operation, the microprocessor will
need 2 cycles to fetch the 32 bit instruction/operand.
iii. How many bits are needed for the program counter and the instruction register?
[5 Marks]
The program counter must be at least 24 bits. Typically, a 32-bit microprocessor will
have a 32-bit external address bus and a 32-bit program counter, unless on-chip
segment registers are used that may work with a smaller program counter. If the
instruction register is to contain the whole instruction, it will have to be 32-bits long; if
it will contain only the op code (called the op code register) then it will have to be 8 bits
long.

2. Interrupt Driven I/O is a technique used to perform I/O operations.

a. Once an I/O device completes an I/O operation, it sends interrupt signal to the processor.
Briefly explain the steps taken by the processor to handle this interrupt signal. [10 Mark]
i. Processor finishes execution of current instruction.
ii. It sends acknowledgement signal to interrupted I/O device.
iii. The processor pushes PSW(Program Status Word) and PC(Program Counter) onto
control stack.

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 iv. New PC value is loaded by the processor based on the interrupt received.
v. The processor saves remainder of process state information.
vi. Then the processor starts to process the interrupt and finishes it.
vii. Previously executed program process state information is restored back by the
processor.
viii. Further old PSW and PC values are restored and program execution is continued by
the processor.

b. Consider a system employing interrupt-driven I/O for a particular device that transfers data at
an average of 8KB/s on a continuous basis.
i. Assume that interrupt processing takes about 100 μs (i.e., the time to jump to the
interrupt service routine (ISR), execute it, and return to the main program). Determine
what fraction of processor time is consumed by this I/O device if it interrupts for every
byte. [10 Marks]
Time taken to transfer 8 KB of data by I/O device = 1s
Time taken to transfer 1 byte of data by I/O device = 1s / (8 * 1000) = 125 μs
So, time interval between an interrupt (t1) = 1s / 8000) = 125 μs
Time taken to process an interrupt (t2) = 100 μs
Processor time taken by the I/O device if it interrupts for every byte = t2/t1
= 100 μs / 125 μs
= 0.8
ii. Now assume that the device has two 16-byte buffers and interrupts the processor when
one of the buffers is full. Naturally, interrupt processing takes longer, because the ISR
must transfer 16 bytes. While executing the ISR, the processor takes about 8 μs for
the transfer of each byte. Determine what fraction of processor time is consumed by
this I/O device in this case. [10 Marks]
Time taken to transfer 1 byte of data by I/O device = 8 μs
Number of bytes transferred for an interrupt = 16 byte
So, time interval between an interrupt (t1) = 16 * 125 μs = 2000 μs
Time taken to process an interrupt (t2) = 100 + 8 * 15 μs = 220 μs
Processor time taken by the I/O device if it interrupts for every 16 byte = t2/t1
= 220 μs / 2000 μs
= 0.11

c. A particular system is controlled by an operator through commands entered from a keyboard.

The average number of commands entered in a 4 hour interval is 60.
i. Suppose the processor scans the keyboard every 100 ms. How many times will the
keyboard be checked in an 4 hour period? [7 Marks]