Application of Deep Learning in Back-End
Simulation: Challenges and Opportunities
Yufei Chen1 , Haojie Pei2 , Xiao Dong1 , Zhou Jin2 , Cheng Zhuo1∗
1 College of Information Science & Electronic Engineering, Zhejiang University, Hangzhou, China
2 College of Information Science and Engineering, China University of Petroleum, Beijing, China
∗ Email: czhuo@zju.edu.cn
Abstract—Relentless semiconductor scaling and ever increasing
device integration have resulted in the exponentially growing
size of the back-end design, which makes back-end simulation
very time- and resource-consuming. With the success in the
computer vision community, deep learning seems a promising
alternative to assist the back-end simulation. However, unlike
computer vision tasks, most back-end simulation problems are
mathematically and physically well-defined, e.g., power delivery
network sign off and post-layout circuit simulation. It then brings
broad interests in the community where and how to deploy deep
learning in the back-end simulation flows. This paper discusses
a few challenges that the deployment of deep learning models
in back-end simulation have to confront and the corresponding
opportunities for future research.
I. I NTRODUCTION
Relentless semiconductor scaling and ever increasing SoC
integration have imposed various challenges to the back-
end design from problem size to complexity [1]. In order
to understand how the design behaves when implemented
in physical layout, designers have to perform a back-end
simulation from the extracted view. With the smaller geometry
and increased number of transistors, back-end simulation has
observed fast growing circuit size and the exponential increase
in interconnect parasitics, which makes back-end simulation
extremely time- and resource-consuming [2].
As an essential step to validate system performance or
ensure chip sign off, back-end simulations can be roughly
categorized into linear and nonlinear simulations. For example,
power delivery network (PDN) sign off is to solve a huge
sparse linear system in the end, i.e., Ax = b, where A
is the system matrix with a significantly large portion of
zeros, b is the excitation vector, and x is the node voltage
vector to be solved [3]. In modern VLSI designs, such a
linear system can easily have billions of nodes with various
sparsity patterns [4], incurring significant computational and
memory overheads. Moreover, due to the varying test vectors,
i.e., excitations, the power delivery linear system needs to be
repeatedly simulated tens to even hundreds of times to ensure
power integrity, which makes power delivery sign off very
time consuming [4], [5]. Post-layout circuit simulation is a
common nonlinear simulation example for mixed-signal and
analog circuit verification [6]. Thanks to the growing parasitics
impact, it has become a huge risk to simply simulate the
schematic design without the layout parasitics. However, as
the SPICE simulation needs to go down to the transistor level
to replicate the exact model of circuit behavior, the nonlinear
circuit simulation, along with large parasitics network, may
take days to complete and have become a bottleneck to the
verification [7]. To address the inefficiency issues in back-end
simulators, researchers have proposed many physical-law or
heuristics based strategies from different modeling, ordering,
factorization, to solver, so as to handle the huge size of back-
end problems [7]–[9]. However, as the device non-linearity
continues grows and the number of parasitics exponentially
increases, the gains from many prior heuristics quickly fall
behind the demands of the back-end simulations [10].
On the other hand, the success of artificial intelligence (AI),
especially deep learning, in the computer vision tasks, has
brought broad interests in applying AI to back-end problems.
A recent example is Google’s Placer [11] using deep reinforce-
ment learning followed by heated discussions in both academia
and industry. It should be noted that, unlike many computer
vision problems, most back-end simulation problems already
have a theoretically sound mathematical and physical law-
based formulations [6]. This then brings a natural question on
the scope and effectiveness that deep learning techniques may
bring to the back-end simulations. Unlike many deep learning
based works on back-end physical design, e.g., placement and
routing, which are found to a promising alternative, there
are actually limited deep learning based back-end simulation
that can achieve both efficiency and generality [12]–[17]. For
example, a few prior works treated the power delivery noise
map as an image and used the convolutional neural network
(CNN) to estimate the IR drop [5], [12], [18]. While the
execution of CNN is faster than the linear system solver,
the training cost and generality are concerning and usually
limited to a particular scenario. Thus, although deep learning
is effective in addressing the large scale and non-linearity in
back-end simulations, the existing challenges from training,
model to generality still prevent its wide deployment in the
back-end simulation:
• Training: The deep learning model can be dedicated to
a particular design and scenario. The underlying training
cost from data collection to setup is often non-negligible.
Designers have to evaluate the implicit cost before the
deployment.
• Model: The back-end circuit or layout can be huge and
redundant. Domain knowledge is highly desired to select

Fig. 1. Traditional PDN sign off flow.
the proper learning architecture as a trade off between
efficiency and accuracy.
• Generality: Since the training and model design may
consume non-trivial efforts, the model generality is pre-
ferred but challenging in order to support different de-
signs, scenarios and even technologies.
In the following, we will first give a background review, and
then go into details with examples for the above challenges.
After that, we will conclude the paper and discuss the potential
research opportunities.
II. BACKGROUND
A. PDN Sign Off
Traditional PDN sign off involves multiple steps, from
parasitics extraction, timing analysis, power estimation, to
sparse linear system solve, as shown in Fig. 1 [4], [19].
The core problem of PDN sign off is to solve a sparse and
symmetric positive-definite matrix, which can be obtained
from the modified nodal analysis. In general, the complexity
of direct matrix solve is O(n3 ), where n is the number of
unknowns. Obviously, with the exponential increase in PDN
size with unknowns up to billions, even one direct matrix
solve is very time- and resource- consuming. Thus, both
academia and industry have spent significant efforts to reduce
the simulation cost of PDN sign off [3], [4], [20]–[23].
Recently, with the popularity of machine learning, there
were a few works that deployed various machine learning
di
techniques to accelerate the computation of L dt noise and
IR drop without actually invoking the sparse linear system
simulator [24]. For example, the work in [25] utilized deep
neural network (DNN) models, e.g., fully connected network
(FCN) and convolutional neural network (CNN), to predict
on-chip supply noise. In [18], the CNN model explicitly
used power map, layout, and power bump pattern as input
features to compute the full-chip static IR drop. The XGBoost
model was also considered as a promising alternative for
static IR drop prediction using structural and electrical features
extracted from PDN [13], [14], [17], [26]. On the other hand,
the dynamic noise can be more challenging as it needs to
incorporate more fine-grained local information, e.g., decap,
to compute the response to a time-varying input [5], [27]–
[29]. Thus, the network models have to rely on the regional
local model by dividing the global grids to smaller clips
and compute the dynamic noise of a clip within a particular
timing window [5], [27]. In addition to the analysis speed-
up, there are also a few papers that apply machine learning
to help power grid design and optimization [24], [30]–[34].
However, many of the prior works have to incorporate design-
dependent features such as location and timing information of
cells into power maps and hence make the solution dedicated
to a particular design.
B. Post-Layout Circuit Simulation
SPICE-like transistor-level circuit simulation plays an im-
portant role in verifying the core design indicators such as
accuracy, delay, power consumption, etc. Especially under
advanced processes, post-layout circuit simulation has become
one of the most time-consuming parts in the design flow
[35]. Given the exponentially increasing process complexity
and design integration density, machine learning, esp., deep
learning, has been considered as a promising alternative to
speed up circuit simulation [10], [15], [36].
Unlike the PDN sign off, which deals with one linear
system, post-layout circuit simulation needs to account for
both linear components from the parasitics and nonlinear
components from the transistors. The main task of post-layout
circuit simulation is to solve differential algebraic equations
(DAEs) established from the modified nodal analysis.Implicit
integration methods are then used to convert the differential
equations into difference equations [7]. After numerical dis-
cretization, a system of nonlinear algebraic equations needs to
be solved to obtain circuit state quantity at each time point.
Newton Raphson (NR) is a powerful approach to find solutions
of these nonlinear equations through linear approximation
due to its quadratic convergence property [37]. Therefore,
the main simulation problem is transferred to solve a series
of linear equations Ax = b at each NR iteration point.
The computational bottleneck of the entire simulation is the
solution of the Newton equation in the above iterative process,
which is to solve a series of large-scale sparse linear systems.
In the post-layout simulation, due to the increasingly serious
parasitic effects, the execution of sparse linear solvers may
account for 60-90% of the total simulation time [38]. Thus,
it is highly desired to develop machine learning techniques to
accurately predict and control the requested time-step size so
as to reduce the number of NR iterations [8] and accelerate
the sparse LU factorization [9] at each iteration, e.g. provide
selection of reordering algorithms to reduce fill-ins, etc.
Figure 2 shows the flow of transient analysis for post-layout
circuit simulation. Before solving the equations, RC reduction
[39] and circuit partitioning [40] are the two powerful tech-
niques to decrease the order of linear system to be solved.
Hypergraph partitioning, such as patoh [41], hmetis [42], et al.,
is commonly used to partition a large-scale circuit into small-
or medium-scale sub-circuits to facilitate parallel simulation
[8]. However, it is difficult to guarantee the load balance for
 Differential
Netlist MNA RCR/ ķ Nonlinear NR Linear
Parser KCL
algebraic
Partition equations equations
equations
Sparse LU
ĸ False decomposition Ĺ
ķTime discretization˄BE,Gear,etc˅
ĸDifferential equation iteration TRAN NR
True True False
ĹNewton-Raphson iteration Converge
converge? converge?

Fig. 2. Transient analysis flow for post-layout transistor level circuit simulation.

each thread during the parallel simulation. Moreover, the com-

ponents that may induce matrix singularity are usually placed
in the same sub-circuit, causing large coupling complexity and
hence low parallelism efficiency. Machine learning techniques
can then be utilized to enable more efficient circuit partitioning
and load balancing [43], [44].
A DC solve is always needed to provide an initial solution
to speed up the following transient simulation [45]. There
are several popular numerical iterative algorithms to solve the
system of nonlinear algebraic equations, including the basic
Newton-Raphson (NR) method and continuation methods like
Gmin stepping, source stepping, pseudo-transient analysis
(PTA), etc [46], [47]. The continuation methods are supposed
to be slower in speed but more robust than the plain NR. Its
convergence performance are determined by: (i) How to form
a continuation function; (ii) How to trace the solution curve;
and (iii) How to determine the initial solution [48]. Domain
experiences are then highly required to select the appropriate
parameters, where machine learning may help replace the
domain experiences and offer adaptive continuation iteration
for better convergence [15], [47].
III. A PPLICATION OF D EEP L EARNING IN BACK -E ND
S IMULATION
Though there are quite a few differences between linear
and nonlinear back-end simulations as reviewed in the last
section, they actually share similar bottlenecks when deploying
machine learning or deep learning techniques for speed up. We
can roughly divide the deployment of deep learning to three
stages: (i) training; (ii) model architecture; and (iii) model
generality. In the following, we will discuss the challenges of
deploying deep learning and the corresponding opportunities
for future work.
A. Training
The very first stage of any deep learning or machine learning
technique deployment is to decide the training dataset and
strategy. Most published deep learning techniques in back-
end simulation utilize a supervised strategy, i.e., deep learning
models are trained on a labelled dataset. The inference accu-
racy and model generality then largely depends on the quality
of annotation and the diversity of training data. In addition,
while a more complicated neural network architectures typi-
cally yield to more accurate prediction, its required training
set size can be also significantly increased to ensure the model
Fig. 3. Network architecture deployed in our experiment.
convergence. However, for back-end design, design houses are
usually unwilling to share such training data due to the IP and
privacy concerns. Then designers have to go through repeated
time-consuming simulations to collect sufficient training data,
which can only be used for one particular design. Moreover,
even if the quantity of data is resolved, we still need to resolve
the following issues to ensure the quality of the data:
• Insufficient labeled data It can be even more time-
consuming than the simulation to analyze and assign
the corresponding labels to each unlabeled data, which
demands both expertise and time.
• Data imbalance For back-end simulation, designers are
more concerned with the simulation results under the
worst case, e.g., worst case IR drop, which is however
very rare to invoke compared to the other regular cases.
Similar observations exist in post-layout circuit simula-
tion. When using deep learning to adaptively decide the
proper time step, most training data are collected from
the converged phase with larger time steps. However, the
samples representing the smaller time steps in the search
phase are more critical to the model but happen to be very
limited. Thus, the training data appears to be imbalanced
and possibly result in misleading inference.
In the following we present an experiment on how the data
imbalance may affect the inference accuracy. Here we follow
a similar strategy in [5] and design the network architecture
in Fig. 3 to classify whether static IR drop exceeds the
predefined threshold. Our experiment uses with the 2D design-
independent power map as the input and decides the hotspots
in the power grid. The case with hotspot is considered as
positive sample in the training set whereas the negative sample
refers to the IR drop lower than the threshold. Then, by
Fig. 4. Impact of data imbalance on inference accuracy and model prediction
behavior.
maintaining the same positive sample (or hotspot) percentage
in the test set, we change the ratio between the positive and
negative samples in the training set and evaluates its impact
on the inference. As shown in Fig. 4, the model tends to
report more positive cases with an increased positive rate in the
training set, while the inference accuracy is actually decreased
after certain knee point. Thus, when setting up the training set,
it is actually important to balance the positive and negative
samples to ensure a more robust model.
B. Model Architecture
Feature extraction is a crucial part of neural network model
architecture. A well-designed model only contains the nec-
essary information to reduce the unnecessary computational
overhead through feature extraction and selection. Thanks to
the huge dimension of the netlists in back-end simulation,
the input to the deep learning model can be huge, e.g.,
millions to billions, which incurs significant memory and time
consumption. It is then essential to control the input dimension
and only select the necessary features. Many prior works
rely on the manually selected features to reduce the input
size, which are always design-dependent and demand domain
knowledge [13], [14], [17], [26]. Recently, there are also a
few works that combine the domain knowledge with encoding
schemes to more adaptively select the desired features. For
example, to reduce the input dimension while maintaining the
essential information, PDN sign off can decompose the spatial
and temporal information as a pre-processing scheme [5], [12],
[16]. The underlying PDN layout can be spatially divided into
clips, the power map of which can then be further encoded
to reduce the redundant information. Zhou, et al., explores
various feature encoding schemes to reduce the dimension
of both input switching and circuit netlist [16]. As shown
in Fig. 6, the input switching can be modelled using 1D or
2D encoding to capture the register switching trace, while
the netlist can be modelled using graph based encoding.
Fig. 5 presents the trade-off between the inference accuracy on
PDN noise prediction and model complexity through different
feature extractions. It is observed that, even with 36% model
complexity reduction, we can still maintain very accurate pre-
Fig. 5. Impact of feature extraction on prediction accuracy and model
complexity
Fig. 6. Encoding schemes for input switching and netlist used in Primal [16]
(The Figure is from [16]).
diction with only 4% change. Thus, proper feature extraction
is critical to the efficiency of the deep learning model, but
always remain a challenging problem for different back-end
simulations.
C. Model Generality
The last challenge is the generality of the trained deep
learning model. A robust deep learning model can be trans-
ferred between different designs or even technologies, which
is crucial to the deployment of deep learning in the back-end
simulation. However, it is common in prior works that the
learned model is dedicated to a particular set of inputs, design
and technology. If we categorized the learned features from
the training set as specific and general features [49], where
the specific features are design-dependent and the general
features are universal, it is important to ensure the learned
model incorporate more general features than the specific
features. Researchers have spent various efforts improving
the learning of general features in back-end simulation. For
example, GRANNITE [50] adopted a graph neural network
(GNN) architecture to learn the general features from both
RTL simulation trace and input netlist, which is abstracted
as a graph to mitigate the design dependency. Chhabria, et
al., proposed a UNet-like structure to learn the universal
relationship between the selected features and IR Drops,
instead of directly predicting IR drop [18]. For sparse matrix
 TABLE I
C OMPARISON ON MODEL GENERALITY FOR DIFFERENT DESIGNS AND
SCENARIOS
D1 D2
S1 S2 S3 S1 S2 S3
Toggle Rate 20% 15% 25% 20% 15% 25%
Accuracy 96.46% 92.74% 93.29% 68.06% 66.85% 64.28%
computation, e.g. sparse LU factorization, sparse matrix-vector
multiplication (SpMV), etc., that are used in both PDN sign
off and post-layout circuit simulation [9], [38], [51], references
[52]–[55] suggested machine learning methods to select the
proper storage format and implementation kernels. While the
model is designed for the underlying mathematical formulation
without design details, it is not a trivial task to collect sufficient
data and train such a model applicable to all the circuits.
Since the inherent characteristics of industrial-scale circuits
are very complicated, the above techniques are more effective
when the design is with slight changes. We here use the
same IR drop prediction task and the network architecture in
Fig. 3 to demonstrate the problem of model generality. Table I
summarizes the results, where D1 and D2 refer to two different
power grid designs but supplying power to the same circuit
netlist; S1, S2 and S3 refer to three different scenarios or test
vectors to the circuit. The same test vector to the same circuit
may yield to the same excitation. However, thanks to different
power grid designs, the reported noise violations are different
from design to design and scenario to scenario. The original
model is trained on D1/S1 with 96.46% accuracy. While the
model can maintain good accuracy across different scenarios
(S1, S2, S3), the accuracy significantly drops when transferred
to the new power grid design (with the same circuit netlist).
IV. D ISCUSSIONS AND C ONCLUSIONS
In this paper, we discussed a few existing challenges of
deploying machine learning or deep learning models in back-
end simulation. While it is observed growing interest in deep
learning assisted back-end simulation, there are still many
practical issues that need to be addressed, as discussed in the
last section. Even with all the above issues, the popularity
of deep learning still open up many opportunities to the
back-end simulation area. For example, federated learning can
be a promising alternative to unify the data from different
design houses to resolve the issue of data insufficiency and
homogeneity while maintaining local data privacy [56]. While
many models demand very particular domain knowledge or
heuristics to design the proper model architecture, GNN can
be a natural option to properly model the circuit and input
stimulus, and then extract the intrinsic features of complex
circuits [57]. For the model generality, transfer learning has
been proposed to increase the generality, in which the features
in shallow layers can be adapted to other tasks [58].
However, despite all the new techniques, it is noted that the
back-end simulation is well formulated in mathematics. Very
few machine learning works attempt to theoretically assist
the underlying mathematical formulation and matrix solve,
as the overhead of which can be non-trivial in comparison
to the other speed-up techniques, such as parallel execution.
On the other hand, it seems more promising to apply deep
learning to the design or metric modeling so as to reduce
the back-end problem complexity, which demands domain
knowledge to achieve an efficient model. Moreover, since
back-end simulation plays a very critical role in chip sign off,
the model fidelity is important to provide designers with high
confidence in deploying the technique.
ACKNOWLEDGMENT
This work was supported in part by Zhejiang Provincial Key
R&D program (Grant No. 2020C01052), NSFC (Grant No.
62034007 and 61974133) and Science Foundation of China
University of Petroleum, Beijing (No. 2462020YXZZ024).
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