Reinforcement Learning-Driven Optimization for Superior

Performance, Power and Productivity in Chip Design

Thomas Andersen, PhD, Vice President, AI & ML

19 January 2022
Today’s Design - A Deluge of New Design Challenges

ELECTROMIGRATION POWER STA ROUTING PLACEMENT TRANSISTOR

& EXTRACTION & IR DROP COMPLEXITY RULES RULES ARCHITECTURE

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Using Data-Driven Techniques to Improve Visibility
Predictive models accelerate outcomes, already deployed and proven in production
Routability Critical Path ECO DRC Error
Prediction Prediction Prediction Classification

Actual

ML-based

Highly Dimensional SVM Multi Stage CNN Highly Dimensional SVM TensorFlow™

5X Accuracy vs. GR 2X Faster Opt 5X Faster ECO 2-3X Faster Fixing

and many more…

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Learning to play GO
DeepMind AlphaGo goes from zero to world champion in 40 days

How About Chip Design?

Can We Train Machines to Build Integrated Circuits?

Example: https://deepmind.com/blog/alphago-zero-learning-scratch/
© 2021 Synopsys, Inc. 4
A Closer Look at the Chip Design Process Today
Intelligent design processes
• Evaluate transistor Design Fixed Constraints
choices early in design
• Re-generate lib files PPA Metrics
TNS
Library Attributes TNS Design
Cell Design TNS
Timing, slew, Chip Design TNS Experiments
Std.
Layout power, etc WNS
Cells
WNS
WNS
WNS
Process Attributes Power
PDK Generation DRC Power
Metal stacks, Power
Process parasitics, spacing, Power
TLU+
etc Area
Area
Area
• Evaluate metal stack Area
choices early in design
• Re-generate tlu+ files
• Evaluate design space
Flexible Architecture Hierarchy parameters and
Feedback Constraints Choices Floorplan constructs/inputs
(ad-hoc)

© 2021 Synopsys, Inc. 5

AI Driven Design Space Optimization Loop AI
Uses reinforcement-learning to navigate the design-technology solution space

Tunable Inputs Faster Results

Target
Settings Flow Metrics
Reward Action

Design
Trade-offs
Constraints Hierarchy

Pareto
Process Library
State Algorithm Fronts

DSO.ai
© 2021 Synopsys, Inc. 6
DSO.ai – AI-driven Design Space Optimization
Uses machine-learning to navigate the combined design-technology solution space

Settings Chip Design: PPA Search

Area

Hierarchy Flow Manual

Auto

Process Constraints
Timing (TNS)

Manual PPA exploration: 100+ engineer-mo

Cells Automatic pareto front search: Few days
Better PPA

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DSO.ai Case Study – No Prior Learning
Successful search for better power
Timing vs. Power
Problem Statement:
Achieve lowest power while
Baseline keeping TNS

Design Parameter Space

• Design, tool, flow parameters
Power

• Library cell parameters

Best expert
result (manual)
Metrics (prioritized)
• Leakage
DSO.ai autonomously finds • TNS
30% better leakage solution
• Plus secondary (DRC etc)

Timing (TNS)
© 2021 Synopsys, Inc. 8
DSO.ai Case Study – With Prior Learning
Finding a result using prior learning

Timing Vs Power
Problem Statement:
Achieve lowest power while
keeping TNS

Design Parameter Space

• Design, tool, flow parameters
Power

• Library cell parameters

Best expert
result (manual)
Metrics (prioritized)
Previous best • Leakage
DSO.ai solution • TNS
• Plus secondary (DRC etc)
DSO.ai solution
using prior learning

Timing (TNS)
© 2021 Synopsys, Inc. 9
Design Space Optimization ‘Apps’
Plug-n-play exploration environments to further accelerate time to results with DSO.ai

SpaceWare Apps
Library Showcase
Powered by DSO.ai

Flow Opt. Library Opt. Dynamic Power

Tool settings, flow Cell selection Multi-bit strategies,
steps ICG point, activity
profiles, and more
Customized Optimized
Design Spaces Target Metrics Floorplanning Clock Space Path Grouping
Macro placement, Tree architecture, Explore path clustering
floorplan options cell selection, tap for better Fmax
points, and more

Plug-n-play Pre-configured Power Net V-Scaling DTCO

Flow Scripts User Interface PDN architecture, Vmin-Vmax voltage Metal stacks, cell
IR-drop exploration architecture, VT
classes
© 2021 Synopsys, Inc. 10
Operating Condition Optimization with DSO.ai (PVT, Library + Flow)

Frequency vs Power
Best manual
results
Power

Fmax

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Floorplan Optimization with DSO.ai for Area & Fmax

Floorplan Exploration (Die Size vs Frequency)

Die Size/Area

Highest
Frequency

Best tradeoff
Fmax
Smallest Die Size

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 Our Vision: A Complete AI-driven Design System
An autonomous design system that optimizes workflows across Synopsys platforms

Synopsys AI-driven Design System

Dashboards Design Apps Development API ML Models

CAD Team Project 1

Optimizers Trends

Project 2
Management
Cloud Connectors Learning System

Prior
Sessions

Statistical
IT Team Learnings Project N

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Thank You